Simple Scatterometry Structure for Si Recess Etch Control
Dimensions of structures in integrated circuits are shrinking with each new fabrication technology generation. Maintaining control of profiles of structures in transistors and interconnects is becoming more important to sustaining profitable integrated circuit production facilities. Measuring profiles of structures with many elements in integrated circuits, such as MOS transistor gates with recessed regions for Si—Ge epitaxial layers, is not cost effective for the commonly used metrology techniques: SEM, TEM and AFM. Scatterometry is technically unfeasible due to the number of elements and optical constants. The instant invention is a simplified scatterometry structure which reproduces the profiles of a structure to be profiled in a simpler structure that is compatible with conventional scatterometric techniques. A method of fabricating a transistor and an integrated circuit using the inventive simplified scatterometry structure are also disclosed.
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This invention relates to the field of integrated circuits. More particularly, this invention relates to metrology of advanced MOS structures in integrated circuits.
BACKGROUND OF THE INVENTIONAdvanced integrated circuits with MOS transistors commonly have gate and channel structures formed of multiple elements with complicated three-dimensional shapes. For example, transistors with silicon-germanium (Si—Ge) epitaxial elements typically etch silicon in the transistor substrate adjacent to the transistor gates to form trenches for subsequent growth of Si—Ge epitaxial material. Measurement and control of complex three-dimensional structures, such as MOS transistor structures in which source and drain regions have been etched after gate formation in preparation for selective epitaxial growth of germanium containing silicon, in a manufacturing environment is critical to maintaining electrical parameters such as transistor on-state drive currents and off-state leakage currents within specified limits for integrated circuits in high volume production. Commonly used metrology methods for measuring structures in integrated circuits have serious disadvantages for complex three-dimensional structures, for example, structures with undercut features. Top-down Scanning Electron Microscopy (SEM) lacks the resolution to provide detailed profile information. Transmission Electron Microscopy (TEM) is costly, slow and has limited sample size. Atomic Force Microscopy (AFM) profilometry is slow and has limited sample size. Other profilometry techniques are also slow, have limited sample sizes, and typically have insufficient resolution. Scatterometry has difficulty modeling structures with multiple elements such as the multiple gate spacer elements in advanced MOS transistors.
SUMMARY OF THE INVENTIONThis Summary is provided to comply with 37 C.F.R. §1.73, requiring a summary of the invention briefly indicating the nature and substance of the invention. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
A simplified scatterometry structure is disclosed which includes structures with features equivalent to a target structure in an integrated circuit, and which are simple enough to be profiled using known scatterometric techniques. Profiling etched regions for silicon-germanium epitaxial stress layers adjacent to MOS transistor gates is particularly suited to simplified scatterometry structures. A method of fabricating a transistor and an integrated circuit using the inventive simplified scatterometry structure are also disclosed.
The present invention is described with reference to the attached figures, wherein like reference numerals are used throughout the figures to designate similar or equivalent elements. The figures are not drawn to scale and they are provided merely to illustrate the invention. Several aspects of the invention are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide a full understanding of the invention. One skilled in the relevant art, however, will readily recognize that the invention can be practiced without one or more of the specific details or with other methods. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the invention. The present invention is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present invention.
It is desirable to measure profiles of structures such as MOS transistor gates in integrated circuits during fabrication of the integrated circuits. Moreover, it is desirable to perform the measurement quickly, inexpensively, and non-destructively, in order to minimize the impact of the measurement on workpiece flow in an integrated circuit manufacturing facility. The technique of scatterometry satisfies the requirements of speed, low cost and non-destructiveness, but an accurate scatterometry profile measurement of an arbitrary structure in an integrated circuit is not feasible because scatterometry technique requires a configuration with a plurality of structures to obtain an accurate measurement. A common approach to measuring profiles of structures in integrated circuits by scatterometry is to form replicas of the structure in a scatterometry module, in which a sufficient number of structures are placed to enable an accurate measurement. Accurate measurements by scatterometry require accurate values of dimensions and optical properties such as indices of refraction and absorption coefficients of all elements in the structure to be measured. In the case of etched regions adjacent to MOS transistor gate structures, the number of elements in the MOS transistor gate structures and uncertainty in the values of the optical properties of the elements precludes an accurate profile measurement by conventional scatterometry. The instant invention proceeds by fabricating structures in a scatterometry module which reproduce the features of a structure to be measured, for example, an etched region adjacent to an MOS transistor gate structure, but have significantly fewer elements to the point of enabling an accurate profile measurement by scatterometry. The instant invention is a simplified scatterometry structure, and will be referred to as such in this disclosure.
In another embodiment of the instant invention, profiles of structures in interconnect regions of integrated circuits may be estimated by forming simplified structures that reproduce features of interest, such as interconnect trench sidewalls or metal interconnect lines, in a simplified scatterometry structure, and measuring the simplified scatterometry structure using known scatterometric techniques.
In a further embodiment, profiles of structures in micro-electronic-mechanical systems (MEMS) devices may be estimated by forming simplified structures that reproduce features of interest, such as cantilever structures, in a simplified scatterometry structure, and measuring the simplified scatterometry structure using known scatterometric techniques.
Claims
1. A simplified scatterometry structure for estimating a profile of an etched lateral surface of a target structure, comprising:
- provided a substrate;
- a plurality of etch blocking elements over a top surface of said substrate, in which a plurality of the etch blocking elements are configured in a linear array of constant separation between adjacent etch blocking elements;
- a plurality lateral surfaces of etched regions adjacent to said etch blocking elements.
2. The simplified scatterometry structure of claim 1, in which said etch blocking elements are comprised substantially of silicon dioxide.
3. The simplified scatterometry structure of claim 2, in which:
- said target structure is an MOS transistor gate structure; and
- said etch blocking elements have a same lateral size as said MOS transistor gate structure.
4. The simplified scatterometry structure of claim 3, in which said etched regions contain silicon-germanium epitaxial material.
5. The simplified scatterometry structure of claim 1, in which said etch blocking elements are comprised substantially of silicon nitride.
6. The simplified scatterometry structure of claim 1, in which said etch blocking elements are comprised substantially of photoresist.
7. The simplified scatterometry structure of claim 1, in which said etch blocking elements are comprised substantially of polycrystalline silicon.
8. The simplified scatterometry structure of claim 1, in which:
- said target structure is a trench for an interconnect line;
- said etch blocking elements have a same lateral separation as a lateral width of said interconnect line.
9. A method of forming an MOS transistor in an integrated circuit, comprising the steps of:
- providing a first integrated circuit;
- forming a simplified scatterometry structure in said first integrated circuit, comprising the steps of: forming a plurality of etch blocking elements in said first integrated circuit, in which a plurality of the etch blocking elements are configured in a linear array of constant separation between adjacent etch blocking elements; and etching regions in said first integrated circuit adjacent to said etch blocking elements;
- measuring a profile of said regions adjacent to said etch blocking elements using scatterometric techniques and outputting profile measurement data;
- providing a second integrated circuit;
- forming said MOS transistor in said second integrated circuit, further comprising the step of adjusting parameters of an etch process for said MOS transistor using said profile measurement data.
10. The method of claim 9, in which said etch blocking elements are comprised substantially of silicon dioxide.
11. The method of claim 10, in which:
- said MOS transistor further comprises an MOS transistor gate structure; and
- said etch blocking elements have substantially a same lateral size as said MOS transistor gate structure.
12. The method of claim 11, in which the step of forming said MOS transistor further comprising the steps of:
- etching stress regions in said second integrated circuit adjacent to said MOS transistor gate structure; and
- forming a layer of silicon-germanium epitaxial material in said stress regions.
13. The method of claim 1, in which said etch blocking elements are comprised substantially of silicon nitride.
14. The method of claim 1, in which said etch blocking elements are comprised substantially of photoresist.
15. The method of claim 1, in which said etch blocking elements are comprised substantially of polycrystalline silicon.
16. A method of forming an integrated circuit comprising the steps of:
- providing a first substrate;
- forming a simplified scatterometry structure in said first substrate, comprising the steps of: forming a plurality of etch blocking elements in said first substrate, in which a plurality of the etch blocking elements are configured in a linear array of constant separation between adjacent etch blocking elements; and etching regions in said first substrate adjacent to said etch blocking elements;
- measuring a profile of said regions adjacent to said etch blocking elements using scatterometric techniques and outputting profile measurement data;
- providing a second substrate;
- forming said integrated circuit in said second substrate, further comprising the step of adjusting parameters of an etch process for said integrated circuit using said profile measurement data.
17. The method of claim 16, in which said etch blocking elements are comprised substantially of silicon dioxide.
18. The method of claim 17, in which:
- the step of forming said integrated circuit further comprises the step of forming an MOS transistor in said second substrate;
- said MOS transistor further comprises an MOS transistor gate structure; and
- said etch blocking elements have substantially a same lateral size as said MOS transistor gate structure.
19. The method of claim 18, in which the step of forming said MOS transistor further comprising the steps of:
- etching stress regions in said second integrated circuit adjacent to said MOS transistor gate structure; and
- forming a layer of silicon-germanium epitaxial material in said stress regions.
20. The method of claim 16, in which:
- the step of forming said integrated circuit further comprises the step of forming a trench for an interconnect line; and
- said etch blocking elements have a same lateral separation as a lateral width of said interconnect line.
Type: Application
Filed: Mar 14, 2008
Publication Date: Jun 25, 2009
Patent Grant number: 9006001
Applicant: TEXAS INSTRUMENTS INCORPORATED (Dallas, TX)
Inventors: Vladimir Alexeevich Ukraintsev (Allen, TX), Craig Lawrence Hall (Allen, TX)
Application Number: 12/049,028
International Classification: H01L 29/78 (20060101); H01L 21/66 (20060101);