Chemical Etching Patents (Class 438/8)
  • Patent number: 10290553
    Abstract: Provided is a method for determining and utilizing process completion of post heat treatment (PHT) of a dry etch process, the method comprising: providing a substrate in a process chamber, the substrate having a film layer and an underlying layer, the film layer having one or more regions; performing a dry etch process to remove the film layer or region of the film layer, the dry etch process generating a byproduct layer; measuring one or more properties of the byproduct layer; adjusting the PHT process based on the measured one or more properties of the byproduct layer; and performing the PHT process to remove the byproduct layer on the substrate; wherein the PHT process utilizes a real time in-situ process to concurrently determine when removal of the byproduct layer is complete.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: May 14, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Jacob Theisen, Aelan Mosden
  • Patent number: 9824852
    Abstract: A Critical Dimensions Scanning Electron Microscope (CD-SEM) is described that comprises a unit for performing CD-SEM measurements of a semiconductor wafer, a BSE imaging unit for obtaining a Grey Level image (GL) of the wafer, and a unit for GL analysis and for processing the GL analysis results with reference to results of the CD-measurements.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: November 21, 2017
    Assignee: Applied Materials Israel Ltd
    Inventors: Roman Kris, Yakov Weinberg, Yan Ivanchenko, Ishai Schwarzband, Dan Lange, Arbel Englander, Efrat Noifeld, Ran Goldman, Ori Shoval
  • Patent number: 9607910
    Abstract: A method of controlling polishing includes polishing a region of a substrate at a first polishing rate, measuring a sequence of characterizing values for the region of the substrate during polishing with an in-situ monitoring system, determining a polishing rate adjustment for each of a plurality of adjustment times prior to a polishing endpoint time, and adjusting a polishing parameter to polish the substrate at a second polishing rate. The time period is greater than a period between the adjustment times and the projected time is before the polishing endpoint time. The second polishing rate is the first polishing rate as adjusted by the polishing rate adjustment.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: March 28, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Dominic J. Benvegnu, Benjamin Cherian, Sivakumar Dhandapani, Harry Q. Lee
  • Patent number: 9502261
    Abstract: A method includes forming a first material layer on a substrate and performing a first patterning process using a first layout to form a first plurality of trenches in the first material layer. The method further includes performing a second patterning process using a second layout to form a second plurality of trenches in the first material layer, wherein the second layout a cut pattern for the first layout. The method further includes forming spacer features on sidewalls of both the first and second pluralities of trenches, wherein the spacer features have a thickness and the cut pattern corresponds to a first trench of the second plurality whose width is less than twice the thickness of the spacer features. The method further includes removing the first material layer; forming a second material layer on the substrate and within openings defined by the spacer features; and removing the spacer features.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: November 22, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ru-Gun Liu, Cheng-Hsiung Tsai, Chung-Ju Lee, Chih-Ming Lai, Chia-Ying Lee, Jyu-Horng Shieh, Ken-Hsien Hsieh, Ming-Feng Shieh, Shau-Lin Shue, Shih-Ming Chang, Tien-I Bao, Tsai-Sheng Gau
  • Patent number: 9219004
    Abstract: A method for obtaining a film made out of a first material on a polymer support, said method comprising bonding a first wafer to a second wafer, thereby defining a bonding interface between said first wafer and said second wafer, at least one of said first and second wafers comprising a layer of said first material situated in proximity to said bonding interface, in said first wafer, hollowing out a cavity, said cavity comprising a bottom parallel to said bonding interface that defines, in said first wafer, a bottom zone at a controlled distance relative to said second wafer, forming, in said cavity, a polymer layer on a thickness controlled from a bottom thereof to obtain a combined wafer portion, said combined wafer portion comprising a bottom zone formed by said polymer layer on said bottom and a peripheral zone, and eliminating said second wafer on a major portion of a thickness thereof, thereby releasing, beneath said polymer layer, a film comprising said layer of said first material.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: December 22, 2015
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Hubert Moriceau, Maxime Argoud, Christophe Morales, Marc Zussy
  • Patent number: 9214364
    Abstract: A substrate cleaning apparatus includes a supporting unit, provided in a processing chamber having a gas exhaust port, for supporting a substrate; one or more nozzle units, each for ejecting gas clusters to a peripheral portion of the substrate supported by the supporting unit to remove unnecessary substances from the peripheral portion; and a moving mechanism for changing relative positions of the supporting unit and the nozzle unit during ejecting the gas clusters. Each nozzle unit discharges a cleaning gas having a pressure higher than that in the processing chamber so that the cleaning gas is adiabatically expanded to form aggregates of atoms and/or molecules.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: December 15, 2015
    Assignees: TOKYO ELECTRON LIMITED, IWATANI CORPORATION
    Inventors: Kazuya Dobashi, Kensuke Inai, Akitaka Shimizu, Kenta Yasuda, Yu Yoshino, Toshihiro Aida, Takehiko Senoo
  • Patent number: 9153478
    Abstract: A method of forming a target pattern includes forming a first material layer on a substrate; performing a first patterning process using a first layout to form a first plurality of trenches in the first material layer; performing a second patterning process using a second layout to form a second plurality of trenches in the first material layer; forming spacer features on sidewalls of both the first plurality of trenches and the second plurality of trenches, the spacer features having a thickness; removing the first material layer; etching the substrate using the spacer features as an etch mask; and thereafter removing the spacer features. The target pattern is to be formed with the first layout and the second layout.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: October 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Gun Liu, Shih-Ming Chang, Ken-Hsien Hsieh, Ming-Feng Shieh, Chih-Ming Lai, Tsai-Sheng Gau, Chia-Ying Lee, Jyu-Horng Shieh, Chung-Ju Lee, Cheng-Hsiung Tsai, Tien-I Bao, Shau-Lin Shue
  • Patent number: 9087787
    Abstract: A process control monitor for determination of alignment between layers of a semiconductor structure includes a patterned layer having a plurality of lines formed on a base layer, the plurality of lines enclosed within a circle. A photo-resist layer is deposited on top of the base layer and over the patterned layer. The photo-resist layer may be patterned to include an opening that exposes a portion of the base layer adjacent the patterned layer and that exposes a portion of the patterned layer. Alignment between the patterned layer and the patterned photo-resist layer may be determined according to a contrast between the exposed portion of the base layer and the exposed portion of the patterned layer.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: July 21, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Osvaldo Buccafusca, Jim Roland, David Hartzell Leebrick
  • Patent number: 9054342
    Abstract: Provided are an apparatus and method for etching an organic layer, in which an organic material deposited in a non-layer forming area of a substrate is etched. The apparatus includes an etching chamber; a plasma generator configured to supply plasma into the etching chamber; a stage disposed in the etching chamber and configured to support the substrate; and a mask configured to guide the plasma toward the non-pixel area.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: June 9, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yoshiaki Sakamoto, Nam Ha
  • Publication number: 20150147829
    Abstract: A method of controlling polishing includes polishing a region of a substrate at a first polishing rate, measuring a sequence characterizing values for the region of the substrate during polishing with an in-situ monitoring system, determining a polishing rate adjustment for each of a plurality of adjustment times prior to a polishing endpoint time, and adjusting a polishing parameter to polish the substrate at a second polishing rate. The time period is greater than a period between the adjustment times and the projected time is before the polishing endpoint time. The second polishing rate is the first polishing rate as adjusted by the polishing rate adjustment.
    Type: Application
    Filed: November 27, 2013
    Publication date: May 28, 2015
    Applicant: Applied Materials, Inc.
    Inventors: Dominic J. Benvegnu, Benjamin Cherian, Sivakumar Dhandapani, Harry Q. Lee
  • Patent number: 9040315
    Abstract: A method for planarizing semiconductor devices, wherein the method comprises steps as follows: At least one patterned metal layer is formed on a substrate. A material layer having a first area and a second area is provided on the patterned metal layer and the substrate, in which there is a step height existing between the first area and the second area. A first polishing process having a first selection ratio of relative speeds for removing the material layer at the first area to that at the second area is then performed on the material layer. Subsequently, a second polishing process having a second selection ratio of relative speeds for removing the material layer at the first area to that at the second area is performed on the material layer, and the second selection ratio is greater than the first selection ratio.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: May 26, 2015
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Yi-Ching Wu, Tzu-Hung Yang, Chih-Chung Wu
  • Publication number: 20150140691
    Abstract: Systems and methods are provided for performing chemical-mechanical planarization on an article. An example system for performing chemical-mechanical planarization on an article includes a polishing head configured to perform a chemical-mechanical planarization (CMP) on an article, a polishing pad configured to support the article, a light source configured to emit an incident light, a polishing fluid including a plurality of emitter particles capable of emitting a fluorescent light in response to the incident light, a fluorescence light detector configured to detect the fluorescent light, and at least one processor configured to control the polishing head based on the detected fluorescent light.
    Type: Application
    Filed: November 19, 2013
    Publication date: May 21, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: I-SHUO LIU, HUI-CHI HUANG, JUNG-TSAN TSAI, CHIEN-PING LEE
  • Patent number: 9023666
    Abstract: The invention relates to a method for electron beam induced etching of a material (100, 200) with the method steps providing at least one etching gas at a position of the material (100, 200) at which an electron beam impacts on the material (100, 200) and simultaneously providing at least one passivation gas which is adapted for slowing down or inhibiting a spontaneous etching by the at least one etching gas.
    Type: Grant
    Filed: August 13, 2009
    Date of Patent: May 5, 2015
    Assignee: Carl Zeiss SMS GmbH
    Inventors: Nicole Auth, Petra Spies, Rainer Becker, Thorsten Hofmann, Klaus Edinger
  • Patent number: 9018023
    Abstract: An efficient method of detecting defects in metal patterns on the surface of wafers. Embodiments include forming a metal pattern on each of a plurality of wafers, polishing each wafer, and analyzing the surface of the metal pattern on each polished wafer for the presence of defects in the metal pattern by analyzing an optical across-wafer endpoint signal, generated at the endpoint of polishing. Embodiments include determining the location of defects in the metal pattern by determining the position of non-uniformities in the optical-across-wafer endpoint signal.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: April 28, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Mike Schlicker
  • Publication number: 20150111314
    Abstract: A method of polishing a substrate having a film is provided. The method includes: performing polishing of the substrate in a polishing section; transporting the polished substrate to a wet-type film thickness measuring device prior to cleaning and drying of the substrate; measuring a thickness of the film by the wet-type film thickness measuring device; comparing the thickness with a predetermined target value; and if the thickness has not reached the predetermined target value, performing re-polishing of the substrate in the polishing section prior to cleaning and drying of the substrate.
    Type: Application
    Filed: January 5, 2015
    Publication date: April 23, 2015
    Inventors: Takeshi IIZUMI, Katsuhide WATANABE, Yoichi KOBAYASHI
  • Publication number: 20150104887
    Abstract: A method of manufacturing a semiconductor device includes generating a mask layout of patterns in which the distance between adjacent ones of the patterns is equal to or less than a resolution of a lithography process, the patterns are apportioned among a plurality of masks such that in each of the masks the space between adjacent ones of the patterns is greater than the resolution, and a dual pattern is added to one of the masks. A semiconductor pattern is formed on a substrate using the mask(s) and the mask to which the dual pattern has been added. Patterns having a pitch equal to or less than the resolution may be formed on the semiconductor device.
    Type: Application
    Filed: May 23, 2014
    Publication date: April 16, 2015
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: JEE-EUN JUNG, KYOUNG-YUN BAEK, JEONG-HOON LEE
  • Patent number: 9005999
    Abstract: Methods for chemical mechanical polishing (CMP) of semiconductor substrates, and more particularly to temperature control during such chemical mechanical polishing are provided. In one aspect, the method comprises polishing the substrate with a polishing surface during a polishing process to remove a portion of the conductive material, repeatedly monitoring a temperature of the polishing surface during the polishing process, and exposing the polishing surface to a rate quench process in response to the monitored temperature so as to achieve a target value for the monitored temperature during the polishing process.
    Type: Grant
    Filed: June 30, 2012
    Date of Patent: April 14, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Kun Xu, Jimin Zhang, David H. Mai, Stephen Jew, Shih-Haur Walters Shen, Zhihong Wang, Thomas H. Osterheld, Wen-Chiang Tu, Gary Ka Ho Lam, Tomohiko Kitajima
  • Patent number: 9006867
    Abstract: A monitoring structure and a relevant monitoring method for the silicon wet etching depth are provided. The structure includes a wet etched groove formed on a monocrystalline silicon material with at least two top surfaces thereof being rectangular; and the top surface widths of the grooves are Wu and W1 respectively, Wu=du/0.71, and W1=du/0.71, where du is the maximum wet etching depth to be monitored, and d1 is the minimum of the wet etching depth to be monitored. The method includes: performing anisotropic wet etching on a monocrystalline silicon wafer according to a pattern with a monitoring pattern, forming an etched groove to be monitored and a structure for monitoring the depth of the groove, and then monitoring the structure to monitor the wet etching depth. The etching depth of the groove can be monitored with low costs, and a higher monitoring accuracy is obtained.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: April 14, 2015
    Assignee: CSMC Technologies Fabi Co., Ltd.
    Inventors: Xinwei Zhang, Changfeng Xia, Chengjian Fan, Wei Su
  • Publication number: 20150087084
    Abstract: The present invention provides a method of measuring a width of a color filter unit of a liquid crystal panel. The method includes providing a bottom glass substrate having a TFT array thereon; forming the color filter plate locating within an effective region of the liquid crystal panel by photo-etching process, and forming one or more measure modules locating of the liquid crystal panel and on the TFT array by the photo-etching process; and measuring widths of the one or more measure modules out of the effective region to obtain the width of the filter units within the effective region. The method provided is capable of effectively controlling widths of the color filter units formed in process of manufacturing the liquid crystal panel, thus quality of the liquid crystal panel is raised.
    Type: Application
    Filed: October 21, 2013
    Publication date: March 26, 2015
    Inventor: Jiwang Yuan
  • Publication number: 20150084057
    Abstract: A method for reducing the effects of cracks in an epitaxial film. The method includes; providing a semiconductor wafer with an epitaxial film thereon; inspecting the epitaxial film to determine outer peripheral edge regions of the epitaxial film having cracks therein; and selectively removing the determined outer peripheral edge regions of the epitaxial film while leaving portions of the semiconductor wafer underlying the removed determined outer peripheral regions of the epitaxial film.
    Type: Application
    Filed: September 20, 2013
    Publication date: March 26, 2015
    Applicant: Raytheon Company
    Inventor: Kelly P. Ip
  • Patent number: 8987843
    Abstract: A method and system to map density and temperature of a chip, in situ, is disclosed. The method includes measuring a propagation time that a mechanical propagation wave travels along at least one predefined path in a substrate. The method further includes calculating an average substrate density and temperature along the at least one predefined path as a function of the propagation time and distance. The method further includes determining a defect or unauthorized modification in the substrate based on the average substrate density being different than a baseline substrate density.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jerome L. Cann, David P. Vallett
  • Patent number: 8956886
    Abstract: In some embodiments, a method of controlling a photoresist trimming process in a semiconductor manufacturing process may include forming a photoresist layer atop a first surface of a substrate, wherein the photoresist layer comprises a lower layer having a first pattern to be etched into the first surface of the substrate, and an upper layer having a second pattern that is not etched into the first surface of the substrate; trimming the photoresist layer in a direction parallel to the first surface of the substrate; measuring a trim rate of the second pattern using an optical measuring tool during the trimming process; and correlating the trim rate of the second pattern to a trim rate of the first pattern to control the trim rate of the first pattern during the trimming process.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: February 17, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Samer Banna, Olivier Joubert, Lei Lian, Maxime Darnon, Nicolas Posseme, Laurent Vallier
  • Publication number: 20150044785
    Abstract: Embodiments described relate to a method and apparatus for reducing lithographic distortion. A backside of a semiconductor substrate may be texturized. Then a lithographic process may be performed on the semiconductor substrate having the texturized backside.
    Type: Application
    Filed: August 6, 2014
    Publication date: February 12, 2015
    Inventors: Carlos A. FONSECA, Anton DEVILLIERS, Benjamen M. RATHSACK, Jeffrey T. SMITH, Lior HULI
  • Patent number: 8945939
    Abstract: The invention is directed towards methods and compositions for identifying the amount of hydrofluoric acid in a buffered oxide etching composition. In buffered oxide etching compositions it is very difficult to measure the amount of hydrofluoric acid because it has varying equilibriums and it is toxic so it hard to handle and sample. When used to manufacture microchips however, incorrect amounts of hydrofluoric acid will ruin those chips. The invention utilizes a unique method of spectrographically measuring the hydrofluoric acid when in contact with added chromogenic agents to obtain exact measurements that are accurate, immediate, and safe.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: February 3, 2015
    Assignee: Ecolab USA Inc.
    Inventors: Amy M. Tseng, Brian V. Jenkins, Robert Mack
  • Patent number: 8946064
    Abstract: A method of forming a semiconductor device that includes providing a substrate including a semiconductor layer on a germanium-containing silicon layer and forming a gate structure on a surface of a channel portion of the semiconductor layer. Well trenches are etched into the semiconductor layer on opposing sides of the gate structure. The etch process for forming the well trenches forms an undercut region extending under the gate structure and is selective to the germanium-containing silicon layer. Stress inducing semiconductor material is epitaxially grown to fill at least a portion of the well trench to provide at least one of a stress inducing source region and a stress inducing drain region having a planar base.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Thomas N. Adam, Judson R. Holt, Alexander Reznicek, Thomas A. Wallner
  • Patent number: 8942842
    Abstract: A method of generating a library of reference spectra includes storing an optical model for a layer stack having at a plurality of layers, receiving user input identifying a set of one or more refractive index functions and a set of one or more extinction coefficient functions a first layer from the plurality of layers, wherein the set of one or more refractive index functions includes a plurality of different refractive index functions or the set of one or more extinction coefficient functions includes a plurality of different extinction coefficient functions, and for each combination of a refractive index function from the set of refractive index functions and an extinction coefficient function from the set of extinction coefficient functions, calculating a reference spectrum using the optical model based on the refractive index function, the extinction coefficient function and a first thickness of the first layer.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: January 27, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Jeffrey Drue David, Dominic J. Benvegnu, Xiaoyuan Hu
  • Patent number: 8940551
    Abstract: The present invention provides a method for monitoring a contact hole etching process of a TFT substrate, which includes: (1) providing a substrate having a first metal layer and a monitoring machine; (2) providing a target value of reflection rate of the substrate having the first metal layer; (3) applying a masking operation to patternize the first metal layer for forming a gate terminal; (4) forming a gate insulation layer on the gate terminal; and (5) forming a contact hole in the gate insulation layer through etching and simultaneously operating the monitoring machine to measure the reflection rate of a bottom of the contact hole, whereby when the reflection rate of the bottom of the contact hole is substantially equal to the target value, the etching operation is stopped. The variation of reflection rate of the metal layer is monitored to identify if the insulation layer is completely etched away.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: January 27, 2015
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventor: Xiangdeng Que
  • Patent number: 8936948
    Abstract: A hard mask, a protective film, which protects the hard mask film from oxidation, a first mask film and a first organic film are sequentially stacked. The first organic film is processed into a first pattern, and the first mask film is etched using the patterned first organic film as a mask. After the first organic film is removed, a second organic film is formed. The second organic film is processed into a second pattern. The first mask film is secondary etched using the patterned second organic film as a mask so that the surface of the first mask film is exposed but the surface of the protective film is not exposed, thereby selectively patterning only the first mask film. After that, when removing the residual second organic film by ashing, it is possible to ensure the function of the protective film that protects the hard mask film from oxidation.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: January 20, 2015
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Osamu Fujita
  • Publication number: 20150017745
    Abstract: A polishing method capable of preventing damage to a substrate is disclosed. The polishing method includes inspecting a periphery of a substrate for an abnormal portion, polishing the substrate if the abnormal portion is not detected, and not polishing the substrate if the abnormal portion is detected. The abnormal portion of the substrate may be an foreign matter, such as an adhesive, attached to the periphery of the substrate. After polishing of the substrate, the periphery of the substrate may be inspected again for an abnormal portion.
    Type: Application
    Filed: July 3, 2014
    Publication date: January 15, 2015
    Inventors: Toshifumi KIMBA, Keita YAGI
  • Patent number: 8932874
    Abstract: The invention is directed towards methods and compositions for identifying the amount of ammonium acid in a buffered oxide etching composition. In buffered oxide etching compositions it is very difficult to measure the amount of ammonium acid because it has varying equilibriums and it is toxic so it hard to handle and sample. When used to manufacture microchips however, incorrect amounts of ammonium acid will ruin those chips. The invention utilizes a unique method of spectrographically measuring the ammonium acid when in contact with added chromogenic agents to obtain exact measurements that are accurate, immediate, and safe.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: January 13, 2015
    Assignee: Nalco Company
    Inventors: Amy M. Tseng, Brian V. Jenkins, Robert M. Mack
  • Publication number: 20140377887
    Abstract: A method for planarizing semiconductor devices, wherein the method comprises steps as follows: At least one patterned metal layer is formed on a substrate. A material layer having a first area and a second area is provided on the patterned metal layer and the substrate, in which there is a step height existing between the first area and the second area. A first polishing process having a first selection ratio of relative speeds for removing the material layer at the first area to that at the second area is then performed on the material layer. Subsequently, a second polishing process having a second selection ratio of relative speeds for removing the material layer at the first area to that at the second area is performed on the material layer, and the second selection ratio is greater than the first selection ratio.
    Type: Application
    Filed: June 19, 2013
    Publication date: December 25, 2014
    Inventors: Yi-Ching WU, Tzu-Hung Yang, Chih-Chung Wu
  • Publication number: 20140367822
    Abstract: Systems and methods for dry eteching a photodetector array based on InAsSb are provided. A method for fabricating an array of photodetectors includes receiving a pattern of an array of photodetectors formed from InAsSb, the pattern including at least one trench defined between adjacent photodetectors, and dry etching the at least one trench with a plasma including BrCl3 and Ar.
    Type: Application
    Filed: June 17, 2013
    Publication date: December 18, 2014
    Inventor: Pierre-Yves Delaunay
  • Publication number: 20140370625
    Abstract: A method of etching including providing a plurality of nanostructures extending away from a support, the support comprising a dielectric layer located between the plurality of nanowires, forming a patterned mask over a first portion of the plurality of nanostructures, such that a second portion of the plurality of nanostructures are exposed and are not located under the patterned mask, etching the second portion of the plurality of nanostructures to remove at least a portion of the patterned mask and the second portion of the plurality of nanostructures, monitoring at least one gaseous byproduct of the etching of the plurality of nanostructures during the etching of the plurality of nanostructures and stopping the etching on detecting that the dielectric layer is substantially removed.
    Type: Application
    Filed: June 17, 2014
    Publication date: December 18, 2014
    Inventor: Daniel Bryce Thompson
  • Publication number: 20140361329
    Abstract: Conventional techniques are used to control the flux of an LED element, by modifying a surface of a light emitting element. One type of modification is roughening the surface, to enhance the light extraction efficiency. The degree of modification of the surface is controlled by controlling one or more of the parameters associated with the modification process. A given LED technology will have some minimum flux without modification and some maximum flux with optimal modification. By characterizing the relationship between the parameters of the modifying process and the resultant flux, the parameters of the modification process can be controlled to achieve a desired flux between the minimum and maximum flux achievable by the given LED technology.
    Type: Application
    Filed: January 29, 2013
    Publication date: December 11, 2014
    Inventors: Paul Scott Martin, Tiang Chuan Hng, Tomonari Ishikawa
  • Patent number: 8906709
    Abstract: Provided are methods of high productivity combinatorial (HPC) inspection of semiconductor substrates. A substrate includes two layers of dissimilar materials interfacing each other, such as a stack of a silicon bottom layer and an indium gallium arsenide top layer. The dissimilar materials have one or more of thermal, structural, and lattice mismatches. As a part of the inspection, the top layer is etched in a combinatorial manner. Specifically, the top layer is divided into multiple different site-isolated regions. One such region may be etched using different process conditions from another region. Specifically, etching temperature, etching duration and/or etchant composition may vary among the site-isolated regions. After combinatorial etching, each region is inspected to determine its etch-pit density (EPD) value. These values may be then analyzed to determine an overall EPD value for the substrate, which may involve discarding EPD values for over-etched and under-etched regions.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: December 9, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Khaled Ahmed, Frank Greer, George Mirth, Zhi-Wen Sun
  • Publication number: 20140346647
    Abstract: A monitoring structure and a relevant monitoring method for the silicon wet etching depth are provided. The structure includes a wet etched groove formed on a monocrystalline silicon material with at least two top surfaces thereof being rectangular; and the top surface widths of the grooves are Wu and Wl respectively, Wu=du/0.71, and Wl=du/0.71, where du is the maximum wet etching depth to be monitored, and dl is the minimum of the wet etching depth to be monitored. The method includes: performing anisotropic wet etching on a monocrystalline silicon wafer according to a pattern with a monitoring pattern, forming an etched groove to be monitored and a structure for monitoring the depth of the groove, and then monitoring the structure to monitor the wet etching depth. The etching depth of the groove can be monitored with low costs, and a higher monitoring accuracy is obtained.
    Type: Application
    Filed: November 20, 2012
    Publication date: November 27, 2014
    Inventors: Xinwei Zhang, Changfeng Xia, Chengjian Fan, Wei Su
  • Publication number: 20140345683
    Abstract: Provided are methods and systems for treating shunts on solar cell substrates. Also provided are solar cells including such substrates. A shunt detected on a substrate proximate to a metallized grid pattern is electrically disconnected from at least the bus portion of the grid, which reduces shunt's impact on performance on the solar cell. An antireflective layer may be disposed between the shunt and a portion of the grid extending over the shunt. The exposure pattern of a photoresist used to form the antireflective layer may be adjusted accordingly to achieve this result. In some embodiments, the metallized grid may be modified by adjusting the exposure pattern of a photoresist used to form this grid. The grid may be modified to avoid any contact between the grid and the shunt or to disconnect a portion of the grid contacting the shunt from the bus portion area of the grid.
    Type: Application
    Filed: May 24, 2013
    Publication date: November 27, 2014
    Applicant: The Boeing Company
    Inventors: Philip Chiu, Shoghig Mesropian, Dimitri D. Krut
  • Patent number: 8892568
    Abstract: A method of controlling polishing includes storing a library having a plurality of reference spectra, polishing a substrate, measuring a sequence of spectra of light from the substrate during polishing, for each measured spectrum of the sequence of spectra, finding a best matching reference spectrum using a matching technique other than sum of squared differences to generate a sequence of best matching reference spectra, and determining at least one of a polishing endpoint or an adjustment for a polishing rate based on the sequence of best matching reference spectra. Finding a best matching reference spectrum may include performing a cross-correlation of the measured spectrum with each of two or more of the plurality of reference spectra from the library and selecting a reference spectrum with the greatest correlation to the measured spectrum as a best matching reference spectrum.
    Type: Grant
    Filed: October 10, 2011
    Date of Patent: November 18, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Jeffrey Drue David, Dominic J. Benvegnu, Xiaoyuan Hu
  • Publication number: 20140315331
    Abstract: Candidate wet processes for native oxide removal from, and passivation of, germanium surfaces can be screened by high-productivity combinatorial variation of different process parameters on different site-isolated regions of a single substrate. Variable process parameters include the choice of hydrohalic acid used to remove the native oxide, the concentration of the acid in the solution, the exposure time, and the use of an optional sulfur passivation step. Measurements to compare the results of the process variations include attenuated total reflectance Fourier transform infrared spectroscopy (ATR-FTIR), contact angle, atomic force microscopy (AFM), scanning electron microscopy (SEM), and X-ray fluorescence (XRF). A sample screening experiment indicated somewhat less native oxide regrowth using HCl or HBr without sulfur passivation, compared to using HF with sulfur passivation.
    Type: Application
    Filed: March 11, 2014
    Publication date: October 23, 2014
    Applicant: Intermolecular, Inc.
    Inventors: Sandip Niyogi, Shuogang Huang, Chi-I Lang
  • Patent number: 8852967
    Abstract: A multiple channel site-isolated reactor system and method are described. The system contains a reactor block with a plurality of reactors. Input lines are coupled to each reactor to provide a fluid to the respective reactors. A sealing element associated with each reactor contacts a surface of a substrate disposed below the reactor block, which defines isolated regions on the surface of the substrate. A dissolution rate monitor extends into each reactor to monitor a rate of real-time dissolution of one or more layers on the surface of the substrate when it is disposed proximate to the surface of the substrate.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: October 7, 2014
    Assignee: Intermolecular, Inc.
    Inventor: George Mirth
  • Publication number: 20140273296
    Abstract: A method of controlling polishing of a substrate is described. A controller stores a library having a plurality of reference spectra. The controller polishes a substrate and measures a sequence of spectra of light from the substrate during polishing. For each measured spectrum of the sequence of spectra, the controller finds a best matching reference spectrum from the plurality of reference spectra and generates a sequence of best matching reference spectra. The controller uses a cell counting technique for finding the best matching reference spectrum. The controller determines at least one of a polishing endpoint or an adjustment for a polishing rate based on the sequence of best matching reference spectra.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: Applied Materials, Inc.
    Inventor: Kiran Lall Shrestha
  • Publication number: 20140273297
    Abstract: In some embodiments, a method of controlling a photoresist trimming process in a semiconductor manufacturing process may include forming a photoresist layer atop a first surface of a substrate, wherein the photoresist layer comprises a lower layer having a first pattern to be etched into the first surface of the substrate, and an upper layer having a second pattern that is not etched into the first surface of the substrate; trimming the photoresist layer in a direction parallel to the first surface of the substrate; measuring a trim rate of the second pattern using an optical measuring tool during the trimming process; and correlating the trim rate of the second pattern to a trim rate of the first pattern to control the trim rate of the first pattern during the trimming process.
    Type: Application
    Filed: March 11, 2014
    Publication date: September 18, 2014
    Applicant: APPLIED MATERIALS, INC.
    Inventors: SAMER BANNA, OLIVIER JOUBERT, LEI LIAN, MAXIME DARNON, NICOLAS POSSEME, LAURENT VALLIER
  • Patent number: 8828745
    Abstract: A method for manufacturing TSVs, wherein the method comprises several steps as follows: A stack structure having a substrate and an ILD layer (inter layer dielectric layer) is provided, in which an opening penetrating through the ILD layer and further extending into the substrate is formed. After an insulator layer and a metal barrier layer are formed on the stack structure and the sidewalls of the opening, a top metal layer is then formed on the stack structure to fulfill the opening. A first planarization process stopping on the barrier layer is conducted to remove a portion of the top metal layer. A second planarization process stopping on the ILD layer is subsequently conducted to remove a portion of the metal barrier layer, a portion of the insulator layer and a portion of the top metal layer, wherein the second planarization process has a polishing endpoint determined by a light interferometry or a motor current.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: September 9, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Wei-Che Tsao, Chia-Lin Hsu, Jen-Chieh Lin, Teng-Chun Tsai, Hsin-Kuo Hsu, Ya-Hsueh Hsieh, Ren-Peng Huang, Chih-Hsien Chen, Wen-Chin Lin, Yung-Lun Hsieh
  • Publication number: 20140242730
    Abstract: An optical model for a layer stack has a plurality of input parameters, the plurality of input parameters defining a parameter space. A plurality of model spectra are generated by calculating a model spectrum using the optical model for each of a first plurality of different points in the parameter space. A test spectrum of a test substrate is measured. For each model spectrum of the plurality of model spectra, the test spectrum is compared to the model spectrum to determine a difference value, thereby generating a plurality of difference values. A plurality of minima in the plurality of difference values are determined. Reference spectra can be generated clustered around points in the parameter space corresponding to a local minimum from the plurality of minima, or the local minimum can be used as a seed value in fitting the optical model to a measured spectrum.
    Type: Application
    Filed: February 27, 2013
    Publication date: August 28, 2014
    Inventor: Jeffrey Drue David
  • Publication number: 20140242731
    Abstract: A system and method for performing a wet etching process is disclosed. The system includes multiple processing stations accessible by a transfer device, including a measuring station to optically measure the thickness of a substrate, a controller to calculate an etch recipe for the substrate, in real time, and cause a single wafer wet etching station to etch the substrate according to the recipe. In addition, the system can measure the after etch thickness and calculate etch recipes, in real time, as a function of the final measurements of a previous substrate. The system can also include an in situ end point detection device for detecting the TSV reveal point while etching TSVs substrates. The system provides an automated solution to adjust etch recipe parameters in real time according to feedback concerning previously etched wafers and precisely control the TSV reveal height and etch duration using end point detection.
    Type: Application
    Filed: February 28, 2013
    Publication date: August 28, 2014
    Applicant: Solid State Equipment LLC
    Inventors: Laura Mauer, Elena Lawrence, John Taddei, Ramey Youssef
  • Patent number: 8808559
    Abstract: A method and apparatus for etching a photomask substrate with enhanced process monitoring, for example, by providing for optical monitoring at different regions of the photomask to obtain desired etch rate or thickness loss is provided. In one embodiment, the method includes performing an etching process on a reflective multi-material layer that includes at least one molybdenum layer and one silicon layer through a patterned mask, directing radiation having a wavelength from about 170 nm and about 800 nm to an area of the multi-material layer uncovered by the patterned mask, collecting an optical signal reflected from the area uncovered by the patterned mask, analyzing a waveform obtained from the reflected optical signal, and determining a first endpoint of the etching process when an intensity of the reflected optical signal is between about 60 percent and about 90 percent less than an initial reflected optical signal.
    Type: Grant
    Filed: July 8, 2012
    Date of Patent: August 19, 2014
    Assignee: Applied Materials, Inc.
    Inventor: Michael Grimbergen
  • Publication number: 20140196782
    Abstract: Disclosed is a method for yield enhancement of making a semiconductor device. The method for yield enhancement of making a semiconductor device comprises the steps of: providing the semiconductor device comprising an epitaxial layer including a defect; forming a dielectric layer on the epitaxial layer; detecting and identifying a location of the defect; and etching the dielectric layer and leaving a part of the dielectric layer to cover an area substantially corresponding to the detected defect. The semiconductor device made by the method is also disclosed.
    Type: Application
    Filed: January 10, 2014
    Publication date: July 17, 2014
    Applicant: EPISTAR CORPORATION
    Inventors: Yi Hung LIN, Yu Chih YANG, Wu Tsung LO
  • Patent number: 8772054
    Abstract: A method comprises providing a semiconductor substrate having at least one layer of a material over the substrate. A sound is applied to the substrate, such that a sound wave is reflected by a top surface of the layer of material The sound wave is detected using a sensor. A topography of the top surface is determined based on the detected sound wave. The determined topography is used to control an immersion lithography process.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: July 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jen-Pan Wang, Chien-Hsuan Liu, Ching-Hsien Chen, Chao-Chi Chen
  • Patent number: 8753896
    Abstract: A method of monitoring a surfactant in a microelectronic process is disclosed. Specifically, the monitoring of a surfactant occurs by studying the fluorescence or electromagnetic emission of a sample collected from a microelectronic process.
    Type: Grant
    Filed: April 5, 2007
    Date of Patent: June 17, 2014
    Assignee: Nalco Company
    Inventors: Brian V. Jenkins, John E. Hoots, Amy M. Tseng
  • Publication number: 20140147942
    Abstract: According to one embodiment, a memory device includes a nanomaterial assembly layer, a first electrode layer and a second electrode layer. The nanomaterial assembly layer is formed of an assembly of a plurality of micro conductors via gaps between the micro conductors. The first electrode layer is provided on the nanomaterial assembly layer. The second electrode layer is provided on the first electrode layer.
    Type: Application
    Filed: February 4, 2014
    Publication date: May 29, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenji AOYAMA, Kazuhiko YAMAMOTO, Satoshi ISHIKAWA, Shigeto OSHINO