Abstract: A substrate inspection device for inspecting a substrate, includes: a setting part configured to define a group according to a basic state that is not dependent on a presence or absence of a defect in a substrate and set the defined group for each inspection target substrate; an inspection part configured to perform a defect inspection based on a captured image of the inspection target substrate and an inspection recipe corresponding to the defined group to which the inspection target substrate belongs and including a reference image; a recipe creation part configured to create the inspection recipe for each group; and a determination part configured to perform a determination as to whether a group-setting target substrate, for which the group is set by the setting part, belongs to the group defined by the setting part.

Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.

Abstract: Embodiments of this application provide a method, an apparatus and a device for measuring a semiconductor structure. Before measurement of a to-be-measured semiconductor structure, a reference semiconductor structure corresponding to the to-be-measured semiconductor structure is set, and a first simulation model corresponding to the to-be-measured semiconductor structure and a second simulation model corresponding to the reference semiconductor structure are established, some structure parameters of the to-be-measured semiconductor structure have parameter values different from those of corresponding structure parameters of the reference semiconductor structure.

Abstract: There is provided a method for executing processing for a workpiece. The method includes a table imaging step of imaging a foreign object of a transparent part of a holding table having the transparent part composed of a transparent member at least in part of a holding surface and forming a foreign object taken image, a holding step of holding the workpiece by the holding table after executing the table imaging step, a workpiece imaging step of imaging the workpiece held by the holding table through the transparent part and forming a workpiece taken image, and a processing step of executing cutting for the workpiece held by the holding table by a cutting unit.

Abstract: A method for determining a contour of a semiconductor structure is disclosed, which includes: acquiring a best inclination angle of an electron beam; irradiating a sidewall of the semiconductor structure with the electron beam at the best inclination angle, to obtain a measured width of an orthographic projection of the sidewall of the semiconductor structure within a plane perpendicular to an incidence direction of the electron beam; and determining whether a bottom of the semiconductor structure is necked based on the measured width.

Abstract: Embodiments of the present disclosure generally relate to apparatus, systems, and methods for in-situ film growth rate monitoring. A thickness of a film on a substrate is monitored during a substrate processing operation that deposits the film on the substrate. The thickness is monitored while the substrate processing operation is conducted. The monitoring includes directing light in a direction toward a crystalline coupon. The direction is perpendicular to a heating direction. In one implementation, a reflectometer system to monitor film growth during substrate processing operations includes a first block that includes a first inner surface. The reflectometer system includes a light emitter disposed in the first block and oriented toward the first inner surface, and a light receiver disposed in the first block and oriented toward the first inner surface. The reflectometer system includes a second block opposing the first block.

Abstract: A substrate processing system is provided and includes a substrate support, a memory, and calibration, operating parameter, and solving modules. The substrate support supports a substrate and includes temperature control elements. The memory stores, for the temperature control elements, temperature calibration values and sensitivity calibration values. The calibration module, during calibration of the temperature control elements, performs a first calibration process to determine the temperature calibration values or a second calibration process to determine the sensitivity calibration values. The sensitivity calibration values relate at least one of trim amounts or deposition amounts to temperature changes. The operating parameter module determines operating parameters for the temperature control elements based on the temperature and sensitivity calibration values.

Abstract: A memory array includes a first memory cell configured to store data, a second memory cell configured to store data and a bit line extending along the first direction, and being over the first memory cell and the second memory cell. The first memory cell and the second memory cell are arranged along a first direction in a first column of memory cells. The bit line includes a first conductor extending in the first direction and being in a first conductive layer, and a second conductor extending in the first direction and being in a second conductive layer different from the first conductive layer.

Abstract: An inspection system (100) for inspecting a lighting device (150) during an assembly process of the lighting device; wherein the lighting device comprises a base plate (153) and a plurality of components (155) mounted on the base plate; wherein the inspection system comprises: a light source (120) arranged for illuminating the lighting device according to a first light output spectrum for providing a luminance contrast between the base plate and the plurality of components; an imaging unit/camera (130) arranged for capturing a first image of the illuminated lighting device; a controller (110) comprising a processing unit for determining a luminance contrast measure of the captured first image; wherein the processing unit is further arranged for, when the luminance contrast measure of the captured first image exceeds a threshold value, adapting the first light output spectrum, and wherein the imaging unit is further arranged for capturing a second image of the lighting device illuminated according to the adapt

Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip on a substrate, a barrier layer on the first semiconductor chip and the second semiconductor chip, the barrier layer having an opening through which at least a part of the first semiconductor chip is exposed, and a heat transfer part on the barrier layer, the heat transfer part extending along an upper face of the barrier layer and filling the opening.

Abstract: A product includes a semiconductor substrate, with at least first and second thin-film layers disposed on the substrate and patterned to define a matrix of dies, which are separated by scribe lines and contain active areas circumscribed by the scribe lines. A plurality of overlay targets are formed in the first and second thin-film layers within each of the active areas, each overlay target having dimensions no greater than 10 ?m×10 ?m in a plane parallel to the substrate. The plurality of overlay targets include a first linear grating formed in the first thin-film layer and having a first grating vector, and a second linear grating formed in the second thin-film layer, in proximity to the first linear grating, and having a second grating vector parallel to the first grating vector.

Abstract: An imprint device includes a load port for receiving a substrate to be processed, a sensor that acquires information from the substrate about a film on the substrate, and a primer forming unit configured to receive the substrate from the load port. A controller is configured to select primer process conditions corresponding to the film information. The primer forming unit receives primer process conditions from the controller and forms a primer layer on the substrate over the film. The primer layer is formed according to the selected process conditions. An imprinting unit of the imprint device is configured to receive the substrate from the primer forming unit and perform imprint lithography on the substrate.

Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.

Abstract: A method for detecting a gas tightness of a furnace tube device includes: providing a test wafer; conveying the test wafer into the furnace tube device; depositing a dielectric layer on the test wafer; measuring a thickness and a Goodness of Fit (GOF) of the dielectric layer formed on the test wafer by a thickness measuring machine; and judging the gas tightness of the furnace tube device according to the GOF.

Abstract: A memory device is provided. The memory device includes first and second pull-up transistors. The first pull-up transistor is disposed over a semiconductor substrate, and including a first gate structure and two first source/drain structures at opposite sides of the first gate structure. The second pull-up transistor is laterally spaced apart from the first pull-up transistor, and including a second gate structure and two second source/drain structures at opposite sides of the second gate structure. The first and second gate structures extend along a first direction and laterally spaced apart from each other along a second direction intersected with the first direction. The first gate structure further extends along a sidewall of one of the second source/drain structures, and the second gate structure further extends along a sidewall of one of the first source/drain structures.

Abstract: A wafer processing method in which a wafer including devices on a front surface side is processed. The method includes a wafer-with-protective-component forming step of forming the wafer with a protective component through sticking the protective component formed of a resin that softens by heat to the front surface side by pressing and heating the protective component, a thickness measurement step of measuring a thickness of the protective component in the wafer with the protective component, and a grinding step of holding the wafer with the protective component by a chuck table and grinding a back surface side of the wafer until a thickness of the wafer becomes an intended finished thickness. In the grinding step, the thickness of the protective component measured in the thickness measurement step is subtracted from a total thickness of the wafer with the protective component to calculate the thickness of the wafer.

Abstract: An apparatus for processing substrates includes a continuum radiation source, a source manifold optically coupled to the continuum radiation source and comprising: a plurality of beam guides, each having a first end that optically couples the beam guide to the continuum radiation source; and a second end. The apparatus also includes a detector manifold to detect radiation originating from the source manifold and transmitted through a processing area, and one or more transmission pyrometers configured to analyze the source radiation and the transmitted radiation to determine an inferred temperature proximate the processing area.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes loading a first wafer and a second wafer onto a bonding platform such that the second wafer overlies the first wafer. An alignment process is performed to align the second wafer over the first wafer by virtue of a plurality of wafer pins, where a plurality of first parameters are associated with the wafer pins during the alignment process. The second wafer is bonded to the first wafer. An overlay (OVL) measurement process is performed on the first wafer and the second wafer by virtue of the plurality of wafer pins, where a plurality of second parameters are associated with the wafer pins during the alignment process.

Abstract: Methods for forming molybdenum layers on a surface of a substrate and structures and devices formed using the methods are disclosed. Exemplary methods include forming an underlayer prior to forming the molybdenum layer. The underlayer can be used to manipulate stress in the molybdenum layer and/or reduce a nucleation temperature and/or deposition temperature of a step of forming the molybdenum layer.

Abstract: There is provided a processing apparatus that polishes the back surface side of a wafer on which devices are formed on the front surface side. The processing apparatus includes a chuck table that holds the wafer and rotates and a polishing unit that forms scratches on the back surface side of the wafer while polishing the back surface side of the wafer. The processing apparatus includes also a scratch determining unit that determines whether or not the scratches exist on the back surface side of the wafer polished by the polishing unit and an informing unit that informs that a region in which the scratches do not exist is included in the wafer when a region for which it has been determined that the scratches do not exist by the scratch determining unit is included in the wafer.

Abstract: A method for manufacturing a light emitting device including forming a plurality of first light emitting cells and a plurality of second light emitting cells on one surface of a first substrate, providing a second substrate to face the first and second light emitting cells, selectively bonding the first light emitting cells onto the second substrate, and cutting the second substrate to a mounting unit including at least two first light emitting cells.

Abstract: A system includes a robot arm with multiple joints and one or more end effector to carry a substrate. A processing device determines, within joint space of the robot arm, start/end points of the one or more end effector for a complete movement. The processing device builds, in joint space for the multiple joints and the one or more end effector, a graph of reachable positions and sub-paths between the reachable positions that satisfy Cartesian limits. The reachable positions are identified at a granularity that divides the complete movement into multiple sub-movements. The processing device executes a graph optimization algorithm on the graph to determine multiple paths, each a group of the sub-paths, that have one of shortest distances or lowest costs between the start/end points, and selects a path thereof that minimizes move time of the one or more end effector between the start/end points.

Abstract: A semiconductor device includes a main circuit region; and a scribe region surrounding the main circuit region; wherein the main circuit region and the scribe region comprises first and second insulating films and a low-k film formed therebetween; and wherein the low-k film of the scribe region includes a plurality of cavities lining along a border between the main circuit region and the scribe region.

Abstract: A vane guide assembly for a gas turbine engine, the vane guide assembly including: an airfoil having an end bonded to an opening of a platform by an adhesive; and a pull tab partially located in the adhesive and having a portion extending from a bondline formed by the adhesive.

Abstract: The invention relates to a method for determining the thickness and refractive index of a layer (6) on a substrate (26). The layer (6) having a layer boundary surface (30) facing the substrate (26) and a layer top side (28) facing away from the substrate (26).

Abstract: A pulsed-laser LADA system is provided, which utilizes temporal resolution to enhance spatial resolution. The system is capable of resolving CMOS pairs within the illumination spot using synchronization of laser pulses with the DUT clock. The system can be implemented using laser wavelength having photon energy above the silicon bandgap so as to perform single-photon LADA or wavelength having photon energy below the silicon bandgap so as to generate two-photon LADA. The timing of the laser pulses can be adjusted using two feedback loops tied to the clock signal of an ATE, or by adjusting the ATE's clock signal with reference to a fixed-pulse laser source.

Abstract: A mercury emissions monitor includes a mercury sensor tape configured to be fed in a reel-to-reel manner between first and second tape reels, wherein the mercury sensor tape includes a thin metallic film configured to form an amalgam with detected mercury. A mercury collection unit is configured to receive into a chamber a sample of a gas containing mercury, wherein the mercury collection unit is further configured to permit passage of portions of the mercury sensor tape through the chamber containing the gas sample so that the amalgam is formed with the thin metallic film. A mercury analysis unit includes a total reflection x-ray fluorescence (“TXRF”) system configured to perform a TXRF analysis of the amalgam, wherein the mercury analysis unit is configured to permit passage of the mercury sensor tape within a proximity of an XRF detector of the TXRF system.

Abstract: An electrical-test apparatus is provided, which includes a MEMS array. In an example, the MEMS array comprises a plurality of tester interconnect structures cantilevered from first terminals on a first side of a substrate. The tester interconnect structures may have a first diameter. In an example, the MEMS array comprises a plurality of through-substrate vias that extend through the substrate, the vias having a second diameter larger than the first diameter. In an example, individual ones of the vias electrically couple individual ones of the tester interconnect structures to corresponding ones of second terminals on a second side of the substrate.

Abstract: Full wafer in-situ metrology chambers and methods of use are described. The metrology chambers include a substrate support and a sensor bar that are rotatable relative to each other. The sensor bar includes a plurality of sensors at different radii from a central axis.

Abstract: A system includes a factory interface, a deposition tool, and at least one measuring device. The factory interface is configured to carry a wafer. The deposition tool is coupled to the factory interface and configured to process the wafer transferred from the factory interface. The at least one measuring device is equipped in the factory interface, the deposition tool, or the combination thereof. The at least one measuring device is configured to perform real-time measurements of a thickness of a material on the wafer that is carried in the factory interface or the deposition tool.

Abstract: According to one embodiment, a semiconductor defect inspection apparatus includes: an object-under-examination stage on which an inspection target object is placed; an X-ray irradiation unit that irradiates the object-under-examination stage with X-rays; an imaging unit that detects transmitted X-rays which passed through the inspection target object; a fluorescent X-ray detection unit that detects fluorescent X-rays which are emitted from the inspection target object by irradiation with the X-rays; and a defect detection unit that detects a first defect by an analysis of a transmission X-ray image which is obtained by performing photoelectric conversion of the transmitted X-rays and detects a second defect by a spectrum analysis of the fluorescent X-rays.

Abstract: An X-ray inspection device of the present invention includes a sample placement unit 11 for placing a sample as an inspection target therein, a sample placement unit positioning mechanism 30 for moving the sample placement unit 11, a goniometer 20 including first and second rotation members 22, 23 that rotate independently of each other, an X-ray irradiation unit 40 installed on the first rotation member 22, and a two-dimensional X-ray detector 50 installed on the second rotation member 23. The sample placement unit positioning mechanism 30 includes a ? rotation mechanism 35 for rotating the sample placement unit 11 and a ?-axis about a ?-axis that is orthogonal to a ?s-axis and a ?d-axis at a measurement point P and extends horizontally.

Abstract: An assembly includes at least one first element comprising at least one first electrical bonding pad; at least one second element comprising at least one second electrical bonding pad; electrical and mechanical interconnect means, wherein the electrical and mechanical interconnect means comprise at least: at least one first intermediate metal interconnect element, on the surface of at least the first electrical bonding pad; at least one sintered joint of metal microparticles or nanoparticles stacked with the first intermediate metal interconnect element; the melting point of the first intermediate metal interconnect element being greater than the sintering temperature of the metal microparticles or nanoparticles. A method for fabricating an assembly is also provided.

Abstract: A method includes performing Chemical Mechanical Polish (CMP) on a wafer, placing the wafer on a chuck, performing a post-CMP cleaning on the wafer, and determining cleanness of the wafer when the wafer is located on the chuck.

Abstract: A scanning probe microscope with a first actuator (3) configured to move a feature in the form of a tip (2) so that the feature follows a scanning motion. A vision system (10) is configured to collect light from a field of view to generate image data. The field of view includes the feature and the light from the field of view travels from the feature to the vision system via the steering element (13). A tracking control system (15)bis configured to generate one or more tracking drive signals in accordance with stored reference data. A second actuator (14) is configured to receive the one or more tracking drive signals and move the steering element on the basis of the one or more tracking drive signals so that the field of view follows a tracking motion which is synchronous with the scanning motion and the feature remains within the field of view.

Abstract: Provided are a processing method, a processing apparatus and a processing program which can perform pole figure measurement continuously without overlapping of an angle a in a pole figure with the small number of times of ? scan, thereby enabling the efficient measurement. The processing method for determining conditions of pole figure measurement by X-ray diffraction, includes the steps of. receiving input of a diffraction angle 2?; and determining an angle ? formed by an incident X-ray and an x-axis, and a tilt angle ? of a sample in each ? scan for a rotation angle ? within a sample plane so as to make a range of an angle a continuous from ?=90° to ?=0° without overlapping, the angle ? being formed by the sample plane and a scattering vector, the range of the angle ? are detectable at a time on a two-dimensional detection plane in the pole figure measurement at the diffraction angle 2?, in which determining the angle ? and the tilt angle ? is repeated.

Abstract: Provided is a method of measuring the Fe concentration in a p-type silicon wafer by the SPV method, by which the detection limit for the Fe concentration can be lowered, and the measurement can be performed in a short time. The measurement by the SPV method is performed in a measurement mode in which irradiation with a plurality of lights having mutually different wavelengths is performed during the same period under conditions where (i) Time Between Readings is 35 ms or more and 120 ms or less and Time Constant is 20 ms or more, or Time Between Readings is 10 ms or more and less than 35 ms and Time Constant is 100 ms or more, and (ii) Number of Readings is 12 times or less.

Abstract: A method and a device for measuring a plurality of semiconductor chips in a wafer array are disclosed. In an embodiment a method for measuring the semiconductor chips in a wafer array, wherein the wafer array is arranged on an electrically conductive carrier so that in each case back contacts of the semiconductor chips are contacted by the carrier, wherein a contact structure is arranged on a side of the wafer array facing away from the carrier, and wherein the contact structure includes a contact element and/or a plurality of radiation-emitting measurement semiconductor chips, includes applying a voltage between the contact structure and the carrier and measuring the semiconductor chips depending on a luminous image which is generated by emitted radiation which is caused simultaneously by fluorescence when the semiconductor chips are illuminated or by a radiation-emitting operation of the measurement semiconductor chips when the voltage is applied.

Abstract: A multilayer ceramic electronic component includes: a ceramic body including a dielectric layer and first and second internal electrodes alternately exposed to first and second outer surfaces with the dielectric layer interposed therebetween; and first and second external electrodes disposed on the first and second outer surfaces of the ceramic body so as to be connected to the first and second internal electrodes, respectively. The first internal electrode has a plurality of first ends connected to the first external electrode and a first recessed region positioned between the plurality of first ends, the first recessed region at least partially filled with a dielectric material. The second internal electrode has a plurality of second ends connected to the second external electrode and a second recessed region positioned between the plurality of second ends, the second recessed region at least partially filled with the dielectric material.

Abstract: A method for displaying measurement results from X-ray diffraction measurement, in which a sample is irradiated with X-rays and the X-rays diffracted by the sample are detected by an X-ray detector, comprises: (1) forming a one-dimensional diffraction profile by displaying, on the basis of output data from an X-ray detector, a profile in which one orthogonal coordinate axis shows 2? angle values and another orthogonal coordinate axis shows X-ray intensity values; (2) forming a two-dimensional diffraction pattern by linearly displaying X-ray intensity data, for each 2? angle value and on the basis of output data from the X-ray detector; the X-ray intensity data being present in the circumferential direction of a plurality of Debye rings formed at each 2? angle by diffracted X-rays; and (3) displaying the two-dimensional diffraction pattern and the one-dimensional diffraction profile so as to be aligned such that the 2? angle values of both coincide with each other.

Abstract: Testing structures, and their fabrication methods and testing methods are provided. An exemplary testing structure includes a base substrate containing a well region; a first doped epitaxial region in the well region and having a doping type same as a doping type of the well region; a dielectric layer on the base substrate and covering the well region and the first doped epitaxial region; a first contact plug passing through the dielectric layer and electrically connected with the first well region; and a second contact plug and a third contact plug. The second contact plug and the third contact plug pass through the dielectric layer and electrically connected with the first doped epitaxial region. The second contact plug is independent from the third contact plug and between the first contact plug and the third contact plug.

Abstract: Disclosed is apparatus for inspecting a sample. The apparatus includes illumination optics for simultaneously directing a plurality of incident beams at a plurality of azimuth angles towards a sample and collection optics for directing a plurality of field portions of output light from two or more of the plurality of angles towards two or more corresponding sensors. The two or more sensors are arranged for receiving the field portions corresponding to two or more angles and generating two or more corresponding images. The apparatus further comprises a processor for analyzing the two or more images to detect defects on the sample.

Abstract: Techniques and mechanisms for forming a bond between two wafers. In an embodiment, a first wafer and a second wafer are positioned with respective wafer holders, and are deformed to form a first deformation of the first wafer and a second deformation of the second wafer. The first deformation and the second deformation are symmetrical with respect to a centerline which is between the first wafer and the second wafer. A portion of the first deformation is made to contact, and form a bond with, another portion of the second deformation. The bond is propagated along respective surfaces of the wafers to form a coupling therebetween. In another embodiment, one of the wafer holders comprises one of an array of elements to locally heat or cool a wafer, or an array of displacement stages to locally deform said wafer.

Abstract: The application generally relates to digital Engine Integrity Protection (EIP) systems for filters for internal combustion engines and methods of using the digital EIP systems. A pre-programmed digital chip is integrated in filtration hardware such that the Engine Control Unit (ECU) or another controller installed on the engine or vehicle can read encrypted digital signal from the chip when electrically connected with the filter hardware. Based on the read information from the chip, the ECU or controller can determine whether the filter associated with the chip is a genuine filter or a non-genuine filter.

Abstract: Provided is a large-sized silicon nitride sintered substrate and a method for producing the same. The silicon nitride sintered substrate has a main surface 101a of a shape larger than a square having a side of a length of 120 mm. A ratio dc/de of the density dc of the central area and the density de of the end area of the main surface 101a is 0.98 or higher. The void fraction vc of the central area of the main surface 101a is 1.80% or lower, and the void fraction ve of the end area is 1.00% or lower. It is preferred that the density dc of the central area is 3.120 g/cm3 or higher, the density de of the end area is 3.160 g/cm3 or higher, and a ratio ve/vc of the void fraction vc of the central area and the void fraction ve of the end area is 0.50 or higher.

Abstract: A system may include a controller configured to cause a capacitance probe to subject a material to a first electric signal having a first frequency and determine a first capacitance of the material at the first frequency. The controller is configured to cause the capacitance probe to subject the material to a second electric signal at a second frequency and determine a second capacitance of the material at the second frequency. The material includes at least a first constituent phase and a second constituent phase. The first constituent phase and the second constituent phase have substantially similar dielectric constants at the first frequency and substantially different dielectric constants at the second frequency. The controller is further configured to determine a porosity of the material based on the first capacitance and determine a relative phase composition of the first constituent phase and the second constituent phase based on the second capacitance.

Abstract: Methods and systems for descriptor guided fast marching method based image analysis and associated systems are disclosed. A representative image processing method includes processing an image of a microelectronic device using a fast marching algorithm to obtain arrival time information for the image. The arrival time information is analyzed using a targeted feature descriptor to identify targeted features. The detection of defects is facilitated by segmenting the image. The segmented image can be analyzed to identify targeted features which are then labeled for inspection.

Abstract: Implementations described herein generally relate to methods for leveling a component above a substrate. In one implementation, a test substrate is placed on a substrate support inside of a processing chamber. A component, such as a mask, is located above the substrate. The component is lowered to a position so that the component and the substrate are in contact. The component is then lifted and the particle distribution on the test substrate is reviewed. Based on the particle distribution, the component may be adjusted. A new test substrate is placed on the substrate support inside of the processing chamber, and the component is lowered to a position so that the component and the new test substrate are in contact. The particle distribution on the new test substrate is reviewed. The process may be repeated until a uniform particle distribution is shown on a test substrate.

Abstract: A method includes obtaining data associated with an electronic component. The method also includes conducting a multi-tier inspection process to verify a conformance of the electronic component. Each of the tiers includes a different type of identification test, and at least one of the tiers is configured to provide fuzzy outputs. The method further includes analyzing the data associated with the electronic component using one or more first tests associated with a first of the tiers to determine whether the electronic component conforms to a pre-specified requirement. In addition, the method includes generating an output based on the analysis and determining whether additional testing is required using one or more next-level tests associated with another of the tiers.

Abstract: Apparatus and methods for performing optically based film thickness measurements of highly absorbing films (e.g., high-K dielectric films) with improved measurement sensitivity are described herein. A highly absorbing film layer is fabricated on top of a highly reflective film stack. The highly reflective film stack includes one or more nominally identical sets of multiple layers of different, optically contrasting materials. The highly reflective film stack gives rise to optical resonance in particular wavelength ranges. The high reflectance at the interface of the highly absorbing film layer and the highly reflective film stack increases measured light intensity and measurement sensitivity. The thickness and optical dispersion of the different material layers of the highly reflective film stack are selected to induce optical resonance in a desired wavelength range. The desired wavelength range is selected to minimize absorption by the highly absorbing film under measurement.