For Structural Parameters, E.g., Thickness, Line Width, Refractive Index, Temperature, Warp, Bond Strength, Defects, Optical Inspection, Electrical Measurement Of Structural Dimensions, Metallurgic Measurement Of Diffusions (epo) Patents (Class 257/E21.53)
  • Patent number: 10283420
    Abstract: The invention is directed to a method for the production of an optoelectronic module including a support (5) and an additional layer, said support being formed by an assembly (25) which has no optoelectronic properties and which comprises, successively, a metal substrate (27), a dielectric coating (29) disposed on the metal substrate, and an electrically conductive layer (31) disposed on the dielectric coating. The production method comprises: a step of providing the support and performing a method in which the support is checked, or providing the support after it has already been checked; and a step of depositing at least one additional layer on the electrically conductive layer.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: May 7, 2019
    Assignee: ArcelorMittal
    Inventor: Philippe Guaino
  • Patent number: 10250258
    Abstract: Embodiments of devices and method for detecting semiconductor substrate thickness are disclosed. In an embodiment, an IC device includes a semiconductor substrate, a charge emitter embedded in the semiconductor substrate and configured to produce an electrical charge in the semiconductor substrate and a charge sensor embedded in the semiconductor substrate and configured to generate a response signal in response to the electrical charge produced in the semiconductor substrate. The magnitude of the response signal depends on the thickness of the semiconductor substrate.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: April 2, 2019
    Assignee: NXP B.V.
    Inventors: Andreas Bernardus Maria Jansman, Franciscus Petrus Widdershoven, Viet Thanh Dinh
  • Patent number: 10215688
    Abstract: The system includes a modulatable illumination source configured to illuminate a surface of a sample disposed on a sample stage, a detector configured to detect illumination emanating from a surface of the sample, illumination optics configured to direct illumination from the modulatable illumination source to the surface of the sample, collection optics configured to direct illumination from the surface of the sample to the detector, and a modulation control system communicatively coupled to the modulatable illumination source, wherein the modulation control system is configured to modulate a drive current of the modulatable illumination source at a selected modulation frequency suitable for generating illumination having a selected coherence feature length. In addition, the present invention includes the time-sequential interleaving of outputs of multiple light sources to generate periodic pulse trains for use in multi-wavelength time-sequential optical metrology.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: February 26, 2019
    Assignee: KLA-Tencor Corporation
    Inventors: Andrei V. Shchegrov, Lawrence D. Rotter, David Y. Wang, Andrei Veldman, Kevin Peterlinz, Gregory Brady, Derrick A. Shaughnessy
  • Patent number: 10156512
    Abstract: Embodiments are provided herein for testing multichip module (MCM) thermal reliability. An embodiment method includes selecting a chip with higher thermal risk from a plurality of chips in the MCM, and measuring a plurality of predetermined temperature parameters associated with the selected chip. A thermal resistance is then calculated using the predetermined temperature parameters. The thermal resistance is used to determine a thermal performance of the MCM. The predetermined temperature parameters include a junction temperature of the selected chip and at least one of a case temperature above the selected chip, a board temperature below the selected chip, and an ambient air temperature.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: December 18, 2018
    Assignee: FUTUREWEI TECHNOLOGIES, INC.
    Inventors: Qian Han, Junsheng Guo, Yongwang Xiao
  • Patent number: 10152595
    Abstract: A method of container and image scanning includes storing at a central scan store of a multi-tenant system, an image scan result for a container image, the container image for executing functionality of applications and comprising layers, wherein the image scan result generated by a scan process comprising scanning a top layer of the container image, the remaining layers of the container image are immutable, verifying a clean status of the remaining layers of the container image with the central scan store, and transmitting the image scan result for the container image, the image scan result being clean in response to a clean result returned for the scanning and successful verification of the clean status of the remaining layers. The method further includes responsive to receiving a container image scan result request for the container image, transmitting the image scan result for the container image.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: December 11, 2018
    Assignee: Red Hat, Inc.
    Inventors: Thomas Wiest, Joel Smith
  • Patent number: 10127651
    Abstract: Criticality of a detected defect can be determined based on context codes. The context codes can be generated for a region, each of which may be part of a die. Noise levels can be used to group context codes. The context codes can be used to automatically classify a range of design contexts present on a die without needing certain information a priori.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: November 13, 2018
    Assignee: KLA-Tencor Corporation
    Inventors: Ashok Kulkarni, Saibal Banerjee, Santosh Bhattacharyya, Bjorn Brauer
  • Patent number: 10126238
    Abstract: Angle-resolved reflectometers and reflectometry methods are provided, which comprise a coherent light source, an optical system arranged to scan a test pattern using a spot of coherent light from the light source to yield realizations of the light distribution in the collected pupil, wherein the spot covers a part of the test pattern and the scanning is carried out optically or mechanically according to a scanning pattern, and a processing unit arranged to generate a composite image of the collected pupil distribution by combining the pupil images. Metrology systems and methods are provided, which reduce diffraction errors by estimating, quantitatively, a functional dependency of measurement parameters on aperture sizes and deriving, from identified diffraction components of the functional dependency which relate to the aperture sizes, correction terms for the measurement parameters with respect to the measurement conditions.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: November 13, 2018
    Assignee: KLA-Tencor Corporation
    Inventors: Amnon Manassen, Andrew Hill, Daniel Kandel, Ilan Sela, Ohad Bachar, Barak Bringoltz
  • Patent number: 10114065
    Abstract: An electron beam absorbed current measurement method includes connecting a conductive probe to a conductive structure of a sample, irradiating a pulsed electron beam along the conductive structure to generate an alternating current in the conductive probe, and determining a presence of a high resistance defect in the conductive structure based on at least one of a delay of a rising edge of the alternating current waveform and a decrease in amplitude of the alternating current waveform.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: October 30, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Norio Toshima
  • Patent number: 10113944
    Abstract: The present application discloses a circuit board testing apparatus to the printed circuit board, including: a base frame; a carrying platform located on the upper surface of the base frame, the carrying platform including a carrying curved surface, a first distance is formed between the central portion of the carrying curved surface and the upper surface of the base frame, a second distance is formed between the two terminals of the carrying curved surface and the upper surface of the base frame, the second distance is greater than the first distance; and a plurality of supporting components disposed in intervals, each of the supporting components including a supporting rod and a driving member, the driving member is fixed on the base frame, the supporting rods pass through the carrying curved surface, the driving member drives the supporting rod to move in the direction perpendicular to the upper surface, and makes the printed circuit board bending and deformation.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: October 30, 2018
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Xiaoyu Huang
  • Patent number: 10103071
    Abstract: A reticle may be fabricated and inspected. The reticle, which may include thin patterns, may be selectively incorporated into a fabricated semiconductor device based on measurement information generated based on the inspecting. The inspecting may include forming thin patterns on a substrate, forming a first discharge layer on the thin patterns, and directing a first charged particle beam to the substrate, such that the first charged particle beam passes through the first discharge layer. Measurement information may be generated based on the first charged particle beam. The first discharge layer may connect the thin patterns to each other and may be separated from the substrate between the thin patterns.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: October 16, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eokbong Kim, Jin sung Choi, Mun Ja Kim, Kijung Son
  • Patent number: 10062160
    Abstract: Tracking patterns during a semiconductor fabrication process includes: obtaining an image of a portion of a fabricated device; extracting contours of the portion of the fabricated device from the obtained image; aligning the extracted contour to a matching section of a reference design; decomposing the matching section of the reference design into one or more patterns; and updating a pattern tracking database with information pertaining to at least one pattern in the one or more patterns generated as a result of the decomposition.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: August 28, 2018
    Assignee: Anchor Semiconductor Inc.
    Inventors: Khurram Zafar, Chenmin Hu, Ye Chen, Yue Ma, Chingyun Hsiang, Justin Chen, Raymond Xu, Abhishek Vikram, Ping Zhang
  • Patent number: 10043259
    Abstract: A method for facilitating detection of at least one anomaly in a representation of a product having a pattern is provided. The method involves causing at least one processor to receive image data representing the product during processing, identify from the image data generally similar images representing respective instances of a repeated aspect of the pattern, each of the images including image element values, generate a set of corresponding image element values including an image element value from each image, identify at least one image element value from the set of corresponding image element values to be excluded from a subset of the set of corresponding image element values, generate at least one criterion based on the subset, and cause the at least one criterion to be used to facilitate identification of the at least one anomaly. Other methods, apparatuses, systems, and computer readable media are also provided.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: August 7, 2018
    Assignee: PT PAPERTECH INC.
    Inventor: Juha Reunanen
  • Patent number: 10006872
    Abstract: Provided is an optical inspection system including a supporting unit, allowing a target object to be loaded thereon, a light source unit configured to emit a laser beam toward the target object, a light condensing unit collecting scattered light that is scattered at the target object when the laser beam is irradiated onto the target object, and a control unit controlling the light source unit and the light condensing unit and analyzing the scattered light to examine whether there are pollutants on the target object. The supporting unit may include a first supporting unit, on which the target object is disposed, and which is formed of a first material, and a second supporting unit, which is disposed under the first supporting unit and is formed of a second material different from the first material.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: June 26, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wonguk Seo, Kyoungchon Kim, Kuihyun Yoon, Kyunlae Kim, Jaeyoung Park, Kyoungho Yang, Young Heo
  • Patent number: 9991174
    Abstract: The measurement method may include obtaining first measurement data from a recess region formed in a semiconductor substrate, obtaining second measurement data from a conductive pattern filling a portion of the recess region, calculating a first volume of the recess region from the first measurement data, calculating a second volume of the conductive pattern from the second measurement data, and calculating a measurement target parameter using a difference between the first and second volumes.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: June 5, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Choonshik Leem, Jihye Lee, Deokyong Kim, Soobok Chin
  • Patent number: 9984982
    Abstract: The present invention relates to a device and method for generating an identification key using a process variation in a via process, and specifically the device for generating an identification key may include a first node provided in a semiconductor chip, a second node which is formed in a different layer from the first node, a via which is electrically shorted to the first node, and which is formed between the first node and the second node, the overlap distance between the second node and the via, in a pattern layout of the semiconductor chip, being adjusted to a value that is less than a threshold according to a design rule that ensures that the first node and the second node are shorted by the via, and a reader which provides an identification key by identifying whether the first node and the second node are shorted due to the via.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: May 29, 2018
    Assignee: ICTK CO., LTD.
    Inventors: Byong Deok Choi, Dong Kyue Kim
  • Patent number: 9922269
    Abstract: Defect classification includes acquiring one or more images of a specimen including multiple defects, grouping the defects into groups of defect types based on the attributes of the defects, receiving a signal from a user interface device indicative of a first manual classification of a selected number of defects from the groups, generating a classifier based on the first manual classification and the attributes of the defects, classifying, with the classifier, one or more defects not manually classified by the manual classification, identifying the defects classified by the classifier having the lowest confidence level, receiving a signal from the user interface device indicative of an additional manual classification of the defects having the lowest confidence level, determining whether the additional manual classification identifies one or more additional defect types not identified in the first manual classification, and iterating the procedure until no new defect types are found.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: March 20, 2018
    Assignee: KLA-Tencor Corporation
    Inventors: Sankar Venkataraman, Li He, John R. Jordan, III, Oksen Baris, Harsh Sinha
  • Patent number: 9922765
    Abstract: In a method of manufacturing a laminated electronic component, in a step of obtaining a laminate, a position of a second green sheet with respect to a first green sheet is determined such that an overall width of a first portion printed on the first green sheet and a second portion printed on the second green sheet becomes substantially equal to a width of the first portion or a width of the second portion.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: March 20, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Takashi Sawada
  • Patent number: 9875923
    Abstract: A control system that includes deflection sensors which can control clamping forces applied by electrostatic chucks, and related methods are disclosed. By using a sensor to determine a deflection of a workpiece supported by an electrostatic chuck, a control system may use the deflection measured to control a clamping force applied to the workpiece by the electrostatic chuck. The control system applies a clamping voltage to the electrostatic chuck so that the clamping force reaches and maintains a target clamping force. In this manner, the clamping force may secure the workpiece to the electrostatic chuck to enable manufacturing operations to be performed while preventing workpiece damage resulting from unnecessary higher values of the clamping force.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: January 23, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Wendell Boyd, Jr., Vijay D. Parkhe, Matthew James Busche, Konstantin Makhratchev, Masanori Ono, Senh Thach
  • Patent number: 9865514
    Abstract: A through-silicon via (TSV) capacitive test structure and method of determining TSV depth based on capacitance is disclosed. The TSV capacitive test structure is formed from a plurality of TSV bars that are evenly spaced. A first group of bars are electrically connected to form a first capacitor node, and a second group of bars is electrically connected to form a second capacitor node. The capacitance is measured, and a TSV depth is computed, prior to backside thinning. The computed TSV depth may then be fed to downstream grinding and/or polishing tools to control the backside thinning process such that the semiconductor wafer is thinned such that the backside is flush with the TSV.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: January 9, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hanyi Ding, J. Edwin Hostetter, Ping-Chuan Wang, Kimball M. Watson
  • Patent number: 9864173
    Abstract: A spot scanning imaging system with run-time alignment includes a beam scanning device configured to linearly scan a focused beam of illumination across a sample, one or more detectors positioned to receive light from the sample, and a controller communicatively coupled to the beam scanning apparatus, the sample stage, and the one or more detectors. The controller is configured to store a first image, transmit a set of drive signals to at least one of the beam scanning device, the sample stage, or the one or more detectors, compare at least a portion of the second sampling grid to at least a portion of the first sampling grid to determine one or more offset errors, and adjust at least one drive signal in the set of drive signals based on the one or more offset errors such that the second sample grid overlaps the first sample grid.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: January 9, 2018
    Assignee: KLA-Tencor Corporation
    Inventors: Jamie M. Sullivan, Wenjian Cai, Kai Cao
  • Patent number: 9824443
    Abstract: [Object] To improve work efficiency with respect to work using a transparent object, such as a transparent operation tool, for example. [Solution] An image region where an object exists as a target region is detected on the basis of a second captured image, when a first captured image is a captured image obtained by selectively receiving a light of a first wavelength band, and the second captured image is a captured image obtained by selectively receiving a light of a second wavelength band, the captured images being obtained by capturing the object that is transparent for the light of the first wavelength band and is opaque for the light of the second wavelength band. Subsequently, an outline of the object is superimposed on the first captured image on the basis of information of the target region detected by the target detecting unit.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: November 21, 2017
    Assignee: SONY CORPORATION
    Inventor: Tsuneo Hayashi
  • Patent number: 9810905
    Abstract: A support information display method is provided with an acquiring process for acquiring a first image by photographing, via a camera provided in a head mount display, a predetermined part of a substrate processing apparatus as a maintenance object, an estimating process for estimating the support information related to the predetermined part in the first image from information stored in a database, an image creating process for creating a second image by converting the support information estimated in the estimating process into an image, and a displaying process for displaying the second image on the head mount display in order for the operator to visually recognize the support information.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: November 7, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Toshiaki Kodama, Toru Yamauchi, Sensho Kobayashi, Hiroshi Nakamura, Gaku Ikeda, Kazuya Uoyama
  • Patent number: 9784691
    Abstract: A method and apparatus to measure specular reflection intensity, specular reflection angle, near specular scattered radiation, and large angle scattered radiation and determine the location and type of defect present in a first and a second transparent solid that have abutting surfaces. The types of defects include a top surface particle, an interface particle, a bottom surface particle, an interface bubble, a top surface pit, and a stain. The four measurements are conducted at multiple locations along the surface of the transparent solid and the measured information is stored in a memory device. The difference between an event peak and a local average of measurements for each type of measurement is used to detect changes in the measurements. Information stored in the memory device is processed to generate a work piece defect mapping indicating the type of defect and the defect location of each defect found.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: October 10, 2017
    Assignee: ZETA INSTRUMENTS, INC.
    Inventors: Steven W. Meeks, Ronny Soetarman
  • Patent number: 9772282
    Abstract: System for scatter-based differentiation of cells. The system includes a planar substrate having cells disposed thereon for imaging and a microscope employing relatively low magnification detection optics providing a wide field of view focused on the cells on the substrate and defining a microscope optical axis. An illuminator delivers light to the ceils on the substrate focused to a spot larger than the field of view of the microscope, the illuminator having an illumination optical axis highly oblique to the microscope optical axis wherein scattered light is collected by the microscope. A defection system receives the scattered light from the microscope to provide a measure of signal intensity and a measure of size for each cell for discrimination of cell type.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: September 26, 2017
    Assignee: Massachusetts Institute of Technology
    Inventors: Jason Michael Tucker-Schwartz, Shivang Rajendra Dave, German Gonzalez Serrano
  • Patent number: 9759547
    Abstract: The disclosed systems and methods relate to inspecting uncured fiber-reinforced composite components by non-contact 3D measurements of the component using 3D digital image correlation with patterned illumination. Systems comprise a light projector configured to project a light pattern onto a form, a digital camera configured to image the light pattern, and may comprise and/or be associated with an AFP machine that is configured to lay uncured composite on the form. Methods comprise projecting a light pattern onto a form, acquiring a baseline 3D profile of the form by imaging the light pattern on the form, laying an uncured fiber piece onto the form, projecting the light pattern onto the uncured fiber piece, acquiring a test 3D profile of the fiber piece by imaging the light pattern on the uncured fiber piece, and computing a thickness difference between the test 3D profile and the baseline 3D profile.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: September 12, 2017
    Assignee: The Boeing Company
    Inventors: James A. Grossnickle, Kevin Earl McCrary, Karl M. Nelson, Craig Allen Cramer
  • Patent number: 9746436
    Abstract: A detecting device includes a substrate having a cavity portion in the surface thereof; a thin-film layer formed over the cavity portion; an on-thin-film layer pattern formed on the thin-film layer; an on-substrate pattern formed on the substrate; and a first terminal, a second terminal, a third terminal, and a fourth terminal. A resistance between the first terminal and the second terminal includes a resistance of the on-thin-film layer pattern, a resistance between the third terminal and the fourth terminal includes the resistance of the on-thin-film layer pattern and a resistance of the on-substrate pattern, and the resistance between the first terminal and the second terminal is less than the resistance between the third terminal and the fourth terminal.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: August 29, 2017
    Assignee: RICOH COMPANY, LTD.
    Inventor: Shinichi Kubota
  • Patent number: 9715181
    Abstract: A lithography tool is calibrated using a calibration substrate having a set of first marks distributed across its surface in a known pattern. The tool is operated to apply a pattern comprising a plurality of second marks at various positions on the substrate, each second mark overlying one of the first marks and being subject to an overlay error dependent on an apparatus-specific deviation. The second marks are applied by multiple exposures while the substrate remains loaded in the tool. An operating parameter of the apparatus is varied between the exposures. An overlay error is measured and used to calculate parameter-specific, apparatus-specific calibration data based on knowledge of the parameter variation used for each exposure.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: July 25, 2017
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Emil Peter Schmitt-Weaver, Paul Frank Luehrmann, Wolfgang Henke, Marc Jurian Kea
  • Patent number: 9703906
    Abstract: A circuit simulation device includes a measurement unit, a calculation unit, and a processing unit. The measurement unit measures first spaces between adjacent contacts of a plurality of first contacts provided on a source diffusion layer in a line in a direction along which a gate electrode of a transistor extends and also a space between adjacent contacts of a plurality of second contacts provided on a drain diffusion layer in a line in the direction, based on layout design data, and second spaces between the first contacts and the gate electrode and spaces between the second contacts and the gate electrode. The calculation unit calculates a fringe capacitance between the gate electrode, the source diffusion layer, and the drain diffusion layer of the transistor, based on the first and second spaces. The processing unit executes layout simulation based on the fringe capacitance of the transistor.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: July 11, 2017
    Assignee: Renesas Electronics Corporation
    Inventor: Hideo Sakamoto
  • Patent number: 9689751
    Abstract: An optical fiber temperature distribution measurement device for measuring a temperature distribution along a longitudinal direction of an optical fiber is provided.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: June 27, 2017
    Assignee: Yokogawa Electric Corporation
    Inventors: Hideo Shida, Kazushi Oishi
  • Patent number: 9658949
    Abstract: A test system method for testing software of each of a plurality of system on chips (SoCs) are provided. The test system includes: a plurality of test units configured to test the plurality of SoCs according to a plurality of test cases, respectively; a power supplier configured to supply, to each of the plurality of test units, power of a level corresponding to a corresponding test case, among the plurality of test cases; a temperature controller configured to provide, to each of the plurality of test units, a temperature control signal according to the corresponding test case, and to monitor a measurement temperature, provided from each of the plurality of test units, of each of the plurality of SoCs; and an analyzer configured to analyze at least one of a driving voltage, a driving current, and a driving frequency of each of the plurality of SoCs.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: May 23, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Manyoung Shin, Janghyuk An
  • Patent number: 9646224
    Abstract: The present disclosure relates to an image processing method, an image processing device, and an automated optical inspection machine. The method includes: an inspection area determining step for determining a rectangular inspection area in an inspected image; a definition threshold determining step for calculating an image definition threshold according to the gray values of pixels of a plurality of sample images in the inspection area; a product image definition determining step for calculating a product image definition according to the gray values of pixels of a product image in the inspection area; and a comparison step for comparing the product image definition with the image definition threshold; and a product image selecting step for selecting the current product image as an image to be inspected.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: May 9, 2017
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Yueyan Zhang
  • Patent number: 9488593
    Abstract: Provided herein is an apparatus, including a light source configured to illuminate a surface of an article, wherein light incident upon the surface of the article is collimated light; a light detector array including a plurality of light sensors configured to receive scattered light from features about the surface of the article; and a processing means for mapping the features about the surface of the article, wherein the processing means is configured to map the features by analyzing the scattered light received at the light detector array.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: November 8, 2016
    Assignee: Seagate Technology LLC
    Inventors: Joachim W. Ahner, S. Keith McLaurin
  • Patent number: 9470745
    Abstract: A semiconductor device includes a normal pad and a first monitoring unit suitable for monitoring whether a bunker is formed in the normal pad based on an inherent resistance component of the normal pad during a probe test.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: October 18, 2016
    Assignee: SK Hynix Inc.
    Inventor: Jong-Su Kim
  • Patent number: 9435733
    Abstract: A system for measuring a characteristic of a solar cell is disclosed and includes a light source irradiating an optical signal having a spectral range from about 100 nm to about 3000 nm, a wavelength selector configured to selectively narrow the spectral range of the optical signal, a beam splitter, a reference detector in optical communication with the beam splitter and configured to measure a characteristic of the optical signal, a specimen irradiated with the optical signal, a reflectance detector in optical communication with the specimen via the beam splitter and configured to measure an optical characteristic of the optical signal reflected by the specimen, a multiplexer in communication with at least one of the reference detector, specimen, and reflectance detector, and a processor in communication with at least one of the reference detector, specimen, and reflectance detector via the multiplexer and configured to calculate at least one characteristic of the specimen.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: September 6, 2016
    Assignee: NEWPORT CORPORATION
    Inventors: Razvan Ciocan, John Donohue, Arkady Feldman, Zhuoyun Li
  • Patent number: 9418049
    Abstract: A method for establishing a parametric model of a semiconductor process is provided. A first intermediate result is generated according to layout data and a non-parametric model of the semiconductor process. A first response is obtained according to the first intermediate result. A specific mathematical function is selected from a plurality of mathematical functions, and the parametric model is obtained according to the specific mathematical function. A second intermediate result is generated according to the layout data and the parametric model. A second response is obtained according to the second intermediate result. It is determined whether the parametric model is an optimal model according to the first and second responses.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: August 16, 2016
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD, NATIONAL TAIWAN UNIVERSITY
    Inventors: Kuen-Yu Tsai, Chun-Hung Liu
  • Patent number: 9417180
    Abstract: In an optical measuring method, a reflected light from a structure on a substrate is detected by a measuring tool to obtain a raw spectrum. The raw spectrum in a wavelength range having spectrum sensitivity to process variation is analyzed to determine a process variation of an actual process performed on the substrate. The raw spectrum is corrected according to a spectrum offset for the measuring tool which is determined based on the process variation.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: August 16, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Min Seo, Jang-Ik Park
  • Patent number: 9329137
    Abstract: A defect inspection device inspecting a sample includes a movable table on which the sample as an inspection object and a pattern chip are mounted, an illumination light irradiation unit which irradiates a surface of the sample or a surface of the pattern chip with linearly-formed illumination light, a detection optical system section where a plurality of detection optical systems are disposed at a plurality of positions above the table and which detect images of scattered light generated from the sample, and a signal processing unit which processes detected signals to detect a defect of the sample surface, and a plurality of repeating patterns for generating the scattered light according to positions of the objective lenses of the plurality of detection optical systems of the detection optical system section when the linearly-formed illumination light is irradiated by the illumination light irradiation unit are periodically formed in the pattern chip.
    Type: Grant
    Filed: January 20, 2014
    Date of Patent: May 3, 2016
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Yukihiro Shibata, Hideki Fukushima, Yuta Urano, Toshifumi Honda
  • Patent number: 9316604
    Abstract: A method and apparatus for non-destructively determining features in a planer specimen includes providing a heat impulse to the specimen, detecting temperatures in the specimen at a plurality of locations, and imaging the specimen from the detected temperatures. A laser can be used to provide a single or a plurality of heat impulses to the specimen. Temperatures in the specimen can be detected utilizing a contact sensor array or a remote infrared detector. These sensors are joined to a data processing device to image the specimen utilizing the detected temperatures.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: April 19, 2016
    Inventor: Anthony A. Ruffa
  • Patent number: 9018021
    Abstract: A layer is deposited onto a semiconductor wafer by CVD in a process chamber having upper and lower covers, wherein the wafer front side temperature is measured; the wafer is heated to deposition temperature; the temperature of the upper process chamber cover is controlled to a target temperature by measuring the temperature of the center of the outer surface of the upper cover as the value of a controlled variable of an upper cover temperature control loop; a gas flow rate of process gas for depositing the layer is set; and a layer is deposited on the heated wafer front side during control of the upper cover temperature to the target temperature. A process chamber suitable therefor has a sensor for measuring the upper cover outer surface center temperature and a controller for controlling this temperature to a predetermined value.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: April 28, 2015
    Assignee: Siltronic AG
    Inventor: Georg Brenninger
  • Patent number: 8987013
    Abstract: A method of inspecting misalignment of a polysilicon gate is disclosed, characterized in forming only NMOS devices in P-wells in a test wafer and utilizing an advanced electron beam inspection tool operating with a positive mode to carry out electrical defect inspection. The method can be applied in precisely figuring out the in-plane misalignment of the polysilicon gates of an in-process semiconductor product and identifying a misalignment tendency therebetween across a wafer by verifying all locations of interest thereon, thus providing a methodology for process window optimization and on-line monitoring and contributing to the manufacturing process and yield improvement.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: March 24, 2015
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Rongwei Fan, Hunglin Chen, Yin Long, Qiliang Ni
  • Patent number: 8986560
    Abstract: A method for producing an optical semiconductor device includes the steps of determining a wafer size to make a section arrangement including a plurality of sections in each of which the optical semiconductor device including a semiconductor mesa is formed; obtaining an in-plane distribution of a thickness of a resin layer on a wafer; obtaining a correlation between a thickness of a resin layer and a trench width; forming a trench width map using the in-plane distribution of the thickness and the correlation; preparing an epitaxial substrate by forming a stacked semiconductor layer; forming, on the epitaxial substrate, a mask based on the trench width map; forming a trench structure including the semiconductor mesa by etching the stacked semiconductor layer using the mask; forming a resin layer on the trench structure; and forming an opening on the semiconductor mesa by etching the resin layer.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: March 24, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takamitsu Kitamura, Hideki Yagi
  • Patent number: 8980762
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a film having different filling properties dependent on space width above the patterning film to cover the first line patterns and the second line patterns to form the film on the first line patterns and on the first inter-line pattern space while making a cavity in the first inter-line pattern space and to form the film on at least a bottom portion of the second inter-line pattern space and a side wall of each of the second line patterns. The method includes performing etch-back of the film to remove the film on the first line patterns and on the first inter-line pattern space while causing the film to remain on at least the side wall of the second line patterns.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazunori Iida, Yuji Kobayashi
  • Patent number: 8956888
    Abstract: A photovoltaic device is made using a method and a system disclosed herein. The method may comprise: providing a web of photovoltaic material; providing a web of interconnect material; cutting the web of photovoltaic material into a plurality of photovoltaic cells; cutting the web of interconnect material into a plurality of interconnects; providing a respective one of the plurality of interconnects between adjacent photovoltaic cells to electrically connect a first string of photovoltaic cells in series; and laminating the first string of photovoltaic cells which are electrically connected in series between a top laminating sheet and a bottom laminating sheet. The system may comprise: a first conveyor, an optical inspection apparatus, a removal apparatus, a sorter, a second conveyor, and an assembly apparatus configured to place an interconnect between adjacent photovoltaic cells to electrically connect a first string of photovoltaic cells in series.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: February 17, 2015
    Assignee: Apollo Precision Fujian Limited
    Inventor: Paul Shufflebotham
  • Patent number: 8945971
    Abstract: The present disclosure relates a method to mitigate wafer warpage in advanced technology manufacturing processes due to crystallization of one or more amorphous layers with asymmetrical front-surface and back-surface layer thicknesses. After deposition of one or more layers of amorphous material on a front-surface and a back-surface of the wafer in a furnace tool, the front-surface layers are patterned which thins a front layer thickness. Downstream thermal processing performed at a temperature which exceeds a crystallization threshold of the amorphous material will result in asymmetric stress between the front and back surfaces due to the asymmetrical layer thicknesses. To mitigate this effect, the amount of warpage as a function of the difference in asymmetrical layer thickness may be determined such that a front-surface deposition tool may be utilized in conjunction with the furnace tool to reduce the difference in front-surface and back-surface layer thicknesses. Other methods are also disclosed.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun Hsiung Tsai, Shiang-Rung Tsai
  • Patent number: 8940555
    Abstract: The formation of overlap areas in sophisticated semiconductor devices is a critical aspect which may not be efficiently evaluated on the basis of conventional measurement and design strategies. For this reason, the present disclosure provides measurement techniques and systems in which overlying device patterns are transformed into the same material layer, thereby forming a combined pattern which is accessible by well-established defect inspection techniques. Upon geometrically modulating some of these combined patterns, a systematic evaluation of overlap process windows may be accomplished.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: January 27, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Lothar Bauch
  • Patent number: 8932884
    Abstract: Structures and methods are disclosed for evaluating the effect of a process environment variation. A structure and related method are disclosed including a plurality of electrical structures arranged in a non-collinear fashion for determining a magnitude and direction of a process environment variation in the vicinity of the plurality of electrical structures. The plurality of structures may include a first polarity FET coupled to a second polarity FET, each of the first polarity FET and the second polarity FET are coupled to a first pad and a second pad such that the structure allows independent measurement of the first polarity FET and the second polarity FET using only the first and second pads. Alternatively, the electrical structures may include resistors, diodes or ring oscillators. Appropriate measurements of each electrical structure allow a gradient field including a magnitude and direction of the effect of a process environment variation to be determined.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak, Noah D. Zamdmer
  • Patent number: 8912079
    Abstract: Provided is a compound semiconductor deposition method of adjusting the luminous wavelength of a compound semiconductor of a ternary or higher system in a nanometer order in depositing the compound semiconductor on a substrate.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: December 16, 2014
    Assignees: The University of Tokyo, V Technology Co., Ltd.
    Inventors: Motoichi Ohtsu, Takashi Yatsui, Tadashi Kawazoe, Shunsuke Yamazaki, Koichi Kajiyama, Michinobu Mizumura, Keiichi Ito
  • Patent number: 8908161
    Abstract: Approaches for substantially removing bulk aluminum nitride (AlN) from one or more layers epitaxially grown on the bulk AlN are discussed. The bulk AlN is exposed to an etchant during an etching process. During the etching process, the thickness of the bulk AlN can be measured and used to control etching.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: December 9, 2014
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Brent S. Krusor, Christopher L. Chua, Thomas Wunderer, Noble M. Johnson, Bowen Cheng
  • Patent number: 8895325
    Abstract: A system and method are disclosed for aligning substrates during successive process steps, such as ion implantation steps, is disclosed. Implanted regions are created on a substrate. After implantation, an image is obtained of the implanted regions, and a fiducial is provided on the substrate in known relation to at least one of the implanted regions. A thermal anneal process is performed on the substrate such that the implanted regions are no longer visible but the fiducial remains visible. The position of the fiducial may be used in downstream process steps to properly align pattern masks over the implanted regions. The fiducial also may be applied to the substrate before any ion implanting of the substrate is performed. The position of the fiducial with respect to an edge or a corner of the substrate may be used for aligning during downstream process steps. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: November 25, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: John W. Graff, Benjamin B. Riordon, Nicholas P. T. Bateman
  • Patent number: 8877642
    Abstract: Fabricating of one or more semiconductor devices with critical gate dimension control is facilitated by: providing a multilayer stack structure over a substrate; etching through the multilayer stack structure, with critical gate dimension control, to define multiple gate lines; providing a protective layer over the multiple gate lines; and patterning and cutting one or more gate lines of the multiple gate lines to facilitate defining multiple gate structures of the one or more semiconductor devices. Etching through the multilayer stack structure is facilitated by lithographically patterning the multilayer stack structure, and critical dimension feedback control is provided to at least one of the lithographically patterning or the etching through the multilayer stack structure.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: November 4, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Xiang Hu