SENSE AMPLIFIER READ LINE SHARING

Abstract

A memory is provided that practices global read line sharing by including: a global read line, the memory being adapted to be pre-charge the global read line prior to a read operation; an I/O circuit to receive the global read line; and a plurality of sense amplifiers, each sense amplifier being multiplexed with respect to the global read line such that only a selected one of the sense amplifiers in the plurality is activated during a read operation to determine a bit decision, the memory being adapted to discharge the pre-charged global read line if the bit decision from the activated sense amplifier equals one, the pre-charged global read line thereby staying pre-charged if the bit decision from the activated sense amplifier equals zero.

Description

RELATED APPLICATION

This application claims the benefit of U.S. Provisional Application No. 60/982,219, filed Oct. 24, 2007, the contents of which are hereby incorporated by reference.

FIELD OF THE INVENTION

The present invention relates to memories and memory devices, and more particularly to memory global read line sharing architectures.

BACKGROUND OF THE INVENTION

A memory such as a dynamic random access memory (DRAM) or a static random access memory (SRAM) has memory cells arranged in rows and columns. The rows correspond to word lines whereas columns correspond to bit lines. These bit lines travel in the column direction to sense amplifiers that make bit decisions during read operations in an SRAM and during both read and write operations in a DRAM. A memory cell is accessed by asserting the corresponding word line so that an access transistor conducts to couple the memory cell to the corresponding bit line. A sense amplifier may then read the contents of the accessed memory cell by sensing the voltage on the corresponding bit line.

Having sensed the voltage on the bit line, a conventional sense amplifier provides its bit decision on an output line that may be designated as a “global read line.” The global read line couples to input/output (I/O) circuits so that the resulting bit decision may be relayed to external circuits. Prior to a read operation, it is conventional to pre-charge the global read lines to a power supply voltage VDD. If a sense amplifier determines that the sensed bit line carries a logical one voltage state (assuming a logic high operation), the sense amplifier grounds the pre-charged global read line. Because the global read lines often run the entire column height of the memory, pre-charging and discharging them during read operations consumes substantial power.

Accordingly, there is a need in the art for memories having lower power consumption with regard to their global read lines.

SUMMARY OF THE INVENTION

To reduce power consumption, memory architectures are disclosed in which a plurality of sense amplifiers are multiplexed with regard to a single global read line. The global read line couples between the shared sense amplifier and a corresponding I/O circuit.

In accordance with one aspect of the invention, a memory is thus provided that includes: a global read line, the memory being adapted to be pre-charge the global read line prior to a read operation; an I/O circuit to receive the global read line; and a plurality of sense amplifiers, each sense amplifier being multiplexed with respect to the global read line such that only a selected one of the sense amplifiers in the plurality is activated during a read operation to determine a bit decision, the memory being adapted to discharge the pre-charged global read line if the bit decision from the activated sense amplifier equals one, the pre-charged global read line thereby staying pre-charged if the bit decision from the activated sense amplifier equals zero.

Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 illustrates a memory having multiplexed sense amplifiers with respect to a given global read line;

FIG. 2 is a circuit diagram of the multiplexing of FIG. 1 for an SRAM embodiment; and

FIG. 3 is a circuit diagram of the multiplexing of FIG. 1 for a DRAM embodiment.

To allow cross-referencing among the figures, like elements in the figures are provided like reference numerals.

DETAILED DESCRIPTION

Turning now to FIG. 1, a memory 100 is illustrated in which a plurality of sense amplifiers 101 are multiplexed onto a given global read line 105. Memory 100 includes a plurality of bit lines 110 arranged in columns that intersect with a plurality of word lines 115. To perform a read operation, the bit lines are pre-charged to a suitable voltage such as one-half a power supply voltage VDD. A selected word line may then be charged to the power supply voltage VDD. The increased word line voltage then turns on access transistors (not illustrated) so that the bit lines couple to memory cells (not illustrated) at the word line/bit line intersections. Because of the coupling of the memory cell to the bit line, the bit line voltage will change from the pre-charged state: in an active-high logic operation, the bit line voltage will increase from the pre-charged state if the accessed memory cell is storing a logical one whereas the bit line voltage will decrease from the pre-charged state if the accessed memory cell is storing a logical zero.

In memory 100, there is one active bit line per sense amplifier. However, it will be appreciated that alternative embodiments may have bit line multiplexing with respect to a given sense amplifier as disclosed in commonly-assigned U.S. application Ser. No. 12/018,996, the contents of which are incorporated by reference. As discussed in the background section, it is conventional for each sense amplifier to couple to a corresponding global read line to provide its bit decision to I/O circuits. The I/O circuits then drive an output line so that the external world may know the results of the read operation. However, in memory 100 a plurality of sense amplifiers multiplex onto each global read line. In memory 100, this multiplexing is 4:1 such that there are four sense amplifiers per global read line but it will be appreciated that such a multiplexing may be varied either higher or lower from four. As will be explained further herein, a given sense amplifier may be selected from the multiplexed group such that the remaining sense amplifiers do not couple to the shared global read line. Each global read line couples to a corresponding I/O circuit 120 that may latch the bit decision carried by the global read line and drive the bit decision externally from the memory on output lines q. In this fashion, a word may be read from memory 100 over the output lines q such that an i^th bit in the word is carried on output line q[i], an (i+1)^th bit is carried on output line q[i+1], and so on.

As compared to a conventional memory without global read line sharing, memory 100 saves substantial power because fewer global read lines need be charged and discharged. Moreover, memory 100 achieves reduced leakage currents because there is only one pre-charge of the global read line per multiplexed group of sense amplifiers.

The multiplexing of the sense amplifiers may be implemented in a number of fashions depending upon the type of memory. For example, the multiplexing of SRAM sense amplifiers is illustrated in FIG. 2. Prior to a read operation, a pre-charge circuit (not illustrated) pre-charges the global read line to a power supply voltage VDD. A controller 200 decodes an read address to generate an active low sense amplifier selection signal SENX [0:3] to select a particular sense amplifier 101 from the group of multiplexers (this embodiment is similar to that shown in FIG. 1 in that a 4:1 sense amplifier multiplexing occurs with respect to a given global read line 105). Each sense amplifier is isolated from ground through an NMOS transistor M1. The gate of M1 is driven by a corresponding NOR gate 205 output signal SEN that represents the logical NOR of the sense amplifier's SENX signal as well as an active low read enable signal Readx. The SEN signal is thus acting as a sense command for the corresponding sense amplifier. Because only one of the SENX signals (for example, SENX[0]) will be pulled low during a read operation, only the corresponding M1 transistor will conduct, thereby activating the corresponding sense amplifier to perform a sense operation on its accessed bit line (the bit lines of FIG. 1 are not illustrated in FIG. 2 for illustration clarity).

It is conventional for an SRAM sense amplifier to comprise a comparator that will drive its output signal low if the accessed bit line couples to a logic high memory cell. To pull the global read line low for such a logic-high-storing memory cell, each sense amplifier's output signal drives a corresponding inverter 210 that in turn drives a corresponding NMOS transistor M2 that couples between ground and the global read line. Accordingly, if a sense amplifier is sensing a logic high state on its accessed bit line, the corresponding M2 transistor will conduct, thereby pulling the global read line to ground. It will be appreciated that numerous alternative SRAM sense amplifier multiplexing embodiments may be implemented. For example, rather than activating a selected sense amplifier though a grounding transistor M1, the sense amplifiers could directly couple to ground but be isolated from the power supply voltage VDD through a PMOS transistor that would only conduct if both the corresponding SENX signal and the read enable signal Readx were low.

The read enable signal Readx may also be used to open the pass transistors (not illustrated) between the accessed bit lines and the corresponding sense amplifiers. Since a sense command must be generated to fire the sense amplifier after the bit line development in conventional SRAMs, it may be seen that the multiplexing scheme of FIG. 2 is implemented with relatively little overhead—just the provision of however many SENX lines are necessary, depending upon how many sense amplifiers are multiplexed onto a given global read line.

Turning now to FIG. 3, the multiplexing of DRAM sense amplifiers is illustrated. For illustration clarity, just a single DRAM sense amplifier 101 is shown from the group that will multiplex onto a given global read line 105. As contrasted with SRAM operation, a DRAM sense amplifier is slower as it must use gain and a regenerative latch function that are not necessary in an SRAM. Thus, each DRAM sense amplifier 101 is isolated from ground by an NMOS transistor M1 whose gate is controlled by an active high global enable signal (global to both read and write operations). The sense amplifier provides its active low output signal to a NOR gate 300 that also receives an active low output enable signal OEx[i], where i represents the ith DRAM sense amplifier within the multiplexed group. Thus a controller circuit (not illustrated but analogous to the controller of FIG. 2) will generate OEx[i] based upon a decoding of a read address. If OEx[i] and the sense amplifier output signal are both low, an output signal from the corresponding NOR gate 300 will go high, thereby causing a pull-down NMOS transistor M2 to conduct such that the global read line is pulled to ground through M2.

The above-described embodiments of the present invention are merely meant to be illustrative and not limiting. For example, although the global read line is generally a uni-directional in that the bit decision from the sense amplifier flows through the global read line to the corresponding I/O circuit, the global read line could also be made bi-directional. It will thus be obvious to those skilled in the art that various changes and modifications may be made without departing from this invention in its broader aspects. Therefore, the appended claims encompass all such changes and modifications as fall within the true spirit and scope of this invention.

Claims

1. A memory, comprising:

a global read line, the memory being adapted to be pre-charge the global read line prior to a read operation;

an I/O circuit to receive the global read line; and

a plurality of sense amplifiers, each sense amplifier being multiplexed with respect to the global read line such that only a selected one of the sense amplifiers in the plurality is activated during a read operation to determine a bit decision, the memory being adapted to discharge the pre-charged global read line if the bit decision from the activated sense amplifier equals one, the pre-charged global read line thereby staying pre-charged if the bit decision from the activated sense amplifier equals zero.