STRUCTURE AND METHOD FOR MANUFACTURING DEVICE WITH A V-SHAPE CHANNEL NMOSFET
A CMOS structure includes a v-shape surface in an nMOSFET region. The v-shape surface has an orientation in a (100) plane and extends into a Si layer in the nMOSFET region. The nMOSFET gate dielectric layer is a high-k material, such as Hf02. The nMOSFET has a metal gate layer, such as Ta. Poly-Si is deposited on top of the metal gate layer.
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The present invention relates to a semiconductor device and method of manufacturing the same and, more particularly, to a structure and method for manufacturing a complementary metal-oxide-semiconductor (CMOS) with a V-shape channel nMOSFET.
Scaling of gate length of metal-oxide-semiconductor field-effect transistors (MOSFETs) can enhance performance. However, it increases stand-by power of very-large-scale integration (VLSI). Therefore, power consumption is a serious problem for VLSI. MOSFETs with long channel gate length have low stand-by power, but performance is relatively poor.
Increasing of mobility of electrons or holes can enhance performance without increasing stand-by power. Mobility of electrons or holes depends on surface crystalline orientations in silicon. In a MOSFET with an n-type channel (nMOSFET), electrons are responsible for conduction. In a MOSFET with a p-type channel (pMOSFET), holes are responsible for conduction. It is desirable to build an nMOSFET in a (100) surface and pMOSFET in a (110) surface in order to obtain the maximum electron mobility for the nMOSFET and the maximum hole mobility for the pMOSFET.
However, it is difficult and/or expensive to manufacture substrates that have hybrid surface crystalline orientations.
SUMMARY OF THE INVENTIONIn a first aspect of the invention, a method of forming a device includes forming an oxide layer on top of a CMOS structure having an nMOSFET region and a pMOSFET region in a (110) surface, wherein a top of the oxide layer is co-planar with a top of the pMOSFET region. The method includes patterning a hardmask nitride to cover the oxide layer above the pMOSFET region. The method includes removing poly-Si in the nMOSFET region. The method includes removing gate oxide in the nMOSFET region to expose a Si layer in a channel area of the nMOSFET region. The method includes removing Si to form a cavity in the channel area of the nMOSFET region. The method includes performing selective Si epitaxial growth in the cavity to form a V-shape surface having an orientation in a (100) plane. The method includes removing the hardmask nitride above the pMOSFET region. The method includes depositing an nMOSFET gate dielectric layer. The method includes depositing an nMOSFET metal gate layer, such that a top surface of the nMOSFET metal gate layer is below the top of the oxide layer. The method includes depositing poly-Si on top of the nMOSFET metal gate layer, such that a top surface of the Poly-Si is below the top of the oxide layer. The method further includes removing a portion of the nMOSFET gate dielectric layer, such that a top surface of the nMOSFET gate dielectric layer is below the top surface of the oxide layer. The method also includes removing the oxide layer.
In another aspect of the invention, a method of forming a device includes depositing an oxide layer on top of a CMOS structure having an nMOSFET region and a pMOSFET region in a (110) surface. The method includes performing a chemical mechanical polish (CMP) of the oxide layer. The method includes patterning a hardmask nitride to cover the oxide layer above the pMOSFET region. The method includes performing a first reactive ion etching (RIE) to remove poly-Si in the nMOSFET region. The method includes performing a second RIE to remove gate oxide in the nMOSFET region and to expose a Si layer in a channel area of the nMOSFET region. The method includes performing a third RIE to remove Si to form a cavity in the channel area of the nMOSFET region, wherein the cavity has a depth less than the thickness of the Si layer. The method includes performing selective Si epitaxial growth in the cavity to form a V-shape surface having an orientation in a (100) plane. The method includes removing the hardmask nitride above the pMOSFET region. The method includes depositing an nMOSFET gate dielectric layer. The method includes depositing an nMOSFET metal gate layer. The method includes etching back a portion of the nMOSFET metal gate layer, such that a top surface of the nMOSFET metal gate layer is below the top of the oxide layer. The method includes depositing in-situ doped poly-Si on top of the nMOSFET metal gate layer. The method includes etching back a portion the in-situ doped poly-Si, such that a top surface of the in-situ doped poly-Si is below the top of the oxide layer. The method further includes etching back a portion of the nMOSFET gate dielectric layer, such that a top surface of the nMOSFET gate dielectric layer is below the top of the oxide layer. The method also includes etching back the oxide layer.
In a further aspect of the invention, a device includes a CMOS structure having an nMOSFET region and a pMOSFET region. The device includes a V-shape surface in the nMOSFET region, the V-shape surface having an orientation in a (100) plane and extending into a Si layer in the nMOSFET region. The device includes a gate dielectric layer in the V-shape surface. The device further includes a metal gate layer on top of the gate dielectric layer. The device also includes poly-Si on top of the metal gate layer.
The present invention is described in the detailed description below, in reference to the accompanying drawings that depict non-limiting examples of exemplary embodiments of the present invention.
The invention relates to a semiconductor device and method of manufacturing the same and, more particularly, to a structure and method for manufacturing a device with a V-shape channel nMOSFET.
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The method as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
Claims
1. A method of forming a device, comprising:
- forming an oxide layer on top of a CMOS structure having an nMOSFET region and a pMOSFET region in a (110) surface, wherein a top of the oxide layer is co-planar with a top of the pMOSFET region;
- patterning a hardmask nitride to cover the oxide layer above the pMOSFET region;
- removing poly-Si in the nMOSFET region;
- removing gate oxide in the nMOSFET region to expose a Si layer in a channel area of the nMOSFET region;
- removing Si to form a cavity in the channel area of the nMOSFET region;
- performing selective Si epitaxial growth in the cavity to form a V-shape surface having an orientation in a (100) plane;
- removing the hardmask nitride above the pMOSFET region;
- depositing an nMOSFET gate dielectric layer;
- depositing an nMOSFET metal gate layer, such that a top surface of the nMOSFET metal gate layer is below the top of the oxide layer;
- depositing poly-Si on top of the nMOSFET metal gate layer, such that a top surface of the Poly-Si is below the top of the oxide layer;
- removing a portion of the nMOSFET gate dielectric layer, such that a top surface of the nMOSFET gate dielectric layer is below the top surface of the oxide layer; and
- removing the oxide layer.
2. A method according to claim 1, wherein the forming the oxide layer step comprises performing a chemical mechanical polish (CMP) of the oxide layer.
3. A method according to claim 1, wherein the removing the poly-Si step comprises performing a first reactive ion etching (RIE).
4. A method according to claim 1, wherein the removing the gate oxide step comprises performing a second RIE.
5. A method according to claim 1, wherein the removing the Si step comprises performing a third RIE.
6. A method according to claim 1, wherein the nMOSFET gate dielectric layer is a high-k material.
7. A method according to claim 6, wherein the high-k material is selected from the group consisting of: HfO2, ZrO2, Al2O3, TiO2, La2O3, SrTiO3 and LaAlO3.
8. A method according to claim 1, wherein the nMOSFET metal gate layer is selected from the group consisting of: TaN, TiN, TiAlN and WN.
9. A method according to claim 1, wherein the poly-Si is in-situ doped with P.
10. A method according to claim 1, wherein the removing a portion of the nMOSFET gate dielectric layer step comprises etching back the gate dielectric layer.
11. A method according to claim 1, wherein the removing the oxide layer step comprises etching back the oxide layer.
12. A method according to claim 1, wherein the cavity has a depth less than the thickness of the Si layer.
13. A method of forming a device, comprising:
- depositing an oxide layer on top of a CMOS structure having an nMOSFET region and a pMOSFET region in a (110) surface;
- performing a chemical mechanical polish (CMP) of the oxide layer;
- patterning a hardmask nitride to cover the oxide layer above the pMOSFET region;
- performing a first reactive ion etching (RIE) to remove poly-Si in the nMOSFET region;
- performing a second RIE to remove gate oxide in the nMOSFET region and to expose a Si layer in a channel area of the nMOSFET region;
- performing a third RIE to remove Si to form a cavity in the channel area of the nMOSFET region, wherein the cavity has a depth less than the thickness of the Si layer;
- performing selective Si epitaxial growth in the cavity to form a V-shape surface having an orientation in a (100) plane;
- removing the hardmask nitride above the pMOSFET region;
- depositing an nMOSFET gate dielectric layer;
- depositing an nMOSFET metal gate layer;
- etching back a portion of the nMOSFET metal gate layer, such that a top surface of the nMOSFET metal gate layer is below the top of the oxide layer;
- depositing in-situ doped poly-Si on top of the nMOSFET metal gate layer;
- etching back a portion the in-situ doped poly-Si, such that a top surface of the in-situ doped poly-Si is below the top of the oxide layer;
- etching back a portion of the nMOSFET gate dielectric layer, such that a top surface of the nMOSFET gate dielectric layer is below the top of the oxide layer; and
- etching back the oxide layer.
14. A method according to claim 13, wherein the nMOSFET gate dielectric layer is a high-k material.
15. A method according to claim 14, wherein the high-k material is selected from the group consisting of: HfO2, ZrO2, Al2O3, TiO2, La2O3, SrTiO3 and LaAlO3.
16. A method according to claim 13, wherein the nMOSFET metal gate layer is selected from the group consisting of: TaN, TiN, TiAlN and WN.
17. A device, comprising:
- a structure having an nMOSFET region;
- a V-shape surface in the nMOSFET region, the V-shape surface having an orientation in a (100) plane and extending into a Si layer in the nMOSFET region;
- a gate dielectric layer in the V-shape surface;
- a metal gate layer on top of the gate dielectric layer; and
- poly-Si on top of the metal gate layer.
18. A device according to claim 17, wherein the gate dielectric layer is a high-k material.
19. A device according to claim 18, wherein the high-k material is selected from the group consisting of: HfO2, ZrO2, Al2O3, TiO2, La2O3, SrTiO3 and LaAlO3.
20. A device according to claim 18, wherein the metal gate layer is selected from the group consisting of: TaN, TiN, TiAlN and WN.
21. A device according to claim 17, wherein the poly-Si is in-situ doped with P.
22. A device according to claim 17, wherein the V-shape surface has a depth less than the thickness of the Si layer.
Type: Application
Filed: Mar 25, 2008
Publication Date: Oct 1, 2009
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION (Armonk, NY)
Inventors: Huilong Zhu (Poughkeepsie, NY), Zhijiong Luo (Carmel, NY)
Application Number: 12/054,738
International Classification: H01L 29/78 (20060101); H01L 21/336 (20060101);