SOURCE AND BODY CONTACT STRUCTURE FOR TRENCH-DMOS DEVICES USING POLYSILICON
A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a oxide disposed on top of the source region and the gate electrode, and a doped polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide. Methods for manufacturing such device are also disclosed.
Latest ALPHA & OMEGA SEMICONDUCTOR, LTD. Patents:
This invention generally relates to vertical power MOSFET devices and more particularly to power MOSFET devices having improved source and body contact structure for highest-performance.
BACKGROUND OF THE INVENTIONConventionally, a power metal oxide silicon field effect transistor (power MOSFET) is used to provide high voltage circuits for power integrated circuit applications. Various internal parasitic components often impose design and performance limitations on a conventional power MOSFET. Among these parasitic components in a MOSFET transistor, special care must be taken in dealing with a parasitic npn bipolar junction transistor (BJT) formed between the source, the body, and the drain of a MOSFET device. The parasitic current, which flows from the source to the drain and through the body as opposed to a channel, tends to run away, i.e., the more current, the more the bipolar action turns on. For the purpose of reducing parasitic bipolar structure action and improving the device ruggedness, the base resistance of the body or drain to source on-resistance (Rds-on) needs to be minimized. Standard solution is to dope the body as much as possible to reduce base resistance, which reduces current gain of bipolar and forces to push more parasitic current before bipolar turns on since base-emitter voltage VBE is a function of resistance:
VBE=Iparasitic×Rbase-local
For typical BJT devices, VBE is about 0.5V to 0.6V to turn on the bipolar action.
U.S. Pat. No. 5,930,630 discloses a butted trench-contact MOSFET cell structure having a self aligned deep and shallow high-concentration body-dopant regions. A top portion of a lightly doped source region is removed to reduce contact resistance. However, horizontal butted contacts require a lot of space which adversely impacts both cell density and Rds-on. In addition, the trench-contacts can have a high source resistance since a small portion of the N+ source (for NMOS) is contacted by the source metal. Also, for the trench-contact, if the Boron (for NMOS) body contact implant at the bottom of the trench is not vertical, there can be compensation of the N+ source (for NMOS) which results in excessive Rds-on because of increased source resistance.
U.S. Pat. No. 5,684,319 discloses a DMOS device structure, and method of manufacturing the same features a self-aligned source and body contact structure which requires no additional masks. N+ polysilicon spacers are used to form the source region at the periphery of the gate polysilicon. However, the N+ polysilicon source only improves the source contact, which lowers the resistance, but it has no effect on body region.
It would be desirable to develop a structure which achieves self-aligned source/body contact without using mask, highly rugged and robust structure with low-resistance source and body contact. It would be further desirable to develop a structure which achieves low-thermal budget to realize shallow junctions, compatible with stripe and closed-cell geometries, compatible with standard foundry process, with standard metallization schemes to achieve low contact resistivity, compatible with ultra-small cell-pitch. It would be further desirable to produce a device with a low-cost of manufacture.
It is within this context that embodiments of the present invention arise.
Objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which:
Although the following detailed description contains many specific details for the purposes of illustration, anyone of ordinary skill in the art will appreciate that many variations and alterations to the following details are within the scope of the invention. Accordingly, the exemplary embodiments of the invention described below are set forth without any loss of generality to, and without imposing limitations upon, the claimed invention.
The N+ doped polysilicon spacer 106 increases N+ source contact area at the sidewall of the top N+ source region 114 and spaces a heavily P-type implanted contact region 115 formed in the P-body layer 112 away from the top N+ source region 114, and hence away from a channel region 118 formed on the sidewalls of the gate trenches in the body layer 112, to minimize any impact on the threshold voltage of the transistor.
The heavily implanted contact region 115 may be formed, e.g., using a shallow implant of the same conductivity type as the body layer 112, The implant may be done after etching the poly-Si spacers 106 and before metallization. The contact region 115 helps to reduce the body contact resistance. The benefits of spacing the heavily doped P+ body contact region 115 away from the source 114 is really to space the P+ body contact region 115 away from the channel region 118, to ensure that the extra doping does not get close to trench sidewall regions. Any dopant diffusion which reaches the trench sidewall surfaces might result in an increase in the threshold voltage which is detrimental to the performance.
The N+ doped polysilicon spacer 107 allows different types of doping to be done in the top source region.
A heavily P-type implanted contact region 215 may be formed in the P-body layer 212 proximate the spacer 206 and spaced away from the top N+ source region 214, and hence away from a channel region 219 formed on the sidewalls of the gate trenches in the body layer 212, to minimize any impact on the threshold voltage of the transistor by the body contact implant(s).
A heavily P-type implanted contact region 315 may be formed in the P-body layer 312 proximate the spacer 306 and spaced away from the top N+ source region 314, and hence away from a channel region 319 formed on the sidewalls of the gate trenches in the body layer 312, to minimize any impact on the threshold voltage of the transistor.
The trench MOSFET 300 further includes a barrier metal 304 disposed on top of the doped N+ polysilicon spacer 306 and the vertically etched oxide 308, a Tungsten plug 318 adjacent to the barrier metal 304 and a source metal 302 disposed on top of the barrier metal 304 and the Tungsten plug 318.
A configuration of the type shown in
There are a number of different techniques for fabricating MOSFET devices of the types described above. By way of example,
As shown in
As shown in
An oxide 418, such as boro-phospho-silicate glass (BPSG), is formed on top of the gate 410 and the source regions 416 following with the densification and reflow (e.g., at 800 to 900 C) as shown in
A portion of the oxide 418 and the mask 415 are dielectric etched using a contact mask, to expose selected portions of the source regions 416 as shown in
An N+ doped polysilicon layer 420 is deposited on top and sidewall of the remaining portions of the source region 416 and on top of the P-body layer 414 and the oxide 418 as shown in
As shown in
An N+ doped polysilicon layer 420 is deposited on top and sidewall of the remaining portions of the source region 416 and on top of the P-body layer 414 and the oxide 418 as shown in
As shown in
As shown in
An oxide 618, such as boro-phospho-silicate glass, is formed on top of the gate 610 and the low-doped N− source regions 616 followed by a densification and reflow as shown in
An N+ doped polysilicon layer 620 is deposited on top and sidewall of the remaining portions of the source region 616 and on top of the P-body layer 614 and the oxide 618 as shown in
Embodiments of the present invention allow for the fabrication of N-channel or P-channel devices with low contact resistance and parasitic bipolar action. It is noted that although the foregoing examples relate to N-channel devices and their fabrication, those of skill in the art will recognize that the same teachings may be applied to P-channel devices and their fabrication. Since semiconductor materials of opposite polarity (e.g., P-type and N-type) differ primarily in the polarity of the dopants used, the above teachings may be applied to P-channel devices by reversing the polarity of the semiconductor layers and dopants discussed above.
While the above is a complete description of the preferred embodiment of the present invention, it is possible to use various alternatives, modifications and equivalents. Therefore, the scope of the present invention should be determined not with reference to the above description but should, instead, be determined with reference to the appended claims, along with their full scope of equivalents. Any feature, whether preferred or not, may be combined with any other feature, whether preferred or not. In the claims that follow, the indefinite article “A”, or “An” refers to a quantity of one or more of the item following the article, except where expressly stated otherwise. The appended claims are not to be interpreted as including means-plus-function limitations, unless such a limitation is explicitly recited in a given claim using the phrase “means for.”
Claims
1. A semiconductor device comprising:
- a P-body layer formed in an N-epitaxial layer;
- a gate electrode formed in a trench in the P-body and N-epitaxial layers;
- a top source region disposed on the P-body layer next to the gate electrode;
- a gate oxide disposed between the gate electrode and the top source region, the P-body and the N-epitaxial layers;
- a drain region formed by a substrate disposed below the bottom of the gate electrode and below the P-body layer
- an oxide disposed on top of the source region and the gate electrode; and
- a doped N+ polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide.
2. The semiconductor device of claim 1, further comprising an exposed P+ Body contact region in an upper portion of the P-Body region, adjacent to the N+ polysilicon spacer.
3. The semiconductor device of claim 2, wherein the exposed P+ body contact region has a top surface which is recessed below the bottom surface of the N+ source and spaced away from the N+ source by the N+ Polysilicon spacer.
4. The semiconductor device of claim 1 wherein the semiconductor device is an N-channel device.
5. The semiconductor device of claim 1 further comprising a barrier metal disposed on top of the doped N+ polysilicon spacer and the oxide.
6. The semiconductor device of claim 1 wherein the N+ polysilicon spacer is formed on a shelf on a portion of a top surface of the source region that is not covered by the oxide wherein the shelf is configured such that the N+ Polysilicon spacer contacts the top source region on a horizontal surface as well as a vertical surface.
7. The semiconductor device of claim 3 wherein a portion of a top surface of the P-body region not underlying the source region is recessed to a lower level than a portion of the top surface of the P-body region underlying the source region
8. The semiconductor device of claim 1 wherein a portion of a top surface of the P-body region not underlying the source region is recessed to a lower level than a portion of the top surface of the P-body region underlying the source region.
9. The semiconductor device of claim 1 wherein the N+ polysilicon spacer extends to a top portion of the source region.
10. The semiconductor device of claim 1 wherein the oxide is a reflowed oxide.
11. The semiconductor device of claim 1 further comprising Tungsten-plugs adjacent to the barrier metal and over the P-body region.
12. The semiconductor device of claim 1 wherein the top source region comprises N+ source.
13. The semiconductor device of claim 1 wherein the top source region comprises N− source.
14. A method for manufacturing a semiconductor device comprising:
- a) providing an N-type epitaxial (N-epi) layer;
- b) forming a trench mask on top of the N-epi layer;
- c) etching the N-epi layer through the trench mask to a predetermined depth to form a trench;
- d) forming a gate oxide on a bottom and sidewalls of the trench;
- e) filling a remaining space in the trench with a conductive material to form a gate electrode;
- f) removing the trench mask;
- g) implanting and diffusing dopants into a top region of the N-epi layer to form a P-body layer;
- h) implanting and diffusing dopants into a top region of the P-body layer to form a source region;
- i) forming oxide on top of the gate electrode and the source region;
- j) etching portions of the oxide to expose selected portions of the source region;
- k) etching selected portions of the source region not covered by the oxide down to the p-body layer;
- l) depositing N+ doped polysilicon on sidewalls of remaining portions of the source region and the oxide; and
- m) etching back the N+ doped polysilicon to form an N+ doped polysilicon spacer disposed along the sidewalls of the remaining portions of the source region and the oxide.
15. The method of claim 14 wherein the conductive material is N+ doped polysilicon.
16. The method of claim 14 wherein c), d) and e) are implemented in a way that results in the conductive material of the gate electrode being recessed to below a surface of the N-epi layer.
17. The method of claim 14, further comprising, after m) doping an exposed portions of the P-body layer P+ to form a body contact region proximate the polysilicon spacer.
18. The method of claim 14, after step m, further comprising:
- depositing barrier metal over the P-body layer, N+ doped polysilicon spacer and the oxide;
- depositing and patterning a metal on top of the barrier metal; and
- depositing and patterning a passivation layer on top of the patterned metal.
19. The method of claim 14, after step e, further comprising:
- etching back the conductive material filled in the trench to a level below a top surface of the N-epi layer.
20. The method of claim 14, wherein step h) comprises implanting and diffusing dopants into the top region of the P-body layer to form an N+ source region.
21. The method of claim 14, wherein step h) comprises implanting and diffusing dopants into the top region of the P-body layer to form an N− polysilicon source region.
22. The method of claim 14, after step k) further comprising etching a portion of a top surface of the P-body region not covered by the oxide to a level below that of a bottom surface of the source region.
23. A semiconductor device comprising:
- a body layer formed on an epitaxial layer, wherein the body layer and epitaxial layer are semiconductors of opposite polarity types;
- a gate electrode formed in a trench in the body and epitaxial layers;
- a top source region disposed on the body layer next to the gate electrode;
- a gate oxide disposed between the gate electrode and the top source region, the body and the epitaxial layers;
- a drain region formed by a substrate disposed below the bottom of the gate electrode and below the body layer;
- an oxide disposed on top of the source region and the gate electrode; and
- a doped N+ polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide.
24. A method for manufacturing a semiconductor device comprising:
- a) providing an epitaxial layer of a first polarity type semiconductor;
- b) forming a trench mask on top of the epitaxial layer;
- c) etching the epitaxial layer through the trench mask to a predetermined depth to form a trench;
- d) forming a gate oxide on a bottom and sidewalls of the trench;
- e) filling a remaining space in the trench with a conductive material to form a gate electrode;
- f) removing the trench mask;
- g) implanting and diffusing dopants into a top region of of an opposite polarity type to that of the epitaxial layer into the epitaxial layer to form a body layer of an opposite polarity to that of the epitaxial layer;
- h) implanting and diffusing dopants into a top region of the body layer to form a source region;
- i) forming oxide on top of the gate electrode and the source region;
- j) etching portions of the oxide to expose selected portions of the source region;
- k) etching selected portions of the source region not covered by the oxide down to the body layer;
- l) depositing doped polysilicon on sidewalls of remaining portions of the source region and the oxide; and
- m) etching back the doped polysilicon to form a doped polysilicon spacer disposed along the sidewalls of the remaining portions of the source region and the oxide.
Type: Application
Filed: Mar 31, 2008
Publication Date: Oct 1, 2009
Applicant: ALPHA & OMEGA SEMICONDUCTOR, LTD. (Hamilton)
Inventors: Francois Hebert (San Mateo, CA), Anup Bhalla (Santa Clara, CA)
Application Number: 12/060,096
International Classification: H01L 29/78 (20060101); H01L 21/336 (20060101);