Vertical Transistor (epo) Patents (Class 257/E21.41)
  • Patent number: 10541249
    Abstract: A method for forming a 3D memory device is disclosed. The method includes: forming an alternating dielectric stack including multiple first dielectric layers and second dielectric layers on a substrate; forming a channel hole penetrating the alternating dielectric stack, a first diameter of a lower portion of the channel hole being smaller than a second diameter of an upper portion of the channel hole; forming a channel structure including a functional layer in the channel hole, the functional layer including a storage layer; forming an electrode plug in the upper portion of the channel hole; replacing the storage layer in the functional layer in the upper portion of the channel hole with a second insulating layer; and replacing the second dielectric layers in the alternating dielectric stack with conductive layers.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: January 21, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Ziqi Chen, Guanping Wu
  • Patent number: 10522552
    Abstract: The disclosed technology generally relates semiconductor devices and more particularly to a vertical transistor device, and a method of fabricating the same. In one aspect, the method includes providing, on a substrate, a fin formed of a stack of a first layer, a second layer and a third layer, wherein the second layer is positioned above the first layer and the third layer is positioned above the second layer. The method additionally includes forming a dielectric on the sidewalls of the first and third layers of the fin selectively against a sidewall of the second layer, and the method additionally includes forming a gate contacting layer for contacting a sidewall of the second layer. The first and third layers define a source region and a drain region, respectively, of the vertical transistor device. The second layer defines a channel region of the vertical transistor device.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: December 31, 2019
    Assignee: IMEC vzw
    Inventors: Julien Ryckaert, Naoto Horiguchi, Dan Mocuta, Trong Huynh Bao
  • Patent number: 10483366
    Abstract: A semiconductor device includes a third first-conductivity-type semiconductor layer on a semiconductor substrate, and a first pillar-shaped semiconductor layer on the semiconductor substrate. The first pillar-shaped semiconductor layer including a first first-conductivity-type semiconductor layer, a first body region, a second first-conductivity-type semiconductor layer, a first second-conductivity-type semiconductor layer, a second body region, a second second-conductivity-type semiconductor layer, and a third second-conductivity-type semiconductor layer. A first gate insulating film is around the first body region, and a first gate is around the first gate insulating film. A second gate insulating film is around the second body region and a second gate is around the second gate insulating film. An output terminal is connected to the second first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer, and a first contact connects the first gate and the second gate.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: November 19, 2019
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 10446658
    Abstract: A trench power semiconductor device and a manufacturing method thereof are provided. The trench power semiconductor device includes a substrate, an epitaxial layer disposed on the substrate, and a gate structure. The epitaxial layer has at least one trench formed therein, and the gate structure is disposed in the trench. A gate structure includes a lower doped region and an upper doped region disposed above the lower doped region to form a PN junction. The concentration of the impurity decreases along a direction from a peripheral portion of the upper doped region toward a central portion of the upper doped region.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: October 15, 2019
    Assignee: SUPER GROUP SEMICONDUCTOR CO., LTD.
    Inventor: Hsiu-Wen Hsu
  • Patent number: 10418379
    Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: September 17, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Guangyu Huang, Haitao Liu, Chandra Mouli, Justin B. Dorhout, Sanh D. Tang, Akira Goda
  • Patent number: 10418271
    Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: September 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Teng-Chun Tsai, Li-Ting Wang, De-Fang Chen, Cheng-Tung Lin, Chih-Tang Peng, Chien-Hsun Wang, Bing-Hung Chen, Huan-Just Lin, Yung-Cheng Lu
  • Patent number: 10263122
    Abstract: A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor including a gate contact patterned in a self-aligned process. In one embodiment, we disclose a semiconductor device, including a semiconductor substrate and a first vertical field effect transistor (vFET) including a bottom source/drain (S/D) region disposed on the semiconductor substrate; a fin disposed above the bottom S/D region; a top source/drain (S/D) region disposed above the fin and having a top surface; and a gate having a top surface higher than the top surface of the top S/D region. A gate contact may be formed over the gate.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: April 16, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Ruilong Xie, Tek Po Rinus Lee, Lars Liebmann
  • Patent number: 10236363
    Abstract: Device structures and fabrication methods for a vertical field-effect transistor. A semiconductor fin is formed that projects from a first source/drain region. A first spacer layer is formed on the first source/drain region. A dielectric layer is formed that extends in the vertical direction from the first spacer layer to a top surface of the semiconductor fin. The dielectric layer is recessed in the vertical direction, and a second spacer layer is formed on the recessed dielectric layer such that the dielectric layer is located in the vertical direction between the first spacer layer and the second spacer layer. After the dielectric layer is removed to open a space between the first spacer layer and the second spacer layer, a gate electrode is formed in the space. The vertical field-effect transistor has a gate length that is equal to a thickness of the recessed dielectric layer.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: March 19, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Chun-chen Yeh, Kangguo Cheng, Tenko Yamashita
  • Patent number: 10217665
    Abstract: A semiconductor device includes a first pillar-shaped semiconductor layer formed on a semiconductor substrate; a first first-conductivity-type semiconductor layer formed in the first pillar-shaped semiconductor layer; a third first-conductivity-type semiconductor layer formed in the first pillar-shaped semiconductor layer and located at a higher position than the first first-conductivity-type semiconductor layer; a first gate insulating film formed so as to surround a region of the first pillar-shaped semiconductor layer sandwiched between the first first-conductivity-type semiconductor layer and the third first-conductivity-type semiconductor layer; a first gate formed so as to surround the first gate insulating film; a second gate insulating film formed so as to surround a region of the first pillar-shaped semiconductor layer sandwiched between the first first-conductivity-type semiconductor layer and the third first-conductivity-type semiconductor layer; and a second gate formed so as to surround the secon
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: February 26, 2019
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 10109642
    Abstract: In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: October 23, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Hoon Son, Jong-Wook Lee, Jong-Hyuk Kang
  • Patent number: 10096709
    Abstract: Aspect ratio trapping (ART) approaches for fabricating vertical semiconductor devices and vertical semiconductor devices fabricated there from are described. For example, a semiconductor device includes a substrate with an uppermost surface having a first lattice constant. A first source/drain region is disposed on the uppermost surface of the substrate and has a second, different, lattice constant. A vertical channel region is disposed on the first source/drain region. A second source/drain region is disposed on the vertical channel region. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: October 9, 2018
    Assignee: Intel Corporation
    Inventors: Van H. Le, Benjamin Chu-Kung, Gilbert Dewey, Jack T. Kavalieros, Ravi Pillarisetty, Willy Rachmady, Marko Radosavljevic, Matthew V. Metz, Niloy Mukherjee, Robert S. Chau
  • Patent number: 10043864
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a first electrode. The third semiconductor layer is provided between the first semiconductor layer and the second semiconductor layer. The first electrode opposes the third semiconductor layer. An orientation ratio of the third semiconductor layer is higher than an orientation ratio of the first semiconductor layer.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: August 7, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Minoru Oda, Shinji Mori, Kiwamu Sakuma, Masumi Saitoh
  • Patent number: 10026826
    Abstract: A semiconductor device includes a first type region including a first conductivity type and a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a gate electrode surrounding at least some of the channel region. A first gate edge of the gate electrode is separated a first distance from a first type region edge of the first type region and a second gate edge of the gate electrode is separated a second distance from a second type region edge of the second type region. The first distance is less than the second distance.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: July 17, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Jean-Pierre Colinge, Carlos H. Diaz, Yeh Hsu, Tsung-Hsing Yu, Chia-Wen Liu
  • Patent number: 9941390
    Abstract: The disclosure relates to a method of fabricating a vertical MOS transistor, comprising the steps of: forming, above a semiconductor surface, a conductive layer in at least one dielectric layer; etching a hole through at least the conductive layer, the hole exposing an inner lateral edge of the conductive layer and a portion of the semiconductor surface; forming a gate oxide on the inner lateral edge of the conductive layer and a bottom oxide on the portion of the semiconductor surface; forming an etch-protection sidewall on the lateral edge of the hole, the sidewall covering the gate oxide and an outer region of the bottom oxide, leaving an inner region of the bottom oxide exposed; etching the exposed inner region of the bottom oxide until the semiconductor surface is reached; and depositing a semiconductor material in the hole.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: April 10, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Philippe Boivin
  • Patent number: 9929240
    Abstract: An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: March 27, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Igor Polishchuk, Sagy Charel Levy, Krishnaswamy Ramkumar
  • Patent number: 9899486
    Abstract: An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: February 20, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Igor Polishchuk, Sagy Charel Levy, Krishnaswamy Ramkumar
  • Patent number: 9786774
    Abstract: The disclosure relates to a semiconductor device. An exemplary structure for a semiconductor device comprises a nanowire structure comprising a channel region between a source region and a drain region; and a metal gate surrounding a portion the channel region, wherein the metal gate comprising a first gate portion adjacent to the source region having a first thickness and a second gate portion adjacent to the drain region having a second thickness less than the first thickness.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: October 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jean-Pierre Colinge, Chi-Wen Liu
  • Patent number: 9780215
    Abstract: A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film; a second step of forming a pillar-shaped semiconductor layer and a first dummy gate; a third step of forming a second dummy gate; a fourth step of forming a fifth insulating film and a sixth insulating film; a fifth step of depositing a first interlayer insulating film, removing the second dummy gate and the first dummy gate, forming a gate insulating film, depositing metal, and performing etch back to form a gate electrode and a gate line; a seventh step of forming a seventh insulating film; and an eighth step of forming insulating film sidewalls, forming a first epitaxially grown layer on the fin-shaped semiconductor layer, and forming a second epitaxially grown layer on the pillar-shaped semiconductor layer.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: October 3, 2017
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9754788
    Abstract: A manufacturing method of a semiconductor structure having an array area and a periphery area is provided. The manufacturing method includes the following steps. A substrate is provided. A plurality of trenches is formed on the substrate. The plurality of trenches is filled with insulating material to form at least one first insulating layer. A polysilicon layer is deposited on the substrate and the first insulating layer. A photoresist mask is formed on the periphery area. A portion of the polysilicon layer on the array area is etched, such that a top surface of the polysilicon layer on the array area is higher than the first insulating layer and lower than a top surface of the polysilicon layer on the periphery area. The photoresist mask is removed. A planarization process is implemented to remove a portion of the polysilicon layer on the array area and on the periphery area.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: September 5, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ji-Gang Pan, Han-Chuan Fang, Boon-Tiong Neo
  • Patent number: 9698261
    Abstract: The present disclosure relates to a vertical transistor device having rectangular vertical channel bars extending between a source region and a drain region, and an associated method of formation. In some embodiments, the vertical transistor device has a source region disposed over a semiconductor substrate. A channel region with one or more vertical channel bars is disposed over the source region. The one or more vertical channel bars have a bottom surface abutting the source region that has a rectangular shape (i.e., a shape with four sides, with adjacent sides of different length, and four right angles). A gate region is located over the source region at a position abutting the vertical channel bars, and a drain region is disposed over the gate region and the vertical channel bars. The rectangular shape of the vertical channel bars provides for a vertical device having good performance and cell area density.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: July 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hao Wang, Jhon Jhy Liaw, Wai-Yi Lien, Jia-Chuan You, Yi-Hsun Chiu, Ching-Wei Tsai, Wei-Hao Wu
  • Patent number: 9673321
    Abstract: An opening extending through a gate insulating layer and a gate conductor layer is formed in the circumferential portion of a Si pillar at an intermediate height of the Si pillar. A laminated structure including two sets each including a Ni film, a poly-Si layer containing donor or acceptor impurity atoms, and a SiO2 layer is formed so as to surround the opening. A heat treatment is carried out to form silicide from the poly-Si layers and this silicide formation causes the resultant NiSi layers to protrude and come into contact with the side surface of the Si pillar. The donor or acceptor impurity atoms diffuse from the NiSi layers into the Si pillar to thereby form an N+ region and a P+ region serving as a source or a drain of SGTs.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: June 6, 2017
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Nozomu Harada
  • Patent number: 9640651
    Abstract: A semiconductor device includes a termination trench surrounding a region in which a plurality of gate trenches is provided; a p-type lower end region being in contact with a lower end of the termination trench; a p-type outer circumference region being in contact with the termination trench from an outer circumferential side and exposed on a surface of the semiconductor device; a plurality of guard ring regions of a p-type provided on an outer circumferential side of the p-type outer circumference region and exposed on the surface; and an n-type outer circumference region separating the p-type outer circumference region from the guard ring regions and separating the guard ring regions from each another.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: May 2, 2017
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Hidefumi Takaya, Jun Saito, Akitaka Soeno, Kimimori Hamada, Shoji Mizuno, Sachiko Aoi, Yukihiko Watanabe
  • Patent number: 9601618
    Abstract: A semiconductor device includes a fin-shaped semiconductor layer on a semiconductor substrate and that extends in a first direction with a first insulating film around the fin-shaped semiconductor layer. A pillar-shaped semiconductor layer resides on the fin-shaped semiconductor layer. A width of the bottom of the pillar-shaped semiconductor layer is equal to a width of the top of the fin-shaped semiconductor layer. A gate insulating film is around the pillar-shaped semiconductor layer and a metal gate electrode is around the gate insulating film. A metal gate line is connected to the metal gate electrode, and a nitride film is on an entire top surface of the metal gate electrode and the metal gate line, except at a bottom of a contact.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: March 21, 2017
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9601626
    Abstract: A semiconductor device includes a fin structure protruding from a substrate and having a top face and a first side face and a second side face opposite to the first side face, and first semiconductor layers disposed over the first and second side faces of the fin structure. A thickness in a vertical direction of the first semiconductor layers is smaller than a height of the fin structure.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: March 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung Ying Lee, Yasutoshi Okuno, Chien-Chang Su, Wang-Chun Huang
  • Patent number: 9502569
    Abstract: A method for forming a FinFET transistor structure includes providing a substrate with a buried oxide layer and a layer of first semiconductor material. One or more fin structures are formed on the first layer of semiconductor material using a hard mask layer. Sidewall spacers are formed on sidewalls of the fin structures and the hard mask layer. An angled oxygen ion implantation is carried out using the hard mask and side walls as the mask. Next, an annealing process is performed to form oxide diffusion regions. Then, the oxide diffusion regions are removed, and the exposed first semiconductor material layer is etched to expose portions of the buried oxide layer. The resulting fin structure has recessed regions formed on the sidewalls, and the fin structure has a bottom portion below the recessed regions that is wider than a top portion.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: November 22, 2016
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Meng Zhao
  • Patent number: 9490359
    Abstract: A semiconductor device that includes the following is manufactured: an n? base layer; a p-type base layer formed on the surface of the n? base layer; an n+ source layer formed in the inner area of the p-type base layer; a gate electrode formed so as to face a channel region across a gate insulating film; a plurality of p-type columnar regions that are formed in the n? base layer so as to continue from the p-type base layer and that are arranged at a first pitch; and a plurality of p+ collector layers that are selectively formed on the rear surface of the n? base layer and that are arranged at a second pitch larger than the first pitch.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: November 8, 2016
    Assignee: ROHM CO., LTD.
    Inventor: Toshio Nakajima
  • Patent number: 9472568
    Abstract: A semiconductor device is provided as follows. A peripheral circuit structure is disposed on a first substrate. A cell array structure is disposed on the peripheral circuit structure. A second substrate is interposed between the peripheral circuit structure and the cell array structure. The cell array structure includes a stacked structure, a through hole and a vertical semiconductor pattern. The stacked structure includes gate electrodes stacked on the second substrate. The through hole penetrates the stacked structure and the second substrate to expose the peripheral circuit structure. The vertical semiconductor pattern is disposed on the peripheral circuit structure, filling the through hole.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: October 18, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoocheol Shin, Jaegoo Lee, Young-Jin Kwon, Jintaek Park
  • Patent number: 9437732
    Abstract: A semiconductor device includes a fin-shaped semiconductor layer on a semiconductor substrate and extends in a first direction with a first insulating film around the fin-shaped semiconductor layer. A pillar-shaped semiconductor layer resides on the fin-shaped semiconductor layer. A width of the bottom of the pillar-shaped semiconductor layer, perpendicular to the first direction is equal to a width of the top of the fin-shaped semiconductor layer perpendicular to the first direction. A gate insulating film is around the pillar-shaped semiconductor layer and a metal gate electrode is around the gate insulating film. A metal gate line extends in a second direction perpendicular to the first direction of the fin-shaped semiconductor layer and is connected to the metal gate electrode.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: September 6, 2016
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9406768
    Abstract: A semiconductor device includes a fin-shaped silicon layer and a pillar-shaped silicon layer on the fin-shaped silicon layer, where a width of a bottom part of the pillar-shaped silicon layer is equal to a width of a top part of the fin-shaped silicon layer. A gate insulating film and a metal gate electrode are around the pillar-shaped silicon layer and a metal gate line extends in a direction perpendicular to the fin-shaped silicon layer and is connected to the metal gate electrode. A nitride film is on an entire top surface of the metal gate electrode and the metal gate line, except for the bottom of a contact.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: August 2, 2016
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9397044
    Abstract: A semiconductor device includes an active region tilted at an angle with respect to a buried bit line. The buried bit line includes a metal silicide pattern and a metal pattern. The metal silicide pattern has a plurality of metal silicide films each disposed at a lower portion of the active region and corresponding to a bit line contact region. The metal pattern has a plurality of metal films. The metal silicide films and the metal films are alternately arranged and electrically coupled to each other.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: July 19, 2016
    Assignee: SK HYNIX INC.
    Inventor: Sang Min Won
  • Patent number: 9373715
    Abstract: A semiconductor device may include a memory array including vertical memory cells connected to a digit line, word lines, and a body connection line. A row or column of the memory array may include one or more pillars connected to the body connection line. A voltage may be applied to the body connection line through at least one pillar connected to the body connection line. Application of the voltage to the body connection line may reduce floating body effects. Methods of forming a connection between at least one pillar and a voltage supply are disclosed. Semiconductor devices including such connections are also disclosed.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: June 21, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Wolfgang Mueller, Sanh D. Tang, Sourabh Dhir, Srinivas Pulugurtha
  • Patent number: 9246001
    Abstract: A semiconductor device includes a fin-shaped semiconductor layer on a semiconductor substrate and extends in a first direction with a first insulating film around the fin-shaped semiconductor layer. A pillar-shaped semiconductor layer resides on the fin-shaped semiconductor layer. A width of the pillar-shaped semiconductor layer, perpendicular to the first direction is equal to a width of the fin-shaped semiconductor layer perpendicular to the first direction. A gate insulating film is around the pillar-shaped semiconductor layer and a metal gate electrode is around the gate insulating film. A metal gate line extends in a second direction perpendicular to the first direction of the fin-shaped semiconductor layer and is connected to the metal gate electrode.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: January 26, 2016
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9040989
    Abstract: One embodiment of the present invention is to achieve high mobility in a device using an oxide semiconductor and provide a highly reliable display device. An oxide semiconductor layer including a crystal region in which c-axis is aligned in a direction substantially perpendicular to a surface is formed and an oxide insulating layer is formed over and in contact with the oxide semiconductor layer. Oxygen is supplied to the oxide semiconductor layer by third heat treatment. A nitride insulating layer containing hydrogen is formed over the oxide insulating layer and fourth heat treatment is performed, so that hydrogen is supplied at least to an interface between the oxide semiconductor layer and the oxide insulating layer.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: May 26, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9040346
    Abstract: In one embodiment, a semiconductor package includes a semiconductor chip having a first contact region on a first major surface and a second contact region on an opposite second major surface. The semiconductor chip is configured to regulate flow of a current from the first contact region to the second contact region. An encapsulant is disposed at the semiconductor chip. A first contact plug is disposed within the encapsulant and coupled to the first contact region. A second side conductive layer is disposed under the second major surface and coupled to the second contact region. A through via is disposed within the encapsulant and coupled to the second side conductive layer. The first contact plug and the through via form terminals above the first major surface for contacting the semiconductor package.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: May 26, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ivan Nikitin, Edward Fuergut
  • Patent number: 9029209
    Abstract: A method of manufacturing a thin film transistor substrate (1) includes at least the steps of: forming a gate electrode (15) on an insulating substrate (10) by using a first photomask; forming a channel protective film (21) on an oxide semiconductor layer (13) so as to cover a channel region (C) by using a second photomask; forming a source electrode (19) on the oxide semiconductor layer (13) by using a third photomask; and forming a planarizing film (18) on an interlayer insulating film (17) by using a fourth photomask.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: May 12, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Mitsunobu Miyamoto
  • Patent number: 9024330
    Abstract: A method of manufacturing a semiconductor device includes forming an ohmic electrode in a first area on one of main surfaces of a silicon carbide layer, siliciding the ohmic electrode, and forming a Schottky electrode in a second area on the one of the main surfaces of the silicon carbide layer with self alignment. The second area is exposed where the ohmic electrode is not formed.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: May 5, 2015
    Assignees: Toyota Jidosha Kabushiki Kaisha, Denso Corporation
    Inventors: Yukihiko Watanabe, Sachiko Aoi, Masahiro Sugimoto, Akitaka Soeno, Shinichiro Miyahara
  • Patent number: 9018063
    Abstract: A method includes performing an epitaxy to grow a semiconductor layer, which includes a top portion over a semiconductor region. The semiconductor region is between two insulation regions that are in a substrate. The method further includes recessing the insulation regions to expose portions of sidewalls of the semiconductor region, and etching a portion of the semiconductor region, wherein the etched portion of the semiconductor region is under and contacting a bottom surface of the semiconductor layer, wherein the semiconductor layer is spaced apart from an underlying region by an air gap. A gate dielectric and a gate electrode are formed over the semiconductor layer.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: April 28, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Georgios Vellianitis, Mark van Dal, Blandine Duriez
  • Patent number: 9018109
    Abstract: A thin film transistor in which deterioration at initial operation is not likely to be caused and a manufacturing method thereof. A transistor which includes a gate insulating layer at least whose uppermost surface is a silicon nitride layer, a semiconductor layer over the gate insulating layer, and a buffer layer over the semiconductor layer and in which the concentration of nitrogen in the vicinity of an interface between the semiconductor layer and the gate insulating layer, which is in the semiconductor layer is lower than that of the buffer layer and other parts of the semiconductor layer. Such a thin film transistor can be manufactured by exposing the gate insulating layer to an air atmosphere and performing plasma treatment on the gate insulating layer before the semiconductor layer is formed.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: April 28, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Erika Kato, Kunihiko Suzuki
  • Patent number: 9012974
    Abstract: A vertical memory device includes a channel, a ground selection line (GSL), word lines, a string selection line (SSL), and a contact. The channel includes a vertical portion and a horizontal portion. The vertical portion extends in a first direction substantially perpendicular to a top surface of a substrate, and the horizontal portion is connected to the vertical portion and parallel to the top surface of the substrate. The GSL, the word lines and the SSL are formed on a sidewall of the vertical portion of the channel sequentially in the first direction, and are spaced apart from each other. The contact is on the substrate and electrically connected to the horizontal portion of the channel.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: April 21, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soo-Doo Chae, Ki-Hyun Hwang, Han-Mei Choi, Dong-Chul Yoo
  • Patent number: 9006821
    Abstract: An electronic device can include a semiconductor layer overlying a substrate and having a primary surface and a thickness, wherein a trench extends through at least approximately 50% of the thickness of semiconductor layer to a depth. The electronic device can further include a conductive structure within the trench, wherein the conductive structure extends at least approximately 50% of the depth of the trench. The electronic device can still further include a vertically-oriented doped region within the semiconductor layer adjacent to and electrically insulated from the conductive structure; and an insulating layer disposed between the vertically-oriented doped region and the conductive structure. A process of forming an electronic device can include patterning a semiconductor layer to define a trench extending through at least approximately 50% of the thickness of the semiconductor layer and forming a vertically-oriented doped region after patterning the semiconductor layer to define the trench.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: April 14, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Prasad Venkatraman, Gordon M. Grivna, Gary H. Loechelt
  • Patent number: 9006819
    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type which is formed on a first main surface of the semiconductor substrate, a second well region of a second conductivity type which is formed to surround a cell region of the drift layer, and a source pad for electrically connecting the second well regions and a source region of the cell region through a first well contact hole provided to penetrate a gate insulating film on the second well region, a second well contact hole provided to penetrate a field insulating film on the second well region and a source contact hole.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: April 14, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shiro Hino, Naruhisa Miura, Shuhei Nakata, Kenichi Ohtsuka, Shoyu Watanabe, Akihiko Furukawa, Yukiyasu Nakao, Masayuki Imaizumi
  • Patent number: 8999789
    Abstract: A super-junction trench MOSFET with a short termination area is disclosed, wherein the short termination area comprising a charge balance region and a channel stop region formed near a top surface of an epitaxial layer with a trenched termination contact penetrating therethrough.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: April 7, 2015
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8993397
    Abstract: A method of forming a memory device. The method provides a semiconductor substrate having a surface region. A first dielectric layer is formed overlying the surface region of the semiconductor substrate. A bottom wiring structure is formed overlying the first dielectric layer and a second dielectric material is formed overlying the top wiring structure. A bottom metal barrier material is formed to provide a metal-to-metal contact with the bottom wiring structure. The method forms a pillar structure by patterning and etching a material stack including the bottom metal barrier material, a contact material, a switching material, a conductive material, and a top barrier material. The pillar structure maintains a metal-to-metal contact with the bottom wiring structure regardless of the alignment of the pillar structure with the bottom wiring structure during etching. A top wiring structure is formed overlying the pillar structure at an angle to the bottom wiring structure.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: March 31, 2015
    Assignee: Crossbar, Inc.
    Inventor: Scott Brad Herner
  • Patent number: 8980712
    Abstract: A non-volatile memory device having a string of a plurality of memory cells that are serially coupled, wherein the string of memory cells includes a plurality of second channels of a pillar type, a first channel coupling lower end portions of the plurality of the second channels with each other, and a plurality of control gate electrodes surrounding the plurality of the second channels.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: March 17, 2015
    Assignee: SK Hynix Inc.
    Inventor: Han-Soo Joo
  • Patent number: 8975138
    Abstract: A method including patterning a thickness dimension of an interconnect material into a thickness dimension for a wiring line with one or more vias extending from the wiring line and introducing a dielectric material on the interconnect material. A method including depositing and patterning an interconnect material into a wiring line and one or more vias; and introducing a dielectric material on the interconnect material such that the one or more vias are exposed through the dielectric material. An apparatus including a first interconnect layer in a first plane and a second interconnect in a second plane on a substrate; and a dielectric layer separating the first and second interconnect layers, wherein the first interconnect layer comprises a monolith including a wiring line and at least one via, the at least one via extending from the wiring line to a wiring line of the second interconnect layer.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: March 10, 2015
    Assignee: Intel Corporation
    Inventors: Manish Chandhok, Hui Jae Yoo, Yan A. Borodovsky, Florian Gstrein, David N. Shykind, Kevin L. Lin
  • Patent number: 8956940
    Abstract: An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. Source and body regions inside the active region are at source potential and source and body regions outside the isolation trench are at drain potential. The device can be made using a three-mask or four-mask process.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: February 17, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Sik Lui, Anup Bhalla
  • Patent number: 8946812
    Abstract: To provide a miniaturized semiconductor device with stable electric characteristics in which a short-channel effect is suppressed. Further, to provide a manufacturing method of the semiconductor device. The semiconductor device (transistor) including a trench formed in an oxide insulating layer, an oxide semiconductor film formed along the trench, a source electrode and a drain electrode which are in contact with the oxide semiconductor film, a gate insulating layer over the oxide semiconductor film, a gate electrode over the gate insulating layer is provided. The lower corner portions of the trench are curved, and the side portions of the trench have side surfaces substantially perpendicular to the top surface of the oxide insulating layer. Further, the width between the upper ends of the trench is greater than or equal to 1 time and less than or equal to 1.5 times the width between the side surfaces of the trench.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: February 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihiro Ishizuka, Shinya Sasagawa
  • Patent number: 8940606
    Abstract: The present invention provides a trench type power transistor device including a substrate, an epitaxial layer, a doped diffusion region, a doped source region, and a gate structure. The substrate, the doped diffusion region, and the doped source region have a first conductivity type, and the substrate has an active region and a termination region. The epitaxial layer is disposed on the substrate, and has a second conductivity type. The epitaxial layer has a through hole disposed in the active region. The doped diffusion region is disposed in the epitaxial layer at a side of the through hole, and is in contact with the substrate. The doped source region is disposed in the epitaxial layer disposed right on the doped diffusion region, and the gate structure is disposed in the through hole between the doped diffusion region and the doped source region.
    Type: Grant
    Filed: July 8, 2012
    Date of Patent: January 27, 2015
    Assignee: Anpec Electronics Corporation
    Inventors: Yung-Fa Lin, Shou-Yi Hsu, Meng-Wei Wu, Main-Gwo Chen, Chia-Hao Chang, Chia-Wei Chen
  • Patent number: 8941186
    Abstract: A semiconductor device includes: a first vertical type transistor having a first lower diffusion layer, a first upper diffusion layer, and a gate electrode; a second vertical type transistor having a second lower diffusion layer, a second upper diffusion layer, and a second gate electrode; a gate wiring connected to the first and second gate electrodes; a first wiring connected to the first lower diffusion layer and second upper diffusion layer; and a second wiring connected to the first upper diffusion layer and second lower diffusion layer.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: January 27, 2015
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Hiroyuki Fujimoto
  • Patent number: RE45449
    Abstract: A power semiconductor element having a lightly doped drift and buffer layer is disclosed. One embodiment has, underneath and between deep well regions of a first conductivity type, a lightly doped drift and buffer layer of a second conductivity type. The drift and buffer layer has a minimum vertical extension between a drain contact layer on the adjacent surface of a semiconductor substrate and the bottom of the deepest well region which is at least equal to a minimum lateral distance between the deep well regions. The vertical extension can also be determined such that a total amount of dopant per unit area in the drift and buffer layer is larger than a breakdown charge amount at breakdown voltage.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: April 7, 2015
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Franz Hirler, Armin Willmeroth