Having Vertical Bulk Current Component Or Current Vertically Following Trench Gate (e.g., Vertical Power Dmos Transistor) (epo) Patents (Class 257/E29.257)
  • Patent number: 10132696
    Abstract: A semiconductor die includes a discrete semiconductor device and at least one diode. The temperature of the discrete semiconductor device is determined by measuring a first forward voltage drop of the at least one diode under a first test condition, measuring a second forward voltage drop of the at least one diode under a second test condition and estimating the temperature of the discrete semiconductor device based on the difference between the first and second forward voltage drop measurements.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: November 20, 2018
    Assignee: Infineon Technologies AG
    Inventors: Andreas Kiep, Holger Ruething, Frank Wolter
  • Patent number: 9666569
    Abstract: Provided is switch circuit including first and second transistors, a source pad connected to a second node of the second transistor through a first signal path and connected to a gate node of the first transistor through a second signal path, a gate pad connected to a gate node of the second transistor through a third signal path; and a drain pad connected to a first node of the first transistor through a fourth signal path, wherein a second node of the first transistor and a first node of the second transistor are connected to each other through a fifth signal path, and the gate node of the first transistor and the second node of the second transistor are connected to each other through a sixth signal path separated from the first and second signal paths.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: May 30, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventor: Woojin Chang
  • Patent number: 9553084
    Abstract: According to the present invention, a switching element includes a substrate, a first gate pad formed on the substrate, a second gate pad formed on the substrate, a first resistor portion formed on the substrate, the first resistor portion connecting the first gate pad and the second gate pad to each other, and a cell region formed on the substrate and connected to the first gate pad. Thus, measurement of the gate resistance value and selection from gate resistances of the switching element can be performed after the completion of the gate-resistor-incorporating-type switching element.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: January 24, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shigeru Hasegawa, Kazuhiro Morishita, Takeshi Kitani
  • Patent number: 9530766
    Abstract: A transistor (2) is provided on a semiconductor substrate (8). A temperature detection diode (4) for monitoring temperature of an upper surface of the semiconductor substrate (8) is provided on the semiconductor substrate (8). An external electrode (7) is connected in common to an emitter (E) of the transistor (2) and a cathode (K) of the temperature detection diode (4). Therefore, an external electrode for the cathode (K) of the temperature detection diode (4) can be removed, and thus the device can be reduced in size and improved in terms of ease of assembly.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: December 27, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Mikio Ishihara, Kazuaki Hiyama, Tatsuya Kawase, Tsuyoshi Osaga
  • Patent number: 9041063
    Abstract: High electron mobility transistors (HEMTs) and methods of manufacturing the same. A HEMT may include a source electrode, a gate electrode, a drain electrode, a channel formation layer including at least a 2-dimensional electron gas (2DEG) channel, a channel supplying layer for forming the 2DEG channel in the channel formation layer, a portion of the channel supplying layer including a first oxygen treated region. The channel supplying layer may include a second oxygen treated region that extends from the first oxygen treated region towards the drain electrode, and the depth and concentration of oxygen of the second oxygen treated region may be less than those of the first oxygen treated region.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: May 26, 2015
    Assignee: SAMSUNG ELECTRONCS CO., LTD.
    Inventor: In-jun Hwang
  • Patent number: 9041085
    Abstract: A semiconductor device may include, but is not limited to, a semiconductor substrate having a first gate groove; a first fin structure underneath the first gate groove; a first diffusion region in the semiconductor substrate, the first diffusion region covering an upper portion of a first side of the first gate groove; and a second diffusion region in the semiconductor substrate. The second diffusion region covers a second side of the first gate groove. The second diffusion region has a bottom which is deeper than a top of the first fin structure.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: May 26, 2015
    Assignee: PS4 LUXCO S.A.R.L.
    Inventors: Kiyonori Oyu, Koji Taniguchi, Koji Hamada, Hiroaki Taketani
  • Patent number: 9018699
    Abstract: A SiC semiconductor element includes: a SiC substrate which has a principal surface tilted with respect to a (0001) Si plane; a SiC layer arranged on the principal surface of the substrate; a trench arranged in the SiC layer and having a bottom, a sidewall, and an upper corner region located between the sidewall and the upper surface of the SiC layer; a gate insulating film arranged on at least a part of the sidewall and on at least a part of the upper corner region of the trench and on at least a part of the upper surface of the SiC layer; and a gate electrode arranged on the gate insulating film. The upper corner region has a different surface from the upper surface of the SiC layer and from a surface that defines the sidewall. The gate electrode contacts with both of a first portion of the gate insulating film located on the upper corner region and a second portion of the gate insulating film located on the sidewall.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: April 28, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Tsutomu Kiyosawa, Kazuyuki Sawada, Kunimasa Takahashi, Yuki Tomita
  • Patent number: 9018635
    Abstract: An embodiment of an integrated electronic device formed in a semiconductor body delimited by a lateral surface, which includes: a substrate made of a first semiconductor material; a first epitaxial region made of a second semiconductor material, which overlies the substrate and defines a first surface; a second epitaxial region made of a third semiconductor material, which overlies the first surface and is in contact with the first epitaxial region, the third semiconductor material having a bandgap narrower than the bandgap of the second semiconductor material; an active area, extending within the second epitaxial region and housing at least one elementary electronic component; and an edge structure, arranged between the active area and the lateral surface, and including a dielectric region arranged laterally with respect to the second epitaxial region, which overlies the first surface and is in contact with the first epitaxial region.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: April 28, 2015
    Assignee: STMicroelectronics S.R.L.
    Inventors: Ferruccio Frisina, Angelo Magri', Mario Giuseppe Saggio
  • Patent number: 9012982
    Abstract: A recessed transistor and a method of manufacturing the same are provided. The recessed transistor may include a substrate, an active pin, a gate pattern and source and drain regions. The substrate may include an isolation layer that establishes an active region and a field region of the substrate. The substrate may include a recessed structure having an upper recess formed in the active region and a lower recess in communication with the upper recess. An active pin may be formed in a region between side surfaces of the isolation layer and the lower recess and an interface between the active region and the field region. The gate pattern may include a gate insulation layer formed on an inner surface of the recessed structure and a gate electrode formed on the gate insulation layer in the recessed structure. The source/drain regions may be formed adjacent to the active region and the gate electrode.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: April 21, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Keun-Nam Kim, Makoto Yoshida, Chul Lee, Dong-Gun Park, Woun-Suck Yang
  • Patent number: 9012954
    Abstract: An Adjustable Field Effect Rectifier uses aspects of MOSFET structure together with an adjustment pocket or region to result in a device that functions reliably and efficiently at high voltages without significant negative resistance, while also permitting fast recovery and operation at high frequency without large electromagnetic interference.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: April 21, 2015
    Assignee: STMicroelectronics International B.V.
    Inventors: Alexei Ankoudinov, Vladimir Rodov
  • Patent number: 8993426
    Abstract: The invention provides a semiconductor device with a junction termination extension structure on a mesa and a method of fabricating the same. The device comprises: a type-I semiconductor substrate having a first surface and a second surface; a type-I epitaxial layer disposed on the first surface; at least one depression disposed on the type-I epitaxial layer; a mesa-type junction termination extension structure surrounding the at least one depression wherein the mesa-type junction termination extension structure is of type-II; and at least one semiconductor component formed one the depression.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: March 31, 2015
    Inventor: Chii-Wen Jiang
  • Patent number: 8987812
    Abstract: The invention provides an ultra-low-on-resistance, excellent-reliability semiconductor device that can finely be processed using SiC and a semiconductor device producing method.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Kono, Takashi Shinohe, Makoto Mizukami
  • Patent number: 8969929
    Abstract: A general insulated gate power semiconductor active element with many gate electrodes arranged in parallel has a laminated structure including a barrier metal film and a thick aluminum electrode film formed over the gate electrodes via an interlayer insulating film. When the aluminum electrode film is embedded in between the gate electrodes in parallel, voids may be generated with the electrodes. Such voids allow the etchant to penetrate in wet etching, which may promote the etching up to a part of the electrode film in an active cell region which is to be left. Thus, an insulated gate power semiconductor device is provided to include gate electrodes protruding outward from the inside of the active cell region, and a gate electrode coupling portion for coupling the gate electrodes outside the active cell region. The gate electrode coupling portion is covered with a metal electrode covering the active cell region.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: March 3, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Koichiro Sakanishi, Tsuyoshi Kachi, Koji Fujishima
  • Patent number: 8963242
    Abstract: A power semiconductor device includes first to fifth electrodes, first to sixth semiconductor layers, and several first pillar layers. The first semiconductor layer is formed on the first electrode. The second semiconductor layer is formed on the first semiconductor layer. Several first pillar layers are arranged parallel with the second semiconductor layer. The third and fourth semiconductor layers are formed on the second semiconductor layer. The fourth electrode is formed on the first pillar layer adjacent to the third semiconductor layer. The fifth electrode is formed on the first pillar layer adjacent to the fourth semiconductor layer. The concentration of dopant of the first pillar layer positioning between the first pillar layer under the fourth electrode and the first pillar layer under the fifth electrode is lower than the concentration of dopant of the first pillar layer under the fourth electrode and the first pillar layer under the fifth electrode.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: February 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Wataru Saito
  • Patent number: 8957473
    Abstract: MOS-gated devices, related methods, and systems for vertical power and RF devices including an insulated trench and a gate electrode. A body region is positioned so that a voltage bias on the gate electrode will cause an inversion layer in the body region. Permanent electrostatic charges are included in said insulation material. A conductive shield layer is positioned above the insulated trench, to reduce parasitic capacitances.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: February 17, 2015
    Assignee: MaxPower Semiconductor Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng
  • Patent number: 8952430
    Abstract: The present application relates to technology for improving a withstand voltage of a semiconductor device. The semiconductor device includes a termination area that surrounds a cell area. The cell area is provided with a plurality of main trenches. The termination area is provided with one or more termination trenches surrounding the cell area. A termination trench is disposed at an innermost circumference of one or more termination trenches. A body region is disposed on a surface of a drift region. Each main trench reaches the drift region. A gate electrode is provided within each main trench. The termination trench reaches the drift region. Sidewalls and a bottom surface of the termination trench are covered with a insulating layer. A surface of the insulating layer covering the bottom surface of the termination trench is covered with a buried electrode. A gate potential is applied to the buried electrode.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: February 10, 2015
    Assignees: Denso Corporation, Toyota Jidosha Kabushiki Kaisha
    Inventors: Hidefumi Takaya, Hideo Matsuki, Naohiro Suzuki, Tsuyoshi Ishikawa
  • Patent number: 8941174
    Abstract: It is an object to improve the breakdown voltage characteristics of a vertical semiconductor device having an opening and including a channel formed of two-dimensional electron gas in the opening. A GaN-based stacked layer 15 includes n?-type GaN drift layer 4/p-type GaN barrier layer 6/n+-type GaN contact layer 7. An opening 28 extends from a top layer and reaches the n?-type GaN drift layer 4. The semiconductor device includes a regrown layer 27 located so as to cover a wall surface and a bottom portion of the opening, the regrown layer 27 including an electron drift layer 22 and an electron source layer 26, a source electrode S located around the opening, a gate electrode G located on the regrown layer in the opening, and a bottom insulating layer 37 located in the bottom portion of the opening.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: January 27, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Masaya Okada, Makoto Kiyama, Yu Saitoh, Seiji Yaegashi, Mitsunori Yokoyama, Kazutaka Inoue
  • Patent number: 8937350
    Abstract: A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: January 20, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Hitoshi Matsuura, Yoshito Nakazawa, Tsuyoshi Kachi, Yuji Yatsuda
  • Patent number: 8933508
    Abstract: A recessed transistor construction is formed between a first access transistor construction and a second access transistor construction to provide isolation between the access transistor constructions of a memory device. In some embodiments, a gate of the recessed transistor construction is grounded. In an embodiment, the access transistor constructions are recess access transistors. In an embodiment, the memory device is a DRAM. In another embodiment, the memory device is a 4.5F2 DRAM cell.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: January 13, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 8933509
    Abstract: A semiconductor device includes a device isolation structure, a recess channel structure, a first lower gate conductive layer conformal to the recess channel structure and defining a recess, a holding layer over the first lower gate conductive layer to fill the recess defined by the first lower gate conductive layer, and a second lower gate conductive layer over the first lower gate conductive layer and the holding layer. The holding layer is configured to hold a shift of the seam occurring in the recess channel structure.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: January 13, 2015
    Assignee: SK hynix Inc.
    Inventors: Shin Gyu Choi, Seung Chul Oh
  • Patent number: 8921190
    Abstract: A semiconductor structure and method of manufacture and, more particularly, a field effect transistor that has a body contact and method of manufacturing the same is provided. The structure includes a device having a raised source region of a first conductivity type and an active region below the raised source region extending to a body of the device. The active region has a second conductivity type different than the first conductivity type. A contact region is in electric contact with the active region. The method includes forming a raised source region over an active region of a device and forming a contact region of a same conductivity type as the active region, wherein the active region forms a contact body between the contact region and a body of the device.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: December 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Alan B. Botula, Alvin J. Joseph, Stephen E. Luce, John J. Pekarik, Yun Shi
  • Patent number: 8907421
    Abstract: A superjunction structure with unevenly doped P-type pillars (4) and N-type pillars (2a) is disclosed. The N-type pillars (2a) have uneven impurity concentrations in the vertical direction and the P-type pillars (4) have two or more impurity concentrations distributed both in the vertical and lateral directions to ensure that the total quantity of P-type impurities in the P-type pillars (4) close to the substrate (8) is less than that of N-type impurities in the N-type pillars close to the substrate; the total quantity of P-type impurities in the P-type pillars close to the top of the device is greater than that of N-type impurities in the N-type pillars close to the top. A superjunction MOS transistor and manufacturing method of the same are also disclosed. The superjunction structure can improve the capability of sustaining current-surge of a device without affecting or may even reduce the on-resistance of the device.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: December 9, 2014
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventor: Shengan Xiao
  • Patent number: 8901641
    Abstract: A semiconductor device with a super-junction structure is provided, including: a semiconductor substrate having a first conductivity type; an epitaxial layer having the first conductivity type formed over the semiconductor substrate; a first doping region having the first conductive type formed in a portion of the epitaxial layer; a second doping region having a second conductivity type formed in a portion of the of the epitaxial layer; a third doping region having the second conductivity type formed in a portion of the of the epitaxial layer, wherein the doping region partially comprises doped polysilicon materials having the second conductivity type; a gate dielectric layer formed over the epitaxial layer, partially overlying the well region; and a gate electrode formed over a portion of the gate dielectric layer.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: December 2, 2014
    Assignee: Vanguard International Semiconductor Corporation
    Inventor: Tsung-Hsiung Lee
  • Patent number: 8896058
    Abstract: It is an object to improve the breakdown voltage characteristics of a vertical semiconductor device having an opening and including a channel formed of two-dimensional electron gas in the opening. The vertical semiconductor device includes a GaN-based stacked layer 15 having an opening 28 and the GaN-based stacked layer 15 includes n-type GaN-based drift layer 4/p-type GaN-based barrier layer 6/n-type GaN-based contact layer 7. The vertical semiconductor device includes a regrown layer 27 located so as to cover the opening, the regrown layer 27 including an electron drift layer 22 and an electron supply layer 26, a source electrode S, and a gate electrode G located on the regrown layer. The gate electrode G covers a portion having a length corresponding to the thickness of the p-type GaN-based barrier layer and is terminated at a position on the wall surface, the position being away from the bottom portion of the opening.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: November 25, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Masaya Okada, Makoto Kiyama, Yu Saitoh, Seiji Yaegashi, Mitsunori Yokoyama, Kazutaka Inoue
  • Patent number: 8889532
    Abstract: In one embodiment, a vertical insulated-gate field effect transistor includes a shield electrode formed in trench structure within a semiconductor material. A gate electrode is isolated from the semiconductor material using gate insulating layers. Before the shield electrode is formed, spacer layers can be used form shield insulating layers along portions of the trench structure. The shield insulating layers are thicker than the gate insulating layers. In another embodiment, the shield insulating layers have variable thickness.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: November 18, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Peter A. Burke, Gordon M. Grivna, Balaji Padmanabhan, Prasad Venkatraman
  • Patent number: 8890239
    Abstract: In a vertical semiconductor device including a channel in an opening, a semiconductor device whose high-frequency characteristics can be improved and a method for producing the semiconductor device are provided. The semiconductor device includes n-type GaN-based drift layer 4/p-type GaN-based barrier layer 6/n-type GaN-based contact layer 7. An opening 28 extends from a top layer and reaches the n-type GaN-based drift layer. The semiconductor device includes a regrown layer 27 located so as to cover the opening, the regrown layer 27 including an electron drift layer 22 and an electron supply layer 26, a source electrode S, a drain electrode D, and a gate electrode G located on the regrown layer. Assuming that the source electrode serving as one electrode and the drain electrode serving as the other electrode constitute a capacitor, the semiconductor device includes a capacitance-decreasing structure that decreases the capacitance of the capacitor.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: November 18, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Seiji Yaegashi, Makoto Kiyama, Mitsunori Yokoyama, Kazutaka Inoue, Masaya Okada, Yu Saitoh
  • Patent number: 8866217
    Abstract: Described here are transistors and fabrication methods thereof. In one implementation, a transistor includes an n-well region implanted into a surface of a substrate, and a trench in the n-well region. The trench extends from the surface to a first depth. The trench includes a gate of conductive material in the trench, and dielectric material filling a volume of the trench not filled by the conductive material. The transistor also includes a p-type material in a first region extending from a second depth to a third depth, the second depth and the third depth being greater than the first depth. The transistor further includes a source region and a drain region.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: October 21, 2014
    Assignee: Volterra Semiconductor LLC
    Inventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
  • Patent number: 8860144
    Abstract: In general, according to one embodiment, a power semiconductor device includes a first pillar region, a second pillar region, and an epitaxial layer of a first conductivity type on a first semiconductor layer. The first pillar region is composed of a plurality of first pillar layers of a second conductivity type and a plurality of second pillar layers of the first conductivity type alternately arranged along a first direction. The second pillar region is adjacent to the first pillar region along the first direction and includes a third pillar layer of the second conductivity type, a fourth pillar layer of the first conductivity type, and a fifth pillar layer of the second conductivity type in this order along the first direction. A plurality of second base layers of the second conductivity type electrically connected, respectively, onto the third pillar layer and the fifth pillar layer and spaced from each other.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: October 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Ohta, Yasuto Sumi, Kiyoshi Kimura, Junji Suzuki, Hiroyuki Irifune, Wataru Saito, Syotaro Ono
  • Patent number: 8853779
    Abstract: An embodiment of a process for manufacturing a power semiconductor device envisages the steps of: providing a body of semiconductor material having a top surface and having a first conductivity; forming columnar regions having a second type of conductivity within the body of semiconductor material, and surface extensions of the columnar regions above the top surface; and forming doped regions having the second type of conductivity, in the proximity of the top surface and in contact with the columnar regions. The doped regions are formed at least partially within the surface extensions of the columnar regions; the surface extensions and the doped regions have a non-planar surface pattern, in particular with a substantially V-shaped groove.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: October 7, 2014
    Assignee: STMicroelectronics S.R.L.
    Inventors: Alfio Guarnera, Mario Giuseppe Saggio, Ferruccio Frisina
  • Patent number: 8853784
    Abstract: A device having a substrate defined with a device region which includes an ESD protection circuit is disclosed. The ESD protection circuit has first and second transistors. A transistor includes a gate having first and second sides, a first diffusion region in the device region adjacent to the first side of the gate, and a second diffusion region in the device region displaced away from the second side of the gate. The first and second diffusion regions include dopants of a first polarity type. The device includes a first device well which encompasses the device region and second device wells which are disposed within the first device well. A well contact is coupled to the second device wells. The well contact surrounds the gates of the transistors and abuts the first diffusion regions of the transistors.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: October 7, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Da-Wei Lai, Handoko Linewih, Ying-Chang Lin
  • Patent number: 8853776
    Abstract: An electronic circuit includes a transistor device that can be operated in a reverse operation mode and a control circuit. The transistor device includes a source region, a drain region, a body region and a drift region, a source electrode electrically connected to the source region, a pn junction formed between the body region and the drift region, a gate electrode adjacent the body region and dielectrically insulated from the body region, and a depletion control structure adjacent the drift region. The depletion control structure has a control terminal and is configured to generate a depletion region in the drift region dependent on a drive signal received at the control terminal. The control circuit is coupled to the control terminal of the depletion control structure and configured to drive the depletion control structure to generate the depletion region when the transistor device is operated in the reverse operation mode.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: October 7, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Lutz Goergens, Martin Feldtkeller
  • Patent number: 8853783
    Abstract: A device which includes a substrate defined with a device region having an ESD protection circuit is disclosed. The ESD protection circuit has a transistor. The transistor includes a gate having first and second sides. A first diffusion region is disposed adjacent to the first side of the gate and a second diffusion region is disposed in the device region displaced away from the second side of the gate. The first and second diffusion regions include dopants of a first polarity type. A drift isolation region is disposed between the gate and the second diffusion region. A first device well encompasses the device region and a second device well is disposed within the first device well. A drain well having dopants of the first polarity type is disposed under the second diffusion region and within the first device well.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: October 7, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Da-Wei Lai, Ming Li, Jeoung Mo Koo, Purakh Raj Verma
  • Patent number: 8847318
    Abstract: A device which includes a substrate defined with a device region with an ESD protection circuit having at least first and second transistors is disclosed. Each of the transistors includes a gate having first and second sides, a first diffusion region in the device region adjacent to the first side of the gate, a second diffusion region in the device region displaced away from the second side of the gate, and a drift isolation region disposed between the gate and the second diffusion region. A first device well encompasses the device region and a second device well is disposed within the first device well. The device also includes a drift well which encompasses the second diffusion region. Edges of the drift well do not extend below the gate and is away from a channel region. A drain well is disposed under the second diffusion region and within the drift well.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 30, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Da-Wei Lai, Handoko Linewih, Ying-Chang Lin
  • Patent number: 8841722
    Abstract: A semiconductor device includes a semiconductor substrate having a first groove. The first groove has a bottom and first and second side surfaces opposite to each other. A first gate insulator extends alongside the first side surface. A first gate electrode is formed in the first groove and on the first gate insulator. A second gate insulator extends alongside the second side surface. A second gate electrode is formed in the first groove and on the second gate insulator. The second gate electrode is separate from the first gate electrode.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: September 23, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Masayoshi Sammi
  • Patent number: 8836017
    Abstract: A semiconductor device is provided. The semiconductor device includes a plurality of first epitaxial layers, a second epitaxial layer and a gate structure. The plurality of first epitaxial layers is stacked on a substrate and has a first conductivity type. Each first epitaxial layer includes at least one first doping region and at least one second doping region adjacent thereto. The first doping region has a second conductivity and the second doping region has the first conductivity type. The second epitaxial layer is disposed on the plurality of first epitaxial layers, having the first conductivity type. The second epitaxial layer has a trench therein and a third doping region having the second conductivity type is adjacent to a sidewall of the trench. The gate structure is disposed on the second epitaxial layer above the second doping region. A method of fabricating a semiconductor device is also disclosed.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: September 16, 2014
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Tsung-Hsiung Lee, Shang-Hui Tu
  • Patent number: 8836021
    Abstract: A semiconductor device includes an active region, a gate conductor and a source electrode. The active region includes a drain region, a channel region stacked on the drain region, and a source region stacked on the channel region. The active region is formed of a silicon semiconductor layer. The gate conductor is embedded within a trench, which is formed from the source region to the drain region penetrating through the channel region. The source electrode is formed to come in contact with the source region and includes an adhesion layer. The source electrode is formed of a metal layer having a film thickness of 150 ? or smaller. The interface between the source electrode and the source region is silicidized.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: September 16, 2014
    Assignee: Rohm Co., Ltd.
    Inventor: Masaki Nagata
  • Patent number: 8829641
    Abstract: In one general aspect, a method of forming a field effect transistor can include forming a well region in a semiconductor region of a first conductivity type where the well region is of a second conductivity type and has an upper surface and a lower surface. The method can include forming a gate trench extending into the semiconductor region to a depth below a depth of the lower surface of the well region, and forming a stripe trench extending through the well region and into the semiconductor region to a depth below the depth of the gate trench. The method can also include forming a contiguous source region of the first conductivity type in the well region where the source region being in contact with the gate trench and in contact with the stripe trench.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: September 9, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Bruce D. Marchant
  • Patent number: 8829608
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, a fourth semiconductor layer of the second conductivity type, a fifth semiconductor layer of the first conductivity type, a control electrode, a first main electrode, a second main electrode, and a sixth semiconductor layer of the first conductivity type. The second semiconductor layer and the third semiconductor layer are alternately provided on the first semiconductor layer in a direction substantially parallel to a major surface of the first semiconductor layer. The fourth semiconductor layer is provided on the second semiconductor layer and the third semiconductor layer. The fifth semiconductor layer is selectively provided on a surface of the fourth semiconductor layer. The control electrode is provided in a trench via an insulating film.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: September 9, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wataru Saito, Syotaro Ono, Shunji Taniuchi, Miho Watanabe, Hiroaki Yamashita
  • Patent number: 8829600
    Abstract: Provided is a power semiconductor device including a semiconductor substrate, in which a current flows in a thickness direction of the semiconductor substrate. The semiconductor substrate includes a resistance control structure configured so that a resistance to the current becomes higher in a central portion of the semiconductor substrate than a peripheral portion of the semiconductor substrate.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: September 9, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kenji Hatori
  • Patent number: 8829605
    Abstract: A MOSFET includes: a substrate made of silicon carbide and having a first trench and a second trench formed therein, the first trench having an opening at the main surface side, the second trench having an opening at the main surface side and being shallower than the first trench; a gate insulating film; a gate electrode; and a source electrode disposed on and in contact with a wall surface of the second trench. The substrate includes a source region, a body region, and a drift region. The first trench is formed to extend through the source region and the body region and reach the drift region. The second trench is formed to extend through the source region and reach the body region.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: September 9, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takeyoshi Masuda, Keiji Wada, Toru Hiyoshi, Shinji Matsukawa
  • Patent number: 8823096
    Abstract: A device includes a semiconductor region in a semiconductor chip, a gate dielectric layer over the semiconductor region, and a gate electrode over the gate dielectric. A drain region is disposed at a top surface of the semiconductor region and adjacent to the gate electrode. A gate spacer is on a sidewall of the gate electrode. A dielectric layer is disposed over the gate electrode and the gate spacer. A conductive field plate is over the dielectric layer, wherein the conductive field plate has a portion on a drain side of the gate electrode. A deep metal via is disposed in the semiconductor region. A source electrode is underlying the semiconductor region, wherein the source electrode is electrically shorted to the conductive field plate through the deep metal via.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chih Su, Hsueh-Liang Chou, Ruey-Hsin Liu, Chun-Wai Ng
  • Patent number: 8816430
    Abstract: According to one embodiment, a semiconductor device includes a substrate, a gate electrode, source/drain regions, and a gate insulating film. The substrate is made of monocrystalline silicon, an upper surface of the substrate is a (100) plane, and a trench is made in the upper surface. The gate electrode is provided in at least an interior of the trench. The source/drain regions are formed in regions of the substrate having the trench interposed. The gate insulating film is provided between the substrate and the gate electrode. The trench includes a bottom surface made of a (100) plane, a pair of oblique surfaces made of (111) planes contacting the bottom surface, and a pair of side surfaces made of (110) planes contacting the oblique surfaces. The source/drain regions are in contact with the side and oblique surfaces and are apart from a central portion of the bottom surface.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: August 26, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Yanagisawa
  • Patent number: 8809942
    Abstract: According to an embodiment, a trench structure and a second semiconductor layer are provided in a semiconductor device. In the trench structure, a trench is provided in a surface of a device termination portion with a first semiconductor layer of a first conductive type including a device portion and the device termination portion, and an insulator is buried in the trench in such a manner to cover the trench. The second semiconductor layer, which is of a second conductive type, is provided on the surface of the first semiconductor layer, is in contact with at least a side on the device portion of the trench, and has a smaller depth than the trench. The insulator and a top passivation film for the semiconductor device are made of the same material.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: August 19, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shizue Matsuda, Shingo Sato, Wataru Saito
  • Patent number: 8803252
    Abstract: A drift layer forms a first main surface of a silicon carbide layer and has a first conductivity type. A source region is provided to be spaced apart from the drift layer by a body region, forms a second main surface, and has the first conductivity type. A relaxing region is provided within the drift layer and has a distance Ld from the first main surface. The relaxing region has a second conductivity type and has an impurity dose amount Drx. The drift layer has an impurity concentration Nd between the first main surface and the relaxing region. Relation of Drx>LdĀ·Nd is satisfied. Thus, a silicon carbide semiconductor device having a high breakdown voltage is provided.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: August 12, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Takeyoshi Masuda, Toru Hiyoshi
  • Patent number: 8796764
    Abstract: A semiconductor device includes a semiconductor substrate, a trench, a buried insulated source electrode arranged in a bottom portion of the trench, a first gate electrode and a second gate electrode arranged in an upper portion of the trench and spaced apart from one another. A surface gate contact extends into the upper portion of the trench and is in physical and electrical contact with the first gate electrode and second gate electrode.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: August 5, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Blank, Uli Hiller
  • Patent number: 8786046
    Abstract: A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: July 22, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Tomohiro Tamaki, Yoshito Nakazawa, Satoshi Eguchi
  • Patent number: 8785275
    Abstract: Methods for fabricating an electronic device and electronic devices therefrom are provided. A method includes forming one or more masking layers on a semiconducting surface of a substrate and forming a plurality of dielectric isolation features and a plurality of fin-type projections using the masking layer. The method also includes processing the masking layers and the plurality of fin-type projections to provide an inverted T-shaped cross-section for the plurality of fin-type projections that includes a distal extension portion and a proximal base portion. The method further includes forming a plurality of bottom gate layers on the distal extension portion and forming a plurality of control gate layers on the plurality of dielectric isolation features and the plurality of bottom gate layers.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: July 22, 2014
    Assignee: Spansion LLC
    Inventors: Chun Chen, Shenqing Fang
  • Patent number: 8779509
    Abstract: A semiconductor device includes a doped layer which contains a first dopant of a first conductivity type. In the doped layer, a counter-doped zone is formed in an edge area that surrounds an element area of the semiconductor device. The counter-doped zone contains at least the first dopant and a second dopant of a second conductivity type, which is the opposite of the first conductivity type. A concentration of the second dopant is at least 20% and at most 100% of a concentration of the first dopant. The dopants in the counter-doped zone decrease charge carrier mobility and minority carrier lifetime such that the dynamic robustness of the semiconductor device is increased.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: July 15, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans-Joachim Schulze, Anton Mauder, Franz Hirler
  • Patent number: 8779504
    Abstract: A super-junction semiconductor substrate is configured in such a manner that an n-type semiconductor layer of a parallel pn structure is opposed to a boundary region between an active area and a peripheral breakdown-resistant structure area. A high-concentration region is formed at the center between p-type semiconductor layers that are located on both sides of the above n-type semiconductor layer. A region where a source electrode is in contact with a channel layer is formed over the n-type semiconductor layer. A portion where the high-concentration region is in contact with the channel layer functions as a diode. The breakdown voltage of the diode is set lower than that of the device.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: July 15, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Noriyuki Iwamuro
  • Patent number: RE45449
    Abstract: A power semiconductor element having a lightly doped drift and buffer layer is disclosed. One embodiment has, underneath and between deep well regions of a first conductivity type, a lightly doped drift and buffer layer of a second conductivity type. The drift and buffer layer has a minimum vertical extension between a drain contact layer on the adjacent surface of a semiconductor substrate and the bottom of the deepest well region which is at least equal to a minimum lateral distance between the deep well regions. The vertical extension can also be determined such that a total amount of dopant per unit area in the drift and buffer layer is larger than a breakdown charge amount at breakdown voltage.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: April 7, 2015
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Franz Hirler, Armin Willmeroth