A METHOD FOR FORMING A MULTI-LAYER SHALLOW TRENCH ISOLATION STRUCTURE IN A SEMICONDUCTOR DEVICE
The disclosure describes a multi-layer shallow trench isolation structure in a semiconductor device. The shallow trench isolation structure may include a first void-free, doped oxide layer in the shallow trench, and a second void-free layer above the first doped oxide layer. The first layer may be formed by vapor deposition of precursors of a source of silicon, a source of oxygen and sources of doping materials and making the layer void-free by reflowing the initial layer by an annealing process. The second layer may be formed by vapor deposition of precursors of silicon and doping materials and making the layer void-free by reflowing the initial layer by an annealing process. Alternatively, the second layer may be a silicon oxide layer that may be formed by an atomic layer deposition method. The processing conditions for forming the two layers are different.
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The present disclosure relates generally to the field of shallow trench isolation structures in semiconductor substrates of integrated circuits, and, more specifically, to the field of multilayer shallow trench isolation structures in semiconductor substrates.
In very large scale integrated circuits (VLSIs), huge numbers of discrete electronic devices are present on a semiconductor substrate. Since all electronic devices are becoming miniaturized, the space between the devices is getting narrower. Due to this, isolation of the devices from each other is becoming increasingly difficult. It is common to etch shallow trenches in silicon substrates to achieve isolation of discrete electronic devices in VLSIs
However, the shallow trench isolation structures used in the art have some disadvantages. For example, voids are formed in the dielectric materials used to fill the shallow trench. Such voids formed in the dielectric materials adversely affect isolation of the devices which affects the overall structural integrity of the integrated circuits.
Accordingly, it would be desirable to provide an improved process for preparation of shallow trench isolation structures. In particular, the method should overcome the problem of void formation and provide effective device isolation.
The steps shown in
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may have been arbitrarily increased or reduced for clarity of discussion. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments discussed.
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. These are, of course, merely examples and are not intended to limit the full scope of the invention.
A schematic cross-section of a silicon substrate 102 is shown in
As shown in
Another step in the embodiment involves formation of an oxide layer 302 on the floor and sidewalls of the shallow trench, as shown in
Another step in this embodiment involves deposition of a silicon nitride layer 402 above the oxide layer 302 as shown in
During the process of deposition of the first doped oxide layer in the shallow trench, seams or voids may be created in the first doped oxide layer. Any voids or seams formed during the initial deposition of the first doped oxide layer may be removed by a thermal annealing (re-flow) process as shown in
During the process of deposition of the second doped oxide layer in the shallow trench, a seam or void can be created in the second doped oxide layer. Any voids or seams formed during the initial deposition of the second doped oxide layer may be removed by a thermal annealing (re-flow) process as shown in
In a preferred embodiment, the thickness ratio between the first void-free doped oxide layer 602 and the second void-free doped oxide layer 902 may vary in a range between about 0.1 and 1.
Another step in this embodiment involves removal of the cap oxide film and/or the doped oxide layers above the pad silicon nitride layer 106 by using CMP, leveling the shallow trench 202 with the surrounding silicon substrate, as shown in
A schematic cross-section of a silicon substrate 102 is shown in
As shown in
Another step in the method of the embodiment involves formation of an oxide layer 302 the floor and sidewalls of the shallow trench, as shown in
Seams or voids may be created during the process of deposition of the first doped oxide layer 502 in the shallow trench. Any voids or seams formed during the initial deposition of the first doped oxide layer 502 may be removed by a thermal annealing (re-flow) process as shown in
In an embodiment, the thickness ratio between the doped oxide layer 602 and the silicon oxide layer 1302 may be in a range between about 0.1 and 1.
Features of several embodiments have been outline above. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages as the embodiments introduced above. In one example, the doped oxide filled in the shallow trench includes more than two doped oxide layers each with different doping concentrations. In furtherance of the example, the doping concentration and other deposition conditions may continuously shift such that a graded doped oxide layer is filled in the shallow trench. In another example, the liner layer including the oxide layer 302 and silicon nitride layer 402 lining the shallow trench may alternatively include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and/or various combinations thereof. In other examples, additional processing steps, such as annealing and CMP may present in various embodiments of the present disclosure to optimize the gap filling of the shallow trench. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations to the disclosed embodiments without departing from the spirit and scope of the present disclosure.
Claims
1. A multi-layer shallow trench isolation structure in a semiconductor device, the structure comprising:
- a shallow trench etched in a silicon substrate of a semiconductor device;
- a dielectric liner layer deposited on a floor and walls of the shallow trench;
- a first doped oxide layer in the shallow trench, the first layer formed by a first processing condition; and
- a second doped oxide layer above the first doped oxide layer, the second layer formed at a second processing condition, different from the first processing condition.
2. The shallow trench isolation structure of claim 1, wherein:
- the dielectric liner layer comprises a silicon oxide layer and a Nitrogen containing layer
3. The shallow trench isolation structure of claim 1, wherein a thickness ratio between the first doped oxide layer and the second layer is in the range of approximately 0.1 to 1.
4. The shallow trench isolation structure of claim 1, wherein the second layer is a doped oxide layer, formed by vapor deposition of precursors of silicon and doping materials.
5. The shallow trench isolation structure of claim 1, wherein:
- the doping materials in the first doped oxide layer comprise boron and phosphorus;
- the first processing condition comprises boron concentration in the range of approximately 4-8 wt %, phosphorus concentration in the range of approximately 3-6 wt %
6. The shallow trench isolation structure of claim 1, wherein:
- the doping materials in the second doped oxide layer are boron and phosphorus;
- the second processing condition comprises boron concentration in the range of approximately 4-6 wt %, phosphorus concentration in the range of approximately 4-6 wt %
7. The shallow trench isolation structure of claim 1, further comprising a cap oxide layer deposited above the second doped oxide layer, keeping a thickness ratio between the second doped oxide layer and the cap oxide layer in the range of approximately 1 to 6.
8. The shallow trench isolation structure of claim 1, wherein material above the silicon substrate, after deposition of each of the first doped oxide layer, the second doped oxide layer, and the cap oxide layer, is removed by chemical mechanical polishing for leveling the shallow trench with the surrounding silicon substrate.
9. The shallow trench isolation of claim 1, further comprising a third oxide layer interposed between the first doped oxide layer and the second doped oxide layer, the third layer formed at a third processing condition, different from the first and second processing conditions.
10. (canceled)
11. The method of claim 12, wherein:
- the dielectric liner layer comprises a silicon oxide layer and a Nitrogen containing layer;
12. A method for forming a multi-layer shallow trench isolation structure in a semiconductor device, the method comprising the steps of:
- etching a shallow trench in a silicon substrate of a semiconductor device;
- forming a dielectric liner layer on a floor and walls of the shallow trench;
- forming a first doped oxide layer in the shallow trench, the first layer formed by vapor deposition of precursors including a source of silicon, a source of oxygen. and sources of doping materials at a first processing condition; and
- forming a second doped oxide layer above and in direct contact with the first doped oxide layer by vapor deposition using precursors of silicon and doping materials, at a second processing condition. different from the first processing condition; wherein the doping materials in the first doped oxide layer comprise boron and phosphorus; and the first processing condition comprises boron concentration in the range of approximately 4-8 wt %, phosphorus concentration in the range of approximately 3-6 wt %.
13. The method of claim 12, wherein:
- the doping materials in the second doped oxide layer are boron and phosphorus;
- the second processing condition comprises boron concentration in the range of approximately 4-6 wt %, phosphorus concentration in the range of approximately 4-6 wt %
14. The method of claim 12, further comprising depositing a cap oxide layer above the second doped oxide layer, keeping a thickness ratio between the second doped oxide layer and the cap oxide layer in the range of approximately 1 to 6.
15. The method of claim 12, wherein a thickness ratio between the first doped oxide layer and the second doped oxide layer is in the range of approximately 0.1 to 1.
16. (canceled)
17. The method of claim 18, wherein: the dielectric liner layer comprises a silicon oxide layer and a Nitrogen containing layer;
18. A method for forming a multi-layer shallow trench isolation structure in a semiconductor device, the method comprising the steps of:
- etching a shallow trench in a silicon substrate of a semiconductor device;
- forming a dielectric liner layer on a floor and walls of the shallow trench;
- forming a doped oxide layer above the dielectric liner layer by vapor deposition using precursors of silicon and doping materials; and
- forming a silicon oxide layer above the doped oxide layer by atomic layer deposition; wherein: a thickness ratio of the doped oxide layer to the silicon oxide layer is in the range of approximately 0.1 to 1; the doping materials in the first doped oxide layer comprise boron and phosphorus; and doping components of the doped oxide layer comprise boron concentration in the range of approximately 4-8 wt %, phosphorus concentration in the range of approximately 3-6 wt %.
19. (canceled)
20. The method of claim 18, further comprising depositing a cap oxide layer above the silicon oxide layer, keeping a thickness ratio between the silicon oxide layer and the cap oxide layer in the range of approximately 1 to 6.
Type: Application
Filed: Apr 29, 2008
Publication Date: Oct 29, 2009
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Hsin-Chu)
Inventors: Shu-Tine Yang (Jhubei City), Chen-Hua Yu (Hsin-Chu), Chu-Yun Fu (Hsinchu City)
Application Number: 12/111,355
International Classification: H01L 29/00 (20060101); H01L 21/76 (20060101);