Substrate fins with different heights
A device includes a number of fins. Some of the fins have greater heights than other fins. This allows the selection of different drive currents and/or transistor areas.
Multi-gate devices such as transistors may be formed on fin structures. The gate channel “width” of such a multi-gate device may depend at least in part on the height of the fin.
Various embodiments of a substrate having fins of different heights are discussed in the following description. One skilled in the relevant art will recognize that the various embodiments may be practiced without one or more of the specific details, or with other replacement and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of various embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials, and configurations are set forth in order to provide a thorough understanding of the invention. Nevertheless, the invention may be practiced without specific details. Furthermore, it is understood that the various embodiments shown in the figures are illustrative example representations and are not necessarily drawn to scale.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention, but do not denote that they are present in every embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments. Various additional layers and/or structures may be included and/or described features may be omitted in other embodiments.
Various operations will be described as multiple discrete operations in turn, in a manner that is most helpful in understanding the invention. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation. Operations described may be performed in a different order, in series or in parallel, than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.
Fins 124 have been formed on the substrate 102. Rather than all fins 124 having the same height, the fins 124 have differing heights above isolation regions 104. Fins 124A through 124C have a smaller height 120 while fins 124D through 124G have a larger height 122. This difference between heights 120 and 122 is selectable by choosing materials and etchants. In an embodiment, the greater height 122 is selected to be between a height roughly equal to the lower height 120 and a height about twice as great as the lower height 120 (i.e. height 120 is between 99% and 50% of height 122). In another embodiment, the greater height 122 may be more than twice the lower height 120. In an embodiment, the lower height 120 may be between 15-20 nanometers, and the greater height 122 30-40 nanometers, although the invention is not limited to fins 124 within those height ranges.
Such an ability to have fins 124 of different height allows multi-gate transistors to be made on the fins 124 with different desired properties. As the drive current of a transistor is dependent on the gate channel “width” of a multi-gate transistor, and the “width” may be made greater by use of a taller fin 124 without increasing the area of the transistor, selectable multi-height fins 124 allow the transistors with the same area to have selected drive currents based on the fin heights. In other embodiments, different areas of transistors may be selected without changing drive currents by selecting the fin heights. Rather than having one selectable parameter, transistor area, with which to affect drive currents, designers may independently select transistor height and area to achieve desired device characteristics.
The formation of the isolation regions 104 also results in pre-fin regions 106 of the substrate 102. These pre-fin regions 106 are between the isolation regions 104.
The thickness of patterned mask layer 126 is selected based on the desired height differential between fin 124D and fins 124E-124G (i.e. height 134 minus height 132) and the etch rate difference between the material of the mask layer 126 and the material of the isolation regions 104. Similarly, the thickness of patterned mask layer 128 is selected based on the desired height differential between fins 124A-124C and fin 124D (i.e. height 132 minus height 130) and the etch rate difference between the material of the mask layer 128 and the material of the isolation regions 104.
Additional mask layers may be used to make yet other differences in the heights of fins 124 on a substrate. More than three different heights may be created. Rather than multiple stacked patterned mask layers 126, 128, there may be a first patterned mask layer with a first thickness covering some pre-fin regions 106, and a second patterned mask layer with a second thickness greater than the first thickness covering different pre-fin regions 106 than those covered by the first patterned mask layer. Alternatively, mask layers with different etch rates in an etchant may be used in place of, or in addition to, different thicknesses. No matter how many different heights are present in the final set of fins 124, the resulting fins 124 may be used in any application calling for such structures.
One application is to make NMOS (n-type metal oxide semiconductor transistors) and PMOS (p-type metal oxide semiconductor transistors) having substantially the same drive current while being closer in area compared to NMOS and PMOS transistors made on fins having equal heights. A PMOS transistor having the same gate channel “width” as an NMOS transistor will typically have a lower drive current. By increasing the fin 124 height 142 of the PMOS transistor compared to the NMOS transistor on the same substrate 102, the PMOS gate “width” can be increased, and the drive current increased, without increasing the area taken up by the PMOS transistor. Thus, the PMOS and NMOS transistors 135 on a substrate 102 may have substantially the same area and substantially the same drive current.
In other embodiments, the PMOS transistor 135 may have substantially the same area as the NMOS transistor 135 and the drive current of the PMOS transistor may be more or less than that of the NMOS transistor by selecting the fin heights of the respective transistor types. Alternatively, both the area and fin height 142 of the PMOS transistor may be selected to each be greater or less than the NMOS transistor based on the desired drive current for some specific circuit requirement and acceptable use of area on the substrate 102.
In yet other embodiments, the drive current of multiple instances of a single transistor type (either N- or P-type) may be varied across a single substrate 102 without changing their area by having different fin 124 heights 142. This may be useful, for example, when transistors 135 of the same area are desired (e.g. when design rules that dictate spacing of transistors are based on transistor area) yet different drive currents are desired. The area and height of the fin 124 may each be separately chosen by the device designer to result in a device such as a transistor having the desired drive current and area.
The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. This description and the claims following include terms, such as left, right, top, bottom, over, under, upper, lower, first, second, etc. that are used for descriptive purposes only and are not to be construed as limiting. For example, terms designating relative vertical position refer to a situation where a device side (or active surface) of a substrate or integrated circuit is the “top” surface of that substrate; the substrate may actually be in any orientation so that a “top” side of a substrate may be lower than the “bottom” side in a standard terrestrial frame of reference and still fall within the meaning of the term “top.” The term “on” as used herein (including in the claims) does not indicate that a first layer “on” a second layer is directly on and in immediate contact with the second layer unless such is specifically stated; there may be a third layer or other structure between the first layer and the second layer on the first layer. The embodiments of a device or article described herein can be manufactured, used, or shipped in a number of positions and orientations. Persons skilled in the relevant art can appreciate that many modifications and variations are possible in light of the above teaching. Persons skilled in the art will recognize various equivalent combinations and substitutions for various components shown in the Figures. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.
Claims
1-12. (canceled)
13. A semiconductor device, comprising:
- a substrate;
- a first multi-gate transistor on a first portion of the substrate, the first multi-gate transistor comprising a first fin, the first fin having a first height above a first isolation region; and
- a second multi-gate transistor on a second portion of the substrate, the second multi-gate transistor comprising a second fin, the second fin having a second height above a second isolation region, the second height being greater than the first height.
14. The device of claim 13, wherein the first multi-gate transistor is an N-type transistor and the second multi-gate transistor is a P-type transistor.
15. The device of claim 14, further comprising a memory cell, wherein both the first and second multi-gate transistors are transistors of the memory cell.
16. The device of claim 14, further comprising a ring oscillator, wherein both the first and second multi-gate transistors are transistors of the ring oscillator.
17. The device of claim 14 wherein the second height is greater than the first height in an amount great enough that the drive current of the first transistor is within 10% of the drive current of the second transistor.
18. The device of claim 17 wherein first multi-gate transistor has a first area, the second multi-gate transistor has a second area, and the first area is within about 15% of the second area.
19. The device of claim 13 wherein the second height is at least 25% greater than the first height.
20. The device of claim 13, further comprising a third multi-gate transistor on a third portion of the substrate, the third multi-gate transistor comprising a third fin, the third fin having a third height above a third isolation region, the third height being greater than the second height.
Type: Application
Filed: Jun 30, 2008
Publication Date: Dec 31, 2009
Inventors: Willy Rachmady (Beaverton, OR), Justin S. Sandford (Tigard, OR), Michael K. Harper (Hillsboro, OR)
Application Number: 12/215,778
International Classification: H01L 21/762 (20060101); H01L 27/088 (20060101);