With Multiple Gate Structure (epo) Patents (Class 257/E29.264)
  • Patent number: 8987835
    Abstract: A fin structure for a fin field effect transistor (FinFET) device is provided. The device includes a substrate, a first semiconductor material disposed on the substrate, a shallow trench isolation (STI) region disposed over the substrate and formed on opposing sides of the first semiconductor material, and a second semiconductor material forming a first fin and a second fin disposed on the STI region, the first fin spaced apart from the second fin by a width of the first semiconductor material. The fin structure may be used to generate the FinFET device by forming a gate layer formed over the first fin, a top surface of the first semiconductor material disposed between the first and second fins, and the second fin.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Georgios Vellianitis, Mark van Dal, Blandine Duriez, Richard Oxland
  • Patent number: 8975141
    Abstract: A method for fabricating a dual-workfunction FinFET structure includes depositing a first workfunction material in a layer in a plurality of trenches of the FinFET structure, depositing a low-resistance material layer over the first workfunction material layer, and etching the low-resistance material layer and the first workfunction material layer from a portion of the FinFET structure. The method further includes depositing a second workfunction material in a layer in a plurality of trenches of the portion and depositing a stress material layer over the second workfunction material layer.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: March 10, 2015
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Andy C. Wei, Bin Yang, Francis M. Tambwe
  • Patent number: 8952447
    Abstract: A non-linear element (e.g., a diode) with small reverse saturation current is provided. A non-linear element includes a first electrode provided over a substrate, an oxide semiconductor film provided on and in contact with the first electrode, a second electrode provided on and in contact with the oxide semiconductor film, a gate insulating film covering the first electrode, the oxide semiconductor film, and the second electrode, and a third electrode provided in contact with the gate insulating film and adjacent to a side surface of the oxide semiconductor film with the gate insulating film interposed therebetween or a third electrode provided in contact with the gate insulating film and surrounding the second electrode. The third electrode is connected to the first electrode or the second electrode.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: February 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8941189
    Abstract: Various embodiments include fin-shaped field effect transistor (finFET) structures that enhance work function and threshold voltage (Vt) control, along with methods of forming such structures. The finFET structures can include a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET). In some embodiments, the PFET has fins separated by a first distance and the NFET has fins separated by a second distance, where the first distance and the second distance are distinct from one another. In some embodiments, the PFET or the NFET include fins that are separated from one another by non-uniform distances. In some embodiments, the PFET or the NFET include adjacent fins that are separated by distinct distances at their source and drain regions.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: January 27, 2015
    Assignee: International Business Machines Corporation
    Inventors: Murshed M. Chowdhury, Benjamin R. Cipriany, Brian J. Greene, Arvind Kumar
  • Patent number: 8941187
    Abstract: In a three-dimensional transistor configuration, a strain-inducing isolation material is provided, at least in the drain and source areas, thereby inducing a strain, in particular at and in the vicinity of the PN junctions of the three-dimensional transistor. In this case, superior transistor performance may be achieved, while in some illustrative embodiments even the same type of internally stressed isolation material may result in superior transistor performance of P-channel transistors and N-channel transistors.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: January 27, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Tim Baldauf, Andy Wei, Tom Herrmann, Stefan Flachowsky, Ralf Illgen
  • Patent number: 8928086
    Abstract: A fin structure includes an optional doped well, a disposable single crystalline semiconductor material portion, and a top semiconductor portion formed on a substrate. A disposable gate structure straddling the fin structure is formed, and end portions of the fin structure are removed to form end cavities. Doped semiconductor material portions are formed on sides of a stack of the disposable single crystalline semiconductor material portion and a channel region including the top semiconductor portion. The disposable single crystalline semiconductor material portion may be replaced with a dielectric material portion after removal of the disposable gate structure or after formation of the stack. The gate cavity is filled with a gate dielectric and a gate electrode. The channel region is stressed by the doped semiconductor material portions, and is electrically isolated from the substrate by the dielectric material portion.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Henry K. Utomo, Kangguo Cheng, Ramachandra Divakaruni, Dechao Guo, Myung-Hee Na, Ravikumar Ramachandran, Kern Rim, Huiling Shang
  • Patent number: 8916931
    Abstract: An N type layer made of an N type epitaxial layer in which an N+ type drain layer etc are formed is surrounded by a P type drain isolation layer extending from the front surface of the N type epitaxial layer to an N+ type buried layer. A P type collector layer is formed in an N type layer made of the N type epitaxial layer surrounded by the P type drain isolation layer and a P type element isolation layer, extending from the front surface to the inside of the N type layer. A parasitic bipolar transistor that uses the first conductive type drain isolation layer as the emitter, the second conductive type N type layer as the base, and the collector layer as the collector is thus formed so as to flow a surge current into a ground line.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: December 23, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Yasuhiro Takeda, Seiji Otake
  • Patent number: 8912596
    Abstract: A transistor used for a semiconductor device for high power application needs to have a channel region for obtaining higher drain current. As an example of such a transistor, a vertical (trench type) transistor has been considered; however, the vertical transistor cannot have a high on/off ratio of drain current and thus cannot have favorable transistor characteristics. Over a substrate having conductivity, an oxide semiconductor layer having a surface having a dotted pattern of a plurality of island-shaped regions with a tapered shape in a cross section is sandwiched between a first electrode formed between the substrate and the oxide semiconductor layer and a second electrode formed over the oxide semiconductor layer, and a conductive layer functioning as a gate electrode is formed on the side surface of the island-shaped region in the oxide semiconductor layer with an insulating layer provided therebetween.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: December 16, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8907431
    Abstract: A device includes a substrate, a semiconductor fin over the substrate, and a gate dielectric layer on a top surface and sidewalls of the semiconductor fin. A gate electrode is spaced apart from the semiconductor fin by the gate dielectric layer. The gate electrode includes a top portion over and aligned to the semiconductor fin, and a sidewall portion on a sidewall portion of the dielectric layer. The top portion of the gate electrode has a first work function, and the sidewall portion of the gate electrode has a second work function different from the first work function.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: December 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chin Kuo, Hsien-Ming Lee
  • Patent number: 8889500
    Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of fin-formation trenches that define a fin, forming a first stressed layer within the trenches and above the fin and performing at least one etching process on the first stressed layer so as to define spaced-apart portions of the first stressed layer positioned at least partially within the trenches on opposite sides of the fin. The method also includes forming spaced-apart portions of a second stressed layer above the spaced-apart portions of the first layer, forming a third stressed layer above the fin between the spaced-apart portions of the second layer and, after forming the third layer, forming a conductive layer above the second and third layers.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: November 18, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vimal K. Kamineni, Derya Deniz, Abner Bello, Abhijeet Paul, Robert J. Miller, William J. Taylor, Jr.
  • Patent number: 8890230
    Abstract: A semiconductor device includes two floating gates, a control gate and a first dielectric layer. The floating gates are disposed on a semiconductor substrate. The control gate partially overlaps each of the floating gates, and a part of the control gate is disposed between the two floating gates. Furthermore, the first dielectric layer disposed between the two floating gates and the control gate has a fixed thickness.
    Type: Grant
    Filed: July 15, 2012
    Date of Patent: November 18, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Yuan Hsu, Chi Ren, Tzeng-Fei Wen
  • Patent number: 8872220
    Abstract: An integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (110) crystal orientations. NMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (100) crystal orientations in a Manhattan layout with the sidewall channels of the different PMOS and NMOS MuGFETs aligned at 0° or 90° rotations.
    Type: Grant
    Filed: April 2, 2013
    Date of Patent: October 28, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Weize W. Xiong, Cloves R. Cleavelin, Angelo Pinto, Rick L. Wise
  • Patent number: 8872280
    Abstract: The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate is disposed on the fin structure. The dielectric layer is disposed between the fin structure and the gate. The source/drain region is disposed in the fin structure. The present invention further provides a method of forming the same.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: October 28, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Shih-Hung Tsai, Ssu-I Fu, Ying-Tsung Chen, Chih-Wei Chen, Ying-Chih Lin, Chien-Ting Lin, Hsuan-Hsu Chen
  • Patent number: 8859389
    Abstract: Methods of making fins and semiconductor structures containing fins are provided. The methods involve forming a multi-layer structure over a semiconductor substrate. The multi-layer structure comprises a first layer over the semiconductor substrate, a second layer over the first layer, and a third layer over the second layer. The method also comprises removing upper portions of the semiconductor substrate and portions of the multi-layer structure to form fins of the semiconductor substrate and portions of the multi-layer structure. Further, the method comprises selectively oxidizing the first layer while oxidization of the second layer and the third layer is less than the oxidization of the first layer. The oxidation can be performed before gap fill recess or after gap fill recess.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: October 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirohisa Kawasaki, Basker Veeraraghavan, Hemant Adhikari, Witold Maszara
  • Patent number: 8859355
    Abstract: A method of fabricating a semiconductor device including proving a substrate having a germanium containing layer that is present on a dielectric layer, and etching the germanium containing layer of the substrate to provide a first region including a germanium containing fin structure and a second region including a mandrel structure. A first gate structure may be formed on the germanium containing fin structures. A III-V fin structure may then be formed on the sidewalls of the mandrel structure. The mandrel structure may be removed. A second gate structure may be formed on the III-V fin structure.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: October 14, 2014
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 8841650
    Abstract: An electronic structure modulation transistor having two gates separated from a channel by corresponding dielectric layers, wherein the channel is formed of a material having an electronic structure that is modified by an electric field across the channel.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: September 23, 2014
    Assignee: Cornell University
    Inventor: Hassan Raza
  • Patent number: 8835917
    Abstract: An object is to provide a semiconductor device having electrical characteristics such as high withstand voltage, low reverse saturation current, and high on-state current. In particular, an object is to provide a power diode and a rectifier which include non-linear elements. An embodiment of the present invention is a semiconductor device including a first electrode, a gate insulating layer covering the first electrode, an oxide semiconductor layer in contact with the gate insulating layer and overlapping with the first electrode, a pair of second electrodes covering end portions of the oxide semiconductor layer, an insulating layer covering the pair of second electrodes and the oxide semiconductor layer, and a third electrode in contact with the insulating layer and between the pair of second electrodes. The pair of second electrodes are in contact with end surfaces of the oxide semiconductor layer.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: September 16, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiromichi Godo, Satoshi Kobayashi
  • Patent number: 8815690
    Abstract: The present disclosure provides a tunneling device, which comprises: a substrate; a channel region formed in the substrate, and a source region and a drain region formed on two sides of the channel region; and a gate stack formed on the channel region and a first side wall and a second side wall formed on two sides of the gate stack, wherein the gate stack comprises: a first gate dielectric layer; at least a first gate electrode and a second gate electrode formed on the first gate dielectric layer; a second gate dielectric layer formed between the first gate electrode and the first side wall; and a third gate dielectric layer formed between the second gate electrode and the second side wall.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: August 26, 2014
    Assignee: Tsinghua University
    Inventors: Ning Cui, Renrong Liang, Jing Wang, Jun Xu
  • Patent number: 8816428
    Abstract: Methods and systems for forming multigate devices and systems are disclosed. In accordance with one such method, a fin is formed on a semiconductor substrate including a carbon-doped semiconductor layer. Further, a first portion of semiconductor material that is beneath the fin is removed to form a void beneath the fin by etching the material such that the fin is supported by at least one supporting pillar of the semiconducting material and such that the carbon-doped semiconductor layer prevents the etching from removing at least a portion of the fin. A dielectric material is deposited in the void to isolate the fin from a second portion of semiconductor material that is below the void. In addition, source and drain regions are formed in the fin and a gate structure is formed over the fin to fabricate the multigate device such that the dielectric material reduces current leakage beneath the device.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Robert J. Miller, Tenko Yamashita, Hui Zang
  • Patent number: 8815691
    Abstract: The device includes a wafer substrate including an isolation feature, a fin base embedded in the isolation feature, at least one channel disposed above the fin base, and a gate stack disposed around the channel, wherein the gate stack includes a top portion and a bottom portion of the gate stack formed by filling a cavity around the channel such that the top portion and bottom portion are aligned each other. The device further includes at least one source and one drain disposed over the fin base, wherein the channel connects the source and the drain. The device further includes the source and the drain disposed over a fin insulator disposed over the fin base.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: August 26, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jean-Pierre Colinge, Kuo-Cheng Ching, Zhiqiang Wu
  • Patent number: 8803132
    Abstract: A method of fabricating a semiconducting device is disclosed. A graphene sheet is formed on a substrate. At least one slot is formed in the graphene sheet, wherein the at least one slot has a width that allows an etchant to pass through the graphene sheet. An etchant is applied to the substrate through the at least one slot formed in the graphene sheet to etch the substrate.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Damon B. Farmer, Aaron D. Franklin, Joshua T. Smith
  • Patent number: 8796777
    Abstract: A method includes forming a gate of a transistor within a substrate having a surface and forming a buried oxide (BOX) layer within the substrate and adjacent to the gate at a first BOX layer face. The method also includes forming a raised source-drain channel (“fin”), where at least a portion of the fin extends from the surface of the substrate, and where the fin has a first fin face adjacent a second BOX layer face of the BOX layer.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: August 5, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Seung-Chul Song, Mohamed Abu-Rahma, Beom-Mo Han
  • Patent number: 8796096
    Abstract: A method of fabricating a semiconducting device is disclosed. A graphene sheet is formed on a substrate. At least one slot is formed in the graphene sheet, wherein the at least one slot has a width that allows an etchant to pass through the graphene sheet. An etchant is applied to the substrate through the at least one slot formed in the graphene sheet to etch the substrate.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: Damon B. Farmer, Aaron D. Franklin, Joshua T. Smith
  • Patent number: 8791028
    Abstract: According to one embodiment, a manufacturing method of a semiconductor device includes a step of forming a dummy-fin semiconductor on a semiconductor substrate; a step of forming an insulating layer, into which a lower part of the dummy-fin semiconductor is buried, on the semiconductor substrate; a step of forming a fin semiconductor, which is bonded to a side face at an upper part of the dummy-fin semiconductor, on the insulating layer; and a step of removing the dummy-fin semiconductor on the insulating layer with the fin semiconductor being left on the insulating layer.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: July 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kimitoshi Okano
  • Patent number: 8759919
    Abstract: A method for fabricating a semiconductor device includes forming a plurality of gate structures on a semiconductor substrate. The plurality of gate structures are arranged in a plurality of lines, wherein an end-to-end spacing between the lines is smaller than a line-to-line spacing between the lines. The method further includes forming an etch stop layer over the gate structures, forming an interlayer dielectric over the gate structures, and forming a dielectric film over the gate structures before the interlayer dielectric is formed. The dielectric film merges in end-to-end gaps formed in the end-to-end spacing between the gate structures.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: June 24, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Shiang-Bau Wang
  • Patent number: 8742508
    Abstract: A three dimensional FET device structure which includes a plurality of three dimensional FET devices. Each of the three dimensional FET devices include an insulating base, a three dimensional fin oriented perpendicular to the insulating base, a gate dielectric wrapped around the three dimensional fin and a gate wrapped around the gate dielectric and extending perpendicularly to the three dimensional fin, the three dimensional fin having a device width being defined as the circumference of the three dimensional fin in contact with the gate dielectric. At least a first of the three dimensional FET devices has a first device width while at least a second of the three dimensional FET devices has a second device width. The first device width is different than the second device width. Also included is a method of making the three dimensional FET device structure.
    Type: Grant
    Filed: July 16, 2011
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni
  • Patent number: 8735990
    Abstract: The embodiments of the invention provide a structure and method for a rad-hard FinFET or mesa. More specifically, a semiconductor structure is provided having at least one fin or mesa comprising a channel region on an isolation region. A doped substrate region is also provided below the fin, wherein the doped substrate region has a first polarity opposite a second polarity of the channel region. The isolation region contacts the doped substrate region. The structure further includes a gate electrode covering the channel region and at least a portion of the isolation region. The gate electrode comprises a lower portion below the channel region of the fin, wherein the lower portion of the gate electrode comprises a height that is at least one-half of a thickness of the fin.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: May 27, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Robert H. Dennard, Mark C. Hakey, Edward J. Nowak
  • Patent number: 8729558
    Abstract: According to one embodiment, a nitride semiconductor device includes a semiconductor layer, a source electrode, a drain electrode, a first and a second gate electrode. The semiconductor layer includes a nitride semiconductor. The source electrode provided on a major surface of the layer forms ohmic contact with the layer. The drain electrode provided on the major surface forms ohmic contact with the layer and is separated from the source electrode. The first gate electrode is provided on the major surface between the source and drain electrodes. The second gate electrode is provided on the major surface between the source and first gate electrodes. When a potential difference between the source and first gate electrodes is 0 volts, a portion of the layer under the first gate electrode is conductive. The first gate electrode is configured to switch a constant current according to a voltage applied to the second gate electrode.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: May 20, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masahiko Kuraguchi
  • Publication number: 20140110785
    Abstract: A field effect transistor device includes a fin including a semiconductor material arranged on an insulator layer, the fin including a channel region, a hardmask layer arranged partially over the channel region of the fin, a gate stack arranged over the hardmask layer and over the channel region of the fin, a metallic alloy layer arranged on a first portion of the hardmask layer, the metallic alloy layer arranged adjacent to the gate stack, and a first spacer arranged adjacent to the gate stack and over the metallic alloy layer.
    Type: Application
    Filed: November 9, 2012
    Publication date: April 24, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hemanth Jagannathan, Sanjay C. Mehta, Junli Wang, Chun-Chen Yeh, Stefan Schmitz
  • Patent number: 8680588
    Abstract: A field effect transistor includes a buried gate pattern that is electrically isolated by being surrounded by a tunneling insulating film. The field effect transistor also includes a channel region that is floated by source and drain regions, a gate insulating film, and the tunneling insulating film. The buried gate pattern and the tunneling insulating film extend into the source and drain regions. Thus, the field effect transistor efficiently stores charge carriers in the buried gate pattern and the floating channel region.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: March 25, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ming Li, Dong-Uk Choi, Chang-Woo Oh, Dong-Won Kim, Min-Sang Kim, Sung-Hwan Kim, Kyoung-Hwan Yeo
  • Patent number: 8679906
    Abstract: In one embodiment, there is an asymmetric multi-gated transistor that has a semiconductor fin with a non-uniform doping profile. A first portion of the fin has a higher doping concentration while a second portion of the fin has a lower doping concentration. In another embodiment, there is an asymmetric multi-gated transistor with gate dielectrics formed on the semiconductor fin that vary in thickness. This asymmetric multi-gated transistor has a thin gate dielectric formed on a first side portion of the semiconductor fin and a thick gate dielectric formed on a second side portion of the fin.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: March 25, 2014
    Assignee: International Business Machines Corporation
    Inventor: Kangguo Cheng
  • Patent number: 8679918
    Abstract: Disclosed is a multiple-gate transistor that includes a channel region and source and drain regions at ends of the channel region. A gate oxide is positioned between a logic gate and the channel region and a first insulator is formed between a floating gate and the channel region. The first insulator is thicker than the gate oxide. The floating gate is electrically insulated from other structures. Also, a second insulator is positioned between a programming gate and the floating gate. Voltage in the logic gate causes the transistor to switch on and off, while stored charge in the floating gate adjusts the threshold voltage of the transistor. The transistor can comprise a fin-type field effect transistor (FinFET), where the channel region comprises the middle portion of a fin structure and the source and drain regions comprise end portions of the fin structure.
    Type: Grant
    Filed: May 15, 2007
    Date of Patent: March 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 8673712
    Abstract: Presented herein is a field effect transistor device, optionally a lateral power transistor, and a method for forming the same, comprising providing a substrate, creating a doped buried layer, and creating a primary well in the substrate on the buried layer. A drift drain may be created in the primary well and a counter implant region implanted in the primary well and between the drift drain and the buried layer. The primary well may comprise a first and second implant region with the second implant region at a depth less than the first. The counter implant may be at a depth between the first and second implant regions. The primary well and counter implant region may comprise dopants of the same conductivity type, or both p+-type dopants. A gate may be formed over a portion of a drift drain.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: March 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Kuang Hsiao, Chen-Liang Chu, Yi-Sheng Chen, Fei-Yuh Chen, Kong-Beng Thei
  • Publication number: 20140054709
    Abstract: A transistor device includes a pair of source/drain regions having a channel region there-between. A first gate is proximate the channel region. A gate dielectric is between the first gate and the channel region. A second gate is proximate the channel region. A programmable material is between the second gate and the channel region. The programmable material includes at least one of a) a multivalent metal oxide portion and an oxygen-containing dielectric portion, or b) a multivalent metal nitride portion and a nitrogen-containing dielectric portion. Memory cells and arrays of memory cells are disclosed.
    Type: Application
    Filed: August 27, 2012
    Publication date: February 27, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: D. V. Nirmal Ramaswamy, Gurtej S. Sandhu
  • Patent number: 8659114
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate, a trench formed in an element isolating area of the semiconductor substrate, and a silicon oxide film that is embedded in the trench and contains an alkali metal element or alkali earth metal element.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: February 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Keisuke Nakazawa
  • Patent number: 8659091
    Abstract: Multigate transistor devices and methods of their fabrication are disclosed. In accordance with one method, a fin and a gate structure that is disposed on a plurality of surfaces of the fin are formed. In addition, at least a portion of an extension of the fin is removed to form a recessed portion that is below the gate structure, is below a channel region of the fin, and includes at least one angled indentation. Further, a terminal extension is grown in the at least one angled indentation below the channel region and along a surface of the channel region such that the terminal extension provides a stress on the channel region to enhance charge carrier mobility in the channel region.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: February 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ming Cai, Dechao Guo, Pranita Kulkarni, Chun-Chen Yeh
  • Patent number: 8652889
    Abstract: When forming sophisticated semiconductor devices, three-dimensional transistors in combination with planar transistors may be formed on the basis of a replacement gate approach and self-aligned contact elements by forming the semiconductor fins in an early manufacturing stage, i.e., upon forming shallow trench isolations, wherein the final electrically effective height of the semiconductor fins may be adjusted after the provision of self-aligned contact elements and during the replacement gate approach.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: February 18, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Andy Wei, Peter Baars, Richard Carter, Frank Ludwig
  • Publication number: 20140035066
    Abstract: The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate is disposed on the fin structure. The dielectric layer is disposed between the fin structure and the gate. The source/drain region is disposed in the fin structure. The present invention further provides a method of forming the same.
    Type: Application
    Filed: July 31, 2012
    Publication date: February 6, 2014
    Inventors: Shih-Hung Tsai, Ssu-I Fu, Ying-Tsung Chen, Chih-Wei Chen, Ying-Chih Lin, Chien-Ting Lin, Hsuan-Hsu Chen
  • Patent number: 8637935
    Abstract: A method for forming a semiconductor device comprises: forming at least one gate stack structure and an interlayer material layer between the gate stack structures on a semiconductor substrate; defining isolation regions and removing a portion of the interlayer material layer and a portion of the semiconductor substrate which has a certain height in the regions, so as to form trenches; removing portions of the semiconductor substrate which carry the gate stack structures, in the regions; and filling the trenches with an insulating material. A semiconductor device is also provided. The area of the isolation regions may be reduced.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: January 28, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huicai Zhong, Qingqing Liang, Haizhou Yin, Huilong Zhu
  • Patent number: 8633471
    Abstract: Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed, which may include a modulation doped heterostructure, wherein the modulation doped heterostructure may comprise an active portion having a first bandgap and a delta doped portion having a second bandgap.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: January 21, 2014
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Mantu Hudait, Marko Radosavljevic, Willy Rachmady, Gilbert Dewey, Jack Kavalieros
  • Patent number: 8629039
    Abstract: A device includes a number of fins. Some of the fins have greater heights than other fins. This allows the selection of different drive currents and/or transistor areas.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: January 14, 2014
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Justin S. Sandford, Michael K. Harper
  • Patent number: 8629500
    Abstract: An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric (GD1) in comparison with other transistors (T2) on the same integrated circuit arrangement (10). As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions (D1, S1) of the tunnel field effect transistor.
    Type: Grant
    Filed: December 9, 2005
    Date of Patent: January 14, 2014
    Assignee: Infineon Technologies AG
    Inventors: Juergen Holz, Ronald Kakoschke, Thomas Nirschl, Christian Pacha, Klaus Schruefer, Thomas Schulz, Doris Schmitt-Landsiedel
  • Patent number: 8629511
    Abstract: In a replacement gate scheme, after formation of a gate dielectric layer, a work function material layer completely fills a narrow gate trench, while not filling a wide gate trench. A dielectric material layer is deposited and planarized over the work function material layer, and is subsequently recessed to form a dielectric material portion overlying a horizontal portion of the work function material layer within the wide gate trench. The work function material layer is recessed employing the dielectric material portion as a part of an etch mask to form work function material portions. A conductive material is deposited and planarized to form gate conductor portions, and a dielectric material is deposited and planarized to form gate cap dielectrics.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: January 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Charles W. Koburger, III, Marc A. Bergendahl, David V. Horak, Shom Ponoth, Chih-Chao Yang
  • Patent number: 8629512
    Abstract: The description relates to a gate stack of a fin field effect transistor (FinFET). An exemplary structure for a FinFET includes a substrate including a first surface and an insulation region covering a portion of the first surface, where a top of the insulation region defines a second surface. The FinFET further includes a fin disposed through an opening in the insulation region to a first height above the second surface, where a base of an upper portion of the fin is broader than a top of the upper portion, wherein the upper portion has first tapered sidewalls and a third surface. The FinFET further includes a gate dielectric covering the first tapered sidewalls and the third surface and a conductive gate strip traversing over the gate dielectric, where the conductive gate strip has second tapered sidewalls along a longitudinal direction of the fin.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Publication number: 20140008733
    Abstract: Some aspects relate to a FinFET that includes a semiconductor fin disposed over a semiconductor substrate and extending laterally between a source region and a drain region. A shallow trench isolation (STI) region laterally surrounds a lower portion of the semiconductor fin, and an upper portion of the semiconductor fin remains above the STI region. A gate electrode traverses over the semiconductor fin to define a channel region in the semiconductor fin under the conductive gate electrode. A punch-through blocking region can extend between the source region and the channel region in the lower portion of the semiconductor fin. A drain extension region can extend between the drain region and the channel region in the lower portion of the semiconductor fin. Other devices and methods are also disclosed.
    Type: Application
    Filed: July 3, 2012
    Publication date: January 9, 2014
    Applicant: Intel Mobile Communications GmbH
    Inventors: Mayank Shrivastava, Harald Gossner
  • Patent number: 8623719
    Abstract: A method and semiconductor structure includes an insulator layer on a substrate, a plurality of parallel fins above the insulator layer. Each of the fins has a central semiconductor portion and conductive end portions. At least one conductive strap is positioned within the insulator layer below the fins. The conductive strap can be perpendicular to the fins and contact the fins. The conductive strap includes recessed portions disposed within the insulator layer, below the plurality of fins, and between each of the plurality of fins, and projected portions disposed above the insulator layer, collinear with each of the plurality of fins. The conductive strap is disposed in at least one of a source region and a drain region of the semiconductor structure. A gate insulator contacts and covers the central semiconductor portion of the fins, and a gate conductor covers and contacts the gate insulator.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: January 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Andres Bryant, Edward J. Nowak, Jed H. Rankin
  • Patent number: 8618609
    Abstract: Embodiments of an apparatus and methods for improving multi-gate device performance are generally described herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: December 31, 2013
    Assignee: Intel Corporation
    Inventors: Brian Doyle, Titash Rakshit, Jack Kavalieros
  • Publication number: 20130341720
    Abstract: A method and circuit for implementing field effect transistors (FETs) having a gate within a gate utilizing a replacement metal gate process (RMGP), and a design structure on which the subject circuit resides are provided. A field effect transistor utilizing a RMGP includes a sacrificial gate in a generally central metal gate region on a dielectric layer on a substrate, a source and drain formed in the substrate, a pair of dielectric spacers, a first metal gate and a second metal gate replacing the sacrificial gate inside the central metal gate region, and a second gate dielectric layer separating the first metal gate and the second metal gate. A respective electrical contact is formed on opposite sides of the central metal gate region for respectively electrically connecting the first metal gate and the second metal gate to a respective voltage.
    Type: Application
    Filed: June 26, 2012
    Publication date: December 26, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams
  • Patent number: RE45165
    Abstract: A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Wei Chen, Tang-Xuan Zhong, Sheng-Da Liu, Chang-Yu Chang, Ping-Kun Wu, Chao-Hsiung Wang, Fu-Liang Yang
  • Patent number: RE45180
    Abstract: A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: October 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Wei Chen, Tang-Xuan Zhong, Sheng-Da Liu, Chang-Yun Chang, Ping-Kun Wu, Chao-Hsiung Wang, Fu-Liang Yang