To Form Insulating Layer Thereon, E.g., For Masking Or By Using Photolithographic Technique (epo) Patents (Class 257/E21.24)

  • Patent number: 11915937
    Abstract: A method includes forming a plurality of nanostructures over a substrate; etching the plurality of nanostructures to form recesses; forming source/drain regions in the recesses; removing first nanostructures of the plurality of nanostructures leaving second nanostructures of the plurality of nanostructures; depositing a gate dielectric over and around the second nanostructures; depositing a protective material over the gate dielectric; performing a fluorine treatment on the protective material; removing the protective material; depositing a first conductive material over the gate dielectric; and depositing a second conductive material over the first conductive material.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yi Lee, Mao-Lin Huang, Lung-Kun Chu, Huang-Lin Chao, Chi On Chui
  • Patent number: 11894460
    Abstract: A semiconductor device structure is provided. The device includes one or more first semiconductor layers, and a dipole layer surrounding each first semiconductor layer of the one or more first semiconductor layers, wherein the dipole layer comprises germanium. The structure also includes a capping layer surrounding and in contact with the dipole layer, wherein the capping layer comprises silicon, one or more second semiconductor layers disposed adjacent the one or more first semiconductor layers. The structure further includes a gate electrode layer surrounding each first semiconductor layer of the one or more first semiconductor layers and each second semiconductor layer of the one or more second semiconductor layers.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Wei Hsu, Kuo-Cheng Chiang, Mao-Lin Huang, Lung-Kun Chu, Jia-Ni Yu, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11862468
    Abstract: In an embodiment, a method includes: depositing a gate dielectric layer on a first fin and a second fin, the first fin and the second fin extending away from a substrate in a first direction, a distance between the first fin and the second fin decreasing along the first direction; depositing a sacrificial layer on the gate dielectric layer by exposing the gate dielectric layer to a self-limiting source precursor and a self-reacting source precursor, the self-limiting source precursor reacting to form an initial layer of a material of the sacrificial layer, the self-reacting source precursor reacting to form a main layer of the material of the sacrificial layer; annealing the gate dielectric layer while the sacrificial layer covers the gate dielectric layer; after annealing the gate dielectric layer, removing the sacrificial layer; and after removing the sacrificial layer, forming a gate electrode layer on the gate dielectric layer.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuei-Lun Lin, Chia-Wei Hsu, Xiong-Fei Yu, Chi On Chui, Chih-Yu Hsu, Jian-Hao Chen
  • Patent number: 11855212
    Abstract: FDSOI device fabrication method is disclosed. The method comprises: disposing a buried oxide layer on the silicon substrate; disposing a SiGe channel on the buried oxide layer, disposing a nitrogen passivation layer on the SiGe channel layer; disposing a metal gate on the nitrogen passivation layer, and attaching sidewalls to sides of the metal gate; and disposing source and drain regions on the nitrogen passivation layer at both sides of the metal gate, wherein the source and drain regions are built in a raised SiGe layer. The stack structure of the SiGe layer and the nitrogen passivation layer forms the gate channel. This stack structure avoids the low stress of the silicon channel in the conventional device. In addition, it prevents the Ge diffusion from the SiGe channel to the gate dielectric in the conventional device. Thereby the invention improves reliability and performance of the device.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: December 26, 2023
    Assignee: SHANGHAI HUALI INTEGRATED CIRCUIT CORPORATION
    Inventors: Zhonghua Li, Runling Li, Nan Li, Jianghua Leng, Tianpeng Guan
  • Patent number: 11761084
    Abstract: A substrate processing apparatus includes a stage provided in a chamber, a shower head in which a plurality of slits are formed and which is opposed to the stage, a first gas supply part which supplies a first gas to a space between the stage and the shower head via the plurality of slits, and a second gas supply part which supplies a second gas which is not a noble gas to a region below the stage, wherein the second gas is the same gas as one of a plurality of kinds of gases constituting the first gas in a case where the first gas is a mixture gas constituted of the plurality of kinds of gases, and the second gas is the same gas as the first gas in a case where the first gas is a single kind of gas.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: September 19, 2023
    Assignee: ASM IP Holding B.V.
    Inventors: Hiroki Arai, Yukihiro Mori, Yuya Nonaka
  • Patent number: 11725111
    Abstract: Described herein are compositions for depositing a carbon-doped silicon containing film comprising: a precursor comprising at least one compound selected from the group consisting of: an organoaminosilane having a formula of R8N(SiR9LH)2, wherein R8, R9, and L are defined herein. Also described herein are methods for depositing a carbon-doped silicon-containing film using the composition wherein the method is one selected from the following: cyclic chemical vapor deposition (CCVD), atomic layer deposition (ALD), plasma enhanced ALD (PEALD) and plasma enhanced CCVD (PECCVD).
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: August 15, 2023
    Assignee: Versum Materials US, LLC
    Inventors: Manchao Xiao, Xinjian Lei, Ronald Martin Pearlstein, Haripin Chandra, Eugene Joseph Karwacki, Bing Han, Mark Leonard O'Neill
  • Patent number: 11699657
    Abstract: Embodiments of source structure of a three-dimensional (3D) memory device and method for forming the source structure of the 3D memory device are disclosed. In an example, a NAND memory device includes a substrate, an alternating conductor/dielectric stack, a NAND string, a source conductor layer, and a source contact. The alternating conductor/dielectric stack includes a plurality of conductor/dielectric pairs above the substrate. The NAND string extends vertically through the alternating conductor/dielectric stack. The source conductor layer is above the alternating conductor/dielectric stack and is in contact with an end of the NAND string. The source contact includes an end in contact with the source conductor layer. The NAND string is electrically connected to the source contact by the source conductor layer. In some embodiments, the source conductor layer includes one or more conduction regions each including one or more of a metal, a metal alloy, and a metal silicide.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: July 11, 2023
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jifeng Zhu, Zhenyu Lu, Jun Chen, Yushi Hu, Qian Tao, Simon Shi-Ning Yang, Steve Weiyi Yang
  • Patent number: 11646369
    Abstract: In an SiC-MOSFET with a built-in Schottky diode, a bipolar current may be passed in a second well region formed at a terminal part to reduce a breakdown voltage. In the SiC-MOSFET with the built-in Schottky diode, a conductive layer in Schottky connection with the second well region is provided on the second well region in the terminal part, and the conductive layer is electrically connected with a source electrode of the MOSFET. A conductive layer contact hole is provided for connecting only the conductive layer and the source electrode.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: May 9, 2023
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yuichi Nagahisa, Shiro Hino, Koji Sadamatsu, Hideyuki Hatta, Kotaro Kawahara
  • Patent number: 11641742
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. A wall is formed in individual of the trenches laterally-between immediately-laterally-adjacent of the memory-block regions. The forming of the wall comprises lining sides of the trenches with insulative material comprising at least one of an insulative nitride and elemental-form boron. A core material is formed in the trenches to span laterally-between the at least one of the insulative nitride and the elemental-form boron. Structure independent of method is disclosed.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: May 2, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Cole Smith, Ramey M. Abdelrahaman, Silvia Borsari, Chris M. Carlson, David Daycock, Matthew J. King, Jin Lu
  • Patent number: 11602743
    Abstract: A method of fabricating a carbon nanotube (“CNT”) array includes providing a substrate with a CNT catalyst disposed on a surface of the substrate, heating the CNT catalyst to an annealing temperature, exposing the CNT catalyst to a CNT precursor for an exposure period to pre-load the CNT catalyst, and exposing the pre-loaded CNT catalyst to a carbon source for a growth period to form the CNT array. The formed CNT array comprises a plurality of CNT bundles that are aligned with one another in an alignment direction. At least one of the plurality of bundles comprises an average structural factor of 1.5 or less along an entirety of the length thereof.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: March 14, 2023
    Assignees: Toyota Motor Engineering & Manufacturing North America, Inc., Vanderbilt University
    Inventors: Yuyang Song, Shailesh N. Joshi, Piran R. Kidambi, Peifu Cheng
  • Patent number: 11569385
    Abstract: An FDSOI device and fabrication method are disclosed. The device comprises: a buried oxide layer disposed on the silicon substrate; a SiGe channel disposed on the buried oxide layer, a nitrogen passivation layer disposed on the SiGe channel layer; a metal gate disposed on the nitrogen passivation layer, and sidewalls attached to sides of the metal gate; and a source and a drain regions disposed on the nitrogen passivation layer at both sides of the metal gate, wherein the source and drain regions are built in a raised SiGe layer. The stack structure of the SiGe layer and the nitrogen passivation layer forms the channel. This stack structure avoids the low stress of the silicon channel in the conventional device. In addition, it prevents the Ge diffusion from the SiGe channel to the gate dielectric in the conventional device. Thereby the invention improves reliability and performance of the device.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: January 31, 2023
    Assignee: Shanghai Huali Integrated Circuit Corporation
    Inventors: Zhonghua Li, Runling Li, Nan Li, Jianghua Leng, Tianpeng Guan
  • Patent number: 11545521
    Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: January 3, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei Chen, Hui-Lin Wang, Yu-Ru Yang, Chin-Fu Lin, Yi-Syun Chou, Chun-Yao Yang
  • Patent number: 11545583
    Abstract: An electronic device can include a NVM cell. The NVM cell can include a drain/source region, a source/drain region, a floating gate electrode, a control gate electrode, and a select gate electrode. The NVM cell can be fabricated using a process flow that also forms a power transistor, high-voltage transistors, and low-voltage transistors on the same die. A relatively small size for the NVM can be formed using a hard mask to define a gate stack and spacer between gate stack and select gate electrode. A gate dielectric layer can be used for the select gate electrode and transistors in a low-voltage region and allows for a fast read access time.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: January 3, 2023
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Weize Chen, Sameer S. Haddad, Bruce B. Greenwood, Mark Griswold, Kenneth A. Bates
  • Patent number: 11515153
    Abstract: A method of forming a silicon nitride film on a substrate having a recess pattern formed in a surface thereof, includes: forming the silicon nitride film in conformity to the surface of the substrate by supplying each of a raw material gas containing silicon and a nitriding gas for nitriding the raw material gas into a processing container in which the substrate is accommodated; shrinking the silicon nitride film such that a thickness thereof is reduced from a bottom side toward an upper side of the recess pattern by supplying a plasmarized shaping gas for shaping the silicon nitride film to the substrate in a state where the supply of the raw material gas containing silicon into the processing container is stopped; and burying the silicon nitride film in the recess pattern by alternately and repeatedly performing the forming the silicon nitride film and the shrinking the silicon nitride film.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: November 29, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Jun Ogawa
  • Patent number: 11508814
    Abstract: A transistor including at least one two-dimensional (2D) channel is disclosed. A transistor according to some example embodiments includes first to third electrodes separated from each other, and a channel layer that is in contact with the first and second electrodes, parallel to the third electrode, and includes at least one 2D channel. The at least one 2D channel includes at least two regions having different doping concentrations. A transistor according to some example embodiments includes: first to third electrodes separated from each other; a 2D channel layer that is in contact with the first and second electrodes and parallel to the third electrode; a first doping layer disposed under the 2D channel layer corresponding to the first electrode; and a second doping layer disposed under the 2D channel layer corresponding to the second electrode, wherein the first and second doping layers contact the 2D channel layer.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: November 22, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Minhyun Lee, Minsu Seol, Hyeonjin Shin
  • Patent number: 11444238
    Abstract: A magnetic random access memory (MRAM) array includes a plurality of MRAM cells, each of the MRAM cells including a magnetic tunnel junction (MTJ) stack disposed on a bottom metal via connecting the MTJ stack to a bottom conductive contact in a substrate, a plurality of top conductive contacts, each of the top conductive contacts disposed on a respective one of the MTJ stacks, and a plurality of unitary structures configured as a heat sink/magnetic shield disposed on a vertical portions of each of the MRAM cells, including vertical portions of the bottom metal vias, and under a portion of each of the MTJ stacks.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: September 13, 2022
    Assignee: International Business Machines Corporation
    Inventors: Julien Frougier, Ruilong Xie, Heng Wu, Chen Zhang, Bruce B. Doris
  • Patent number: 10866017
    Abstract: A processing apparatus includes a first temperature measuring unit configured to measure a surface temperature of a first member exposed in a first closed space, a supply line configured to supply a low-dew point gas into the first closed space and a control unit configured to control a flow rate of the low-dew point gas. The control unit performs a first process to a third process. In the first process, an absolute humidity of a gas within the first closed space at a position of a surface of the first member is specified for the flow rate of the low-dew point gas. In the second process, a saturated absolute humidity at the surface temperature of the first member is specified. In the third process, the flow rate of the low-dew point gas is controlled based on the absolute humidity of the gas and the saturated absolute humidity.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: December 15, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Shin Matsuura, Takuya Nishijima
  • Patent number: 10700006
    Abstract: There is provided a method for manufacturing Ni wiring. The method includes forming an Ni film on a surface of a substrate having a recess formed thereon by CVD or ALD by using an Ni compound as a film forming material and NH3 gas and H2 gas as reduction gases to partially fill the recess. The method further includes annealing the substrate to make the Ni film on the surface of the substrate and on a side surface of the recess reflow into the recess.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: June 30, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hiroaki Kawasaki, Takashi Matsumoto, Hiroyuki Nagai, Ryota Ifuku
  • Patent number: 10656540
    Abstract: A method of forming patterns is provided. The method may include forming a resist layer on a substrate and curing an extrusion confining pattern to define anchoring regions in the resist layer. The template may overlay over the resist layer. the template may include transfer patterns and anchor patterns. The template may be pressed to imprint the anchor patterns on the anchoring regions and to imprint the transfer patterns on a portion of the resist layer. An alignment may be performed to align the template with the resist layer.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: May 19, 2020
    Assignee: SK hynix Inc.
    Inventor: Wooyung Jung
  • Patent number: 10614866
    Abstract: A magnetoresistance effect element has a structure in which a first ferromagnetic layer, a non-magnetic layer, and a second ferromagnetic layer are subsequently laminated and outer circumferential portions of the first ferromagnetic layer, the non-magnetic layer, and the second ferromagnetic layer are covered with a first insulating film which contains silicon nitride as a main component and contains further boron nitride or aluminum nitride.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: April 7, 2020
    Assignee: TDK CORPORATION
    Inventors: Tomoyuki Sasaki, Yohei Shiokawa, Jiro Yoshinari
  • Patent number: 10316407
    Abstract: Described herein are compositions and methods using same for forming a silicon-containing film or material such as without limitation a silicon oxide, silicon nitride, silicon oxynitride, a carbon-doped silicon nitride, or a carbon-doped silicon oxide film in a semiconductor deposition process, such as without limitation, a plasma enhanced atomic layer deposition of silicon-containing film.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: June 11, 2019
    Assignee: VERSUM MATERIALS US, LLC
    Inventors: Xinjian Lei, Moo-Sung Kim, Matthew R. MacDonald, Manchao Xiao
  • Patent number: 9953950
    Abstract: A semiconductor structure comprising a first semiconductor structure; a second semiconductor structure; and a silicon-nitride layer configured to bond the first semiconductor structure and second semiconductor structure together. The first semiconductor structure comprises a first wafer; a first dielectric layer; a first interconnect structure; and a first oxide layer. The second semiconductor structure comprises a second wafer; a second dielectric layer; a second interconnect structure; and a second oxide layer. The structure further comprises a first nitride layer residing on a top surface of the first oxide layer formed by a nitridation process of the top surface of the first oxide layer; and a second nitride layer residing on a top surface of the second oxide layer formed by the nitridation process of the top surface of the second oxide layer. Further, the silicon-nitride layer comprises the first nitride layer and the second nitride layer.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: April 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Chih-Chao Yang
  • Patent number: 9947630
    Abstract: A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: April 17, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Jung Yang, Hsien-Wei Chen, Hsien-Ming Tu, Chang-Pin Huang, Yu-Chia Lai, Tung-Liang Shao
  • Patent number: 9666442
    Abstract: A method including forming a pattern on a surface of a substrate, the pattern including one of discrete structures including at least one sidewall defining an oblique angle relative to the surface and discrete structures complemented with a material layer therebetween, the material layer including a volume modified into distinct regions separated by at least one oblique angle relative to the surface; and defining circuit features on the substrate using the pattern, the features having a pitch less than a pitch of the pattern.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: May 30, 2017
    Assignee: Intel Corporation
    Inventors: Fitih M. Cinnor, Charles H. Wallace
  • Patent number: 9613806
    Abstract: A NAND flash memory array is initially patterned by forming a plurality of sidewall spacers according along sides of patterned portions of material. The pattern of sidewall spacers is then used to form a second pattern of hard mask portions including first hard mask portions defined on both sides by sidewall spacers and second hard mask portions defined on only one side by sidewall spacers.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: April 4, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jongsun Sel, Tuan Duc Pham, Mun Pyo Hong
  • Patent number: 9514935
    Abstract: A method of manufacturing a semiconductor device is provided, which enables the film quality to be improved when the film is formed on a substrate at a low temperature, thus forming fine patterns. The method of manufacturing a semiconductor device includes: forming the film on a substrate by alternately supplying at least a source gas and a reactive gas to the substrate while maintaining the substrate at a first temperature by heating; and modifying the film by supplying a modification gas excited by plasma to the substrate with the film formed thereon while naturally cooling the substrate with the film formed thereon to a second temperature without heating the substrate, the second temperature being lower than the first temperature.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: December 6, 2016
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Takaaki Noda, Takeo Hanashima
  • Patent number: 9287348
    Abstract: Devices, methods, and systems for ion trapping are described herein. One device includes a through-silicon via (TSV) and a trench capacitor formed around the TSV.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: March 15, 2016
    Assignee: Honeywell International Inc.
    Inventor: Daniel Youngner
  • Patent number: 9018767
    Abstract: A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Griselda Bonilla, Alfred Grill, Thomas J. Haigh, Jr., Satyanarayana V. Nitta, Son Nguyen
  • Patent number: 9013018
    Abstract: A moisture barrier, device or product having a moisture barrier or a method of fabricating a moisture barrier having at least a polymer layer, and interfacial layer, and a barrier layer. The polymer layer may be fabricated from any suitable polymer including, but not limited to, fluoropolymers such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), or ethylene-tetrafluoroethylene (ETFE). The interfacial layer may be formed by atomic layer deposition (ALD). In embodiments featuring an ALD interfacial layer, the deposited interfacial substance may be, but is not limited to, Al2O3, AlSiOx, TiO2, and an Al2O3/TiO2 laminate. The barrier layer associated with the interfacial layer may be deposited by plasma enhanced chemical vapor deposition (PECVD). The barrier layer may be a SiOxNy film.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: April 21, 2015
    Assignees: Beneq Oy, U.S. Department of Energy
    Inventors: Joel W. Pankow, Gary J. Jorgensen, Kent M. Terwilliger, Stephen H. Glick, Nora Isomaki, Kari Harkonen, Tommy Turkulainen
  • Patent number: 9012322
    Abstract: Wet-etch solutions for conductive metals (e.g., copper) and metal nitrides (e.g., tantalum nitride) can be tuned to differentially etch the conductive metals and metal nitrides while having very little effect on nearby oxides (e.g., silicon dioxide hard mask materials), and etching refractory metals (e.g. tantalum) at an intermediate rate. The solutions are aqueous base solutions (e.g., ammonia-peroxide mixture or TMAH-peroxide mixture) with just enough hydrofluoric acid (HF) added to make the solution's pH about 8-10. Applications include metallization of sub-micron logic structures.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: April 21, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Anh Duong, Errol Todd Ryan
  • Patent number: 8999859
    Abstract: Methods of depositing a film on a substrate surface include surface mediated reactions in which a film is grown over one or more cycles of reactant adsorption and reaction. In one aspect, the method is characterized by intermittent delivery of dopant species to the film between the cycles of adsorption and reaction.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: April 7, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Shankar Swaminathan, Jon Henri, Dennis M. Hausmann, Pramod Subramonium, Mandyam Sriram, Vishwanathan Rangarajan, Kirthi K. Kattige, Bart K. van Schravendijk, Andrew J. McKerrow
  • Patent number: 8993708
    Abstract: A carbazole polymer including a repeating unit represented by Formula 1 and having excellent one electron oxidation-state stability, wherein, in Formula 1, R1-R4 each independently represents an alkyl group having 1-60 carbon atoms, a haloalkyl group having 1-60 carbon atoms, or similar, Cz represents a divalent group including a carbazole skeleton represented by Formula 2, and Ar represents a divalent aromatic ring or similar; wherein, in Formula 2, R5 represents a hydrogen atom, an alkyl group having 1-60 carbon atoms, or similar, R6-R11 each independently represents a hydrogen atom, a halogen atom, or similar, and m represents an integer 1-10.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: March 31, 2015
    Assignee: Nissan Chemical Industries, Ltd.
    Inventors: Yuki Shibano, Takuji Yoshimoto
  • Patent number: 8993453
    Abstract: A method for fabricating a nonvolatile charge trap memory device and the device are described. In one embodiment, the method includes providing a substrate in an oxidation chamber, wherein the substrate comprises a first exposed crystal plane and a second exposed crystal plane, and wherein the crystal orientation of the first exposed crystal plane is different from the crystal orientation of the second exposed crystal plane. The substrate is then subjected to a radical oxidation process to form a first portion of a dielectric layer on the first exposed crystal plane and a second portion of the dielectric layer on the second exposed crystal plane, wherein the thickness of the first portion of the dielectric layer is approximately equal to the thickness of the second portion of the dielectric layer.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 31, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Jeong Byun, Sagy Levy
  • Patent number: 8994127
    Abstract: Embodiments related to semiconductor manufacturing and semiconductor devices with semiconductor structure are described and depicted.
    Type: Grant
    Filed: November 24, 2011
    Date of Patent: March 31, 2015
    Assignee: Infineon Technologies AG
    Inventors: Thoralf Kautzsch, Boris Binder, Torsten Helm, Stefan Kolb, Marc Probst, Uwe Rudolph
  • Patent number: 8980759
    Abstract: A method of forming a slanted field plate including forming epitaxy for a FET on a substrate, forming a wall near a drain of the FET, the wall comprising a first negative tone electron-beam resist (NTEBR), depositing a dielectric over the epitaxy and the wall, the wall causing the dielectric to have a step near the drain of the FET, depositing a second NTEBR over the dielectric, wherein surface tension causes the deposited second NTEBR to have a slanted top surface between the step and a source of the FET, etching anisotropically vertically the second NTEBR and the dielectric to remove the second NTEBR and to transfer a shape of the slanted top surface to the dielectric, and forming a gatehead comprising metal on the dielectric between the step and the source of the FET, wherein the gatehead forms a slanted field plate.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: March 17, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Andrea Corrion, Joel C. Wong, Keisuke Shinohara, Miroslav Micovic, Ivan Milosavljevic, Dean C. Regan, Yan Tang
  • Patent number: 8975194
    Abstract: Disclosed a method for manufacturing an oxide layer, applicable to a manufacture procedure of a field oxide layer of a CMOS transistor in the field of semiconductor manufacturing, the method includes: injecting a first gas satisfying a first predetermined condition into a processing furnace in which a first CMOS transistor semi-finished product formed with an N-well and a P-well is placed, and dry-oxidizing the first CMOS transistor semi-finished product into a second CMOS transistor semi-finished product; and injecting a second gas satisfying a second predetermined condition different from the first predetermined condition into the processing furnace, and wet-oxidizing the second CMOS transistor semi-finished product into a third CMOS transistor semi-finished product.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: March 10, 2015
    Assignees: Peking University Founder Group Co., Ltd., Founder Microelectronics International Co., Ltd.
    Inventor: Jinyuan Chen
  • Patent number: 8962486
    Abstract: The present invention provides a method of forming an opening on a semiconductor substrate. First, a substrate is provided. Then a dielectric layer and a cap layer are formed on the substrate. A ratio of a thickness of the dielectric layer and a thickness of the cap layer is substantially between 15 and 1.5. Next, a patterned boron nitride layer is formed on the cap layer. Lastly, an etching process is performed by using the patterned hard mask as a mask to etch the cap layer and the dielectric layer so as to form an opening in the cap layer and the dielectric layer.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: February 24, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Po-Chun Chen
  • Patent number: 8940645
    Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes subjecting a substrate to a first oxidation process to form a tunnel oxide layer overlying a polysilicon channel, and forming over the tunnel oxide layer a multi-layer charge storing layer comprising an oxygen-rich, first layer comprising a nitride, and an oxygen-lean, second layer comprising a nitride on the first layer. The substrate is then subjected to a second oxidation process to consume a portion of the second layer and form a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The stoichiometric composition of the first layer results in it being substantially trap free, and the stoichiometric composition of the second layer results in it being trap dense. The second oxidation process can comprise a plasma oxidation process or a radical oxidation process using In-Situ Steam Generation.
    Type: Grant
    Filed: July 1, 2012
    Date of Patent: January 27, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Sagy Levy, Jeong Byun
  • Patent number: 8936957
    Abstract: The present disclosure discloses a method of manufacturing a light-emitting device comprising the steps of providing a light-emitting wafer having a semiconductor stacked structure and an alignment mark, sensing the alignment mark, and separating the light-emitting wafer into a plurality of light-emitting diodes and removing the alignment mark accordingly.
    Type: Grant
    Filed: December 24, 2013
    Date of Patent: January 20, 2015
    Assignee: Epistar Corporation
    Inventor: Tsung-Hsien Yang
  • Patent number: 8932935
    Abstract: A three dimensional shallow trench isolation structure including sets of parallel trenches extending in two perpendicular directions may be formed by depositing a conformal deposition in a first set of parallel trenches, oxidizing the second set of trenches to enable selective deposition in said second set of trenches and then conformally depositing in said second set of trenches. In some embodiments, only one wet anneal, one etch back, and one high density plasma chemical vapor deposition step may be used to fill both sets of trenches.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: January 13, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Enzo Carollo, Marcello Mariani, Sara Marelli, Luca Di Piazza
  • Patent number: 8927441
    Abstract: Methods of forming rutile titanium dioxide comprise exposing a transition metal (such as V, Cr, W, Mn, Ru, Os, Rh, Ir, Pt, Ge, Sn, or Pb) to an atmosphere consisting of oxygen gas (O2) to produce an oxidized transition metal over an unoxidized portion of the transition metal. Rutile titanium dioxide is formed over the oxidized transition metal by atomic layer deposition. The oxidized transition metal is sequentially exposed to a titanium halide precursor and an oxidizer. Other methods include oxidizing a portion of a ruthenium material to ruthenium(IV) oxide using an atmosphere consisting of O2, nitric oxide (NO), or nitrous oxide (N2O); and introducing a gaseous titanium halide precursor and water vapor to the ruthenium(IV) oxide to form rutile titanium dioxide on the ruthenium(IV) oxide by atomic layer deposition. Some methods include exposing transition metal to an atmosphere consisting essentially of O2, NO, and N2O.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: January 6, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Tsai-Yu Huang, Vishwanath Bhat, Vassil Antonov, Chris Carlson
  • Patent number: 8916768
    Abstract: The surface recombination velocity of a silicon sample is reduced by deposition of a thin hydrogenated amorphous silicon or hydrogenated amorphous silicon carbide film, followed by deposition of a thin hydrogenated silicon nitride film. The surface recombination velocity is further decreased by a subsequent anneal. Silicon solar cell structures using this new method for efficient reduction of the surface recombination velocity is claimed.
    Type: Grant
    Filed: April 12, 2006
    Date of Patent: December 23, 2014
    Assignees: Rec Solar Pte. Ltd., Universitetet I Oslo, Instititt for Energiteknikk
    Inventors: Alexander Ulyashin, Andreas Bentzen, Bengt Svensson, Arve Holt, Erik Sauar
  • Patent number: 8901706
    Abstract: A trench structure that in one embodiment includes a trench present in a substrate, and a dielectric layer that is continuously present on the sidewalls and base of the trench. The dielectric layer has a dielectric constant that is greater than 30. The dielectric layer is composed of tetragonal phase hafnium oxide with silicon present in the grain boundaries of the tetragonal phase hafnium oxide in an amount ranging from 3 wt. % to 20 wt. %.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michael P. Chudzik, Bachir Dirahoui, Rishikesh Krishnan, Siddarth A. Krishnan, Oh-jung Kwon, Paul C. Parries, Hongwen Yan
  • Patent number: 8889472
    Abstract: Techniques related to nanocomposite dielectric materials are generally described herein. These techniques may be embodied in apparatuses, systems, methods and/or processes for making and using such material. An example process may include: providing a film having a plurality of nanoparticles and an organic medium; comminuting the film to form a particulate; and applying the particulate to a substrate. The example process may also include providing a nanoparticle film having nanoparticles and voids located between the nanoparticles; contacting the film with a vapor containing an organic material; and curing the organic material to form the nanocomposite dielectric film. Various described techniques may provide nanocomposite dielectric materials with superior nanoparticle dispersion which may result in improved dielectric properties.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: November 18, 2014
    Assignee: Empire Technology Development LLC
    Inventor: Seth Miller
  • Patent number: 8877655
    Abstract: The present invention relates to a process and system for depositing a thin film onto a substrate. One aspect of the invention is depositing a thin film metal oxide layer using atomic layer deposition (ALD).
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: November 4, 2014
    Assignee: ASM America, Inc.
    Inventors: Eric J. Shero, Petri I. Raisanen, Sung-Hoon Jung, Chang-Gong Wang
  • Patent number: 8871656
    Abstract: Methods of depositing initially flowable dielectric films on substrates are described. The methods include introducing silicon-containing precursor to a deposition chamber that contains the substrate. The methods further include generating at least one excited precursor, such as radical nitrogen or oxygen precursor, with a remote plasma system located outside the deposition chamber. The excited precursor is also introduced to the deposition chamber, where it reacts with the silicon-containing precursor in a reaction zone deposits the initially flowable film on the substrate. The flowable film may be treated in, for example, a steam environment to form a silicon oxide film.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: October 28, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Abhijit Basu Mallick, Nitin K. Ingle
  • Patent number: 8872339
    Abstract: A structure includes a substrate, a first supporting member over the substrate, a second supporting member over the substrate, and a layer of material over the substrate and covering the first supporting member and the second supporting member. The first supporting member has a first width, and the second supporting member has a second width. The first supporting member and the second supporting member are separated by a gap region. The first width is at least 10 times the second width, and a gap width of the gap region ranges from 5 to 30 times the second width.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: October 28, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chu Liu, Yi-Shien Mor, Kuei Shun Chen, Yu Lun Liu, Han-Hsun Chang, Shiao-Chian Yeh
  • Patent number: 8871594
    Abstract: According to a process for manufacturing an integrated power device, projections and depressions are formed in a semiconductor body that extend in a first direction and are arranged alternated in succession in a second direction, transversely to the first direction. Further provided are a first conduction region and a second conduction region. The first conduction region and the second conduction region define a current flow direction parallel to the first direction, along the projections and the depressions. To form the projections and the depressions, portions of the semiconductor body that extend in the first direction and correspond to the depressions, are selectively oxidized.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: October 28, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventors: Simone Dario Mariani, Andrea Paleari, Stephane Wen Yung Bach, Paolo Gattari
  • Patent number: 8872272
    Abstract: A method for fabricating a stress enhanced CMOS circuit includes forming a first plurality of MOS transistors at a first pitch and forming a second plurality of MOS transistors at a second pitch. The second pitch is larger than the first pitch. The method further includes depositing a single stress liner overlying the first and second plurality of MOS transistors. The single stress liner is the only stress liner deposited in the fabrication of the stress enhanced CMOS circuit. A stress enhanced CMOS circuit includes a first plurality of MOS transistors formed at a first pitch and a second plurality of MOS transistors formed at a second pitch. The second pitch is larger than the first pitch. The circuit further includes a single stress liner overlying the first and second plurality of MOS transistors. The single stress liner is the only stress liner formed on the stress enhanced CMOS circuit.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: October 28, 2014
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Stefan Flachowsky, Jan Hoentschel
  • Patent number: 8846456
    Abstract: A substrate which has at least one component, such as a semiconductor chip, arranged on it is manufactured from a film made of plastic material laminated onto a surface of the substrate and of the at least one component, where the surface has at least one contact area. First, the film to be laminated onto the surface of the substrate and the at least one component, or a film composite including the film, is arranged in a chamber such that the chamber is split by the film or film composite into a first chamber section and a second chamber section, which is isolated from the first chamber section so as to be gastight. A higher atmospheric pressure is provided or produced in the first chamber section than in the second chamber section; and contact is made between the surface of the substrate arranged in the second chamber section and the at least one component and the film or the film composite, which contact brings about the lamination of the film onto the surface.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: September 30, 2014
    Assignee: Siemens Aktiengesellschaft
    Inventor: Karl Weidner