To Form Insulating Layer Thereon, E.g., For Masking Or By Using Photolithographic Technique (epo) Patents (Class 257/E21.24)

  • Patent number: 10316407
    Abstract: Described herein are compositions and methods using same for forming a silicon-containing film or material such as without limitation a silicon oxide, silicon nitride, silicon oxynitride, a carbon-doped silicon nitride, or a carbon-doped silicon oxide film in a semiconductor deposition process, such as without limitation, a plasma enhanced atomic layer deposition of silicon-containing film.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: June 11, 2019
    Assignee: VERSUM MATERIALS US, LLC
    Inventors: Xinjian Lei, Moo-Sung Kim, Matthew R. MacDonald, Manchao Xiao
  • Patent number: 9953950
    Abstract: A semiconductor structure comprising a first semiconductor structure; a second semiconductor structure; and a silicon-nitride layer configured to bond the first semiconductor structure and second semiconductor structure together. The first semiconductor structure comprises a first wafer; a first dielectric layer; a first interconnect structure; and a first oxide layer. The second semiconductor structure comprises a second wafer; a second dielectric layer; a second interconnect structure; and a second oxide layer. The structure further comprises a first nitride layer residing on a top surface of the first oxide layer formed by a nitridation process of the top surface of the first oxide layer; and a second nitride layer residing on a top surface of the second oxide layer formed by the nitridation process of the top surface of the second oxide layer. Further, the silicon-nitride layer comprises the first nitride layer and the second nitride layer.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: April 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Chih-Chao Yang
  • Patent number: 9947630
    Abstract: A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: April 17, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Jung Yang, Hsien-Wei Chen, Hsien-Ming Tu, Chang-Pin Huang, Yu-Chia Lai, Tung-Liang Shao
  • Patent number: 9666442
    Abstract: A method including forming a pattern on a surface of a substrate, the pattern including one of discrete structures including at least one sidewall defining an oblique angle relative to the surface and discrete structures complemented with a material layer therebetween, the material layer including a volume modified into distinct regions separated by at least one oblique angle relative to the surface; and defining circuit features on the substrate using the pattern, the features having a pitch less than a pitch of the pattern.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: May 30, 2017
    Assignee: Intel Corporation
    Inventors: Fitih M. Cinnor, Charles H. Wallace
  • Patent number: 9613806
    Abstract: A NAND flash memory array is initially patterned by forming a plurality of sidewall spacers according along sides of patterned portions of material. The pattern of sidewall spacers is then used to form a second pattern of hard mask portions including first hard mask portions defined on both sides by sidewall spacers and second hard mask portions defined on only one side by sidewall spacers.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: April 4, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jongsun Sel, Tuan Duc Pham, Mun Pyo Hong
  • Patent number: 9514935
    Abstract: A method of manufacturing a semiconductor device is provided, which enables the film quality to be improved when the film is formed on a substrate at a low temperature, thus forming fine patterns. The method of manufacturing a semiconductor device includes: forming the film on a substrate by alternately supplying at least a source gas and a reactive gas to the substrate while maintaining the substrate at a first temperature by heating; and modifying the film by supplying a modification gas excited by plasma to the substrate with the film formed thereon while naturally cooling the substrate with the film formed thereon to a second temperature without heating the substrate, the second temperature being lower than the first temperature.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: December 6, 2016
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Takaaki Noda, Takeo Hanashima
  • Patent number: 9287348
    Abstract: Devices, methods, and systems for ion trapping are described herein. One device includes a through-silicon via (TSV) and a trench capacitor formed around the TSV.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: March 15, 2016
    Assignee: Honeywell International Inc.
    Inventor: Daniel Youngner
  • Patent number: 9018767
    Abstract: A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Griselda Bonilla, Alfred Grill, Thomas J. Haigh, Jr., Satyanarayana V. Nitta, Son Nguyen
  • Patent number: 9012322
    Abstract: Wet-etch solutions for conductive metals (e.g., copper) and metal nitrides (e.g., tantalum nitride) can be tuned to differentially etch the conductive metals and metal nitrides while having very little effect on nearby oxides (e.g., silicon dioxide hard mask materials), and etching refractory metals (e.g. tantalum) at an intermediate rate. The solutions are aqueous base solutions (e.g., ammonia-peroxide mixture or TMAH-peroxide mixture) with just enough hydrofluoric acid (HF) added to make the solution's pH about 8-10. Applications include metallization of sub-micron logic structures.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: April 21, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Anh Duong, Errol Todd Ryan
  • Patent number: 9013018
    Abstract: A moisture barrier, device or product having a moisture barrier or a method of fabricating a moisture barrier having at least a polymer layer, and interfacial layer, and a barrier layer. The polymer layer may be fabricated from any suitable polymer including, but not limited to, fluoropolymers such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), or ethylene-tetrafluoroethylene (ETFE). The interfacial layer may be formed by atomic layer deposition (ALD). In embodiments featuring an ALD interfacial layer, the deposited interfacial substance may be, but is not limited to, Al2O3, AlSiOx, TiO2, and an Al2O3/TiO2 laminate. The barrier layer associated with the interfacial layer may be deposited by plasma enhanced chemical vapor deposition (PECVD). The barrier layer may be a SiOxNy film.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: April 21, 2015
    Assignees: Beneq Oy, U.S. Department of Energy
    Inventors: Joel W. Pankow, Gary J. Jorgensen, Kent M. Terwilliger, Stephen H. Glick, Nora Isomaki, Kari Harkonen, Tommy Turkulainen
  • Patent number: 8999859
    Abstract: Methods of depositing a film on a substrate surface include surface mediated reactions in which a film is grown over one or more cycles of reactant adsorption and reaction. In one aspect, the method is characterized by intermittent delivery of dopant species to the film between the cycles of adsorption and reaction.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: April 7, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Shankar Swaminathan, Jon Henri, Dennis M. Hausmann, Pramod Subramonium, Mandyam Sriram, Vishwanathan Rangarajan, Kirthi K. Kattige, Bart K. van Schravendijk, Andrew J. McKerrow
  • Patent number: 8994127
    Abstract: Embodiments related to semiconductor manufacturing and semiconductor devices with semiconductor structure are described and depicted.
    Type: Grant
    Filed: November 24, 2011
    Date of Patent: March 31, 2015
    Assignee: Infineon Technologies AG
    Inventors: Thoralf Kautzsch, Boris Binder, Torsten Helm, Stefan Kolb, Marc Probst, Uwe Rudolph
  • Patent number: 8993453
    Abstract: A method for fabricating a nonvolatile charge trap memory device and the device are described. In one embodiment, the method includes providing a substrate in an oxidation chamber, wherein the substrate comprises a first exposed crystal plane and a second exposed crystal plane, and wherein the crystal orientation of the first exposed crystal plane is different from the crystal orientation of the second exposed crystal plane. The substrate is then subjected to a radical oxidation process to form a first portion of a dielectric layer on the first exposed crystal plane and a second portion of the dielectric layer on the second exposed crystal plane, wherein the thickness of the first portion of the dielectric layer is approximately equal to the thickness of the second portion of the dielectric layer.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 31, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Jeong Byun, Sagy Levy
  • Patent number: 8993708
    Abstract: A carbazole polymer including a repeating unit represented by Formula 1 and having excellent one electron oxidation-state stability, wherein, in Formula 1, R1-R4 each independently represents an alkyl group having 1-60 carbon atoms, a haloalkyl group having 1-60 carbon atoms, or similar, Cz represents a divalent group including a carbazole skeleton represented by Formula 2, and Ar represents a divalent aromatic ring or similar; wherein, in Formula 2, R5 represents a hydrogen atom, an alkyl group having 1-60 carbon atoms, or similar, R6-R11 each independently represents a hydrogen atom, a halogen atom, or similar, and m represents an integer 1-10.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: March 31, 2015
    Assignee: Nissan Chemical Industries, Ltd.
    Inventors: Yuki Shibano, Takuji Yoshimoto
  • Patent number: 8980759
    Abstract: A method of forming a slanted field plate including forming epitaxy for a FET on a substrate, forming a wall near a drain of the FET, the wall comprising a first negative tone electron-beam resist (NTEBR), depositing a dielectric over the epitaxy and the wall, the wall causing the dielectric to have a step near the drain of the FET, depositing a second NTEBR over the dielectric, wherein surface tension causes the deposited second NTEBR to have a slanted top surface between the step and a source of the FET, etching anisotropically vertically the second NTEBR and the dielectric to remove the second NTEBR and to transfer a shape of the slanted top surface to the dielectric, and forming a gatehead comprising metal on the dielectric between the step and the source of the FET, wherein the gatehead forms a slanted field plate.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: March 17, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Andrea Corrion, Joel C. Wong, Keisuke Shinohara, Miroslav Micovic, Ivan Milosavljevic, Dean C. Regan, Yan Tang
  • Patent number: 8975194
    Abstract: Disclosed a method for manufacturing an oxide layer, applicable to a manufacture procedure of a field oxide layer of a CMOS transistor in the field of semiconductor manufacturing, the method includes: injecting a first gas satisfying a first predetermined condition into a processing furnace in which a first CMOS transistor semi-finished product formed with an N-well and a P-well is placed, and dry-oxidizing the first CMOS transistor semi-finished product into a second CMOS transistor semi-finished product; and injecting a second gas satisfying a second predetermined condition different from the first predetermined condition into the processing furnace, and wet-oxidizing the second CMOS transistor semi-finished product into a third CMOS transistor semi-finished product.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: March 10, 2015
    Assignees: Peking University Founder Group Co., Ltd., Founder Microelectronics International Co., Ltd.
    Inventor: Jinyuan Chen
  • Patent number: 8962486
    Abstract: The present invention provides a method of forming an opening on a semiconductor substrate. First, a substrate is provided. Then a dielectric layer and a cap layer are formed on the substrate. A ratio of a thickness of the dielectric layer and a thickness of the cap layer is substantially between 15 and 1.5. Next, a patterned boron nitride layer is formed on the cap layer. Lastly, an etching process is performed by using the patterned hard mask as a mask to etch the cap layer and the dielectric layer so as to form an opening in the cap layer and the dielectric layer.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: February 24, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Po-Chun Chen
  • Patent number: 8940645
    Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes subjecting a substrate to a first oxidation process to form a tunnel oxide layer overlying a polysilicon channel, and forming over the tunnel oxide layer a multi-layer charge storing layer comprising an oxygen-rich, first layer comprising a nitride, and an oxygen-lean, second layer comprising a nitride on the first layer. The substrate is then subjected to a second oxidation process to consume a portion of the second layer and form a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The stoichiometric composition of the first layer results in it being substantially trap free, and the stoichiometric composition of the second layer results in it being trap dense. The second oxidation process can comprise a plasma oxidation process or a radical oxidation process using In-Situ Steam Generation.
    Type: Grant
    Filed: July 1, 2012
    Date of Patent: January 27, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Sagy Levy, Jeong Byun
  • Patent number: 8936957
    Abstract: The present disclosure discloses a method of manufacturing a light-emitting device comprising the steps of providing a light-emitting wafer having a semiconductor stacked structure and an alignment mark, sensing the alignment mark, and separating the light-emitting wafer into a plurality of light-emitting diodes and removing the alignment mark accordingly.
    Type: Grant
    Filed: December 24, 2013
    Date of Patent: January 20, 2015
    Assignee: Epistar Corporation
    Inventor: Tsung-Hsien Yang
  • Patent number: 8932935
    Abstract: A three dimensional shallow trench isolation structure including sets of parallel trenches extending in two perpendicular directions may be formed by depositing a conformal deposition in a first set of parallel trenches, oxidizing the second set of trenches to enable selective deposition in said second set of trenches and then conformally depositing in said second set of trenches. In some embodiments, only one wet anneal, one etch back, and one high density plasma chemical vapor deposition step may be used to fill both sets of trenches.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: January 13, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Enzo Carollo, Marcello Mariani, Sara Marelli, Luca Di Piazza
  • Patent number: 8927441
    Abstract: Methods of forming rutile titanium dioxide comprise exposing a transition metal (such as V, Cr, W, Mn, Ru, Os, Rh, Ir, Pt, Ge, Sn, or Pb) to an atmosphere consisting of oxygen gas (O2) to produce an oxidized transition metal over an unoxidized portion of the transition metal. Rutile titanium dioxide is formed over the oxidized transition metal by atomic layer deposition. The oxidized transition metal is sequentially exposed to a titanium halide precursor and an oxidizer. Other methods include oxidizing a portion of a ruthenium material to ruthenium(IV) oxide using an atmosphere consisting of O2, nitric oxide (NO), or nitrous oxide (N2O); and introducing a gaseous titanium halide precursor and water vapor to the ruthenium(IV) oxide to form rutile titanium dioxide on the ruthenium(IV) oxide by atomic layer deposition. Some methods include exposing transition metal to an atmosphere consisting essentially of O2, NO, and N2O.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: January 6, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Tsai-Yu Huang, Vishwanath Bhat, Vassil Antonov, Chris Carlson
  • Patent number: 8916768
    Abstract: The surface recombination velocity of a silicon sample is reduced by deposition of a thin hydrogenated amorphous silicon or hydrogenated amorphous silicon carbide film, followed by deposition of a thin hydrogenated silicon nitride film. The surface recombination velocity is further decreased by a subsequent anneal. Silicon solar cell structures using this new method for efficient reduction of the surface recombination velocity is claimed.
    Type: Grant
    Filed: April 12, 2006
    Date of Patent: December 23, 2014
    Assignees: Rec Solar Pte. Ltd., Universitetet I Oslo, Instititt for Energiteknikk
    Inventors: Alexander Ulyashin, Andreas Bentzen, Bengt Svensson, Arve Holt, Erik Sauar
  • Patent number: 8901706
    Abstract: A trench structure that in one embodiment includes a trench present in a substrate, and a dielectric layer that is continuously present on the sidewalls and base of the trench. The dielectric layer has a dielectric constant that is greater than 30. The dielectric layer is composed of tetragonal phase hafnium oxide with silicon present in the grain boundaries of the tetragonal phase hafnium oxide in an amount ranging from 3 wt. % to 20 wt. %.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michael P. Chudzik, Bachir Dirahoui, Rishikesh Krishnan, Siddarth A. Krishnan, Oh-jung Kwon, Paul C. Parries, Hongwen Yan
  • Patent number: 8889472
    Abstract: Techniques related to nanocomposite dielectric materials are generally described herein. These techniques may be embodied in apparatuses, systems, methods and/or processes for making and using such material. An example process may include: providing a film having a plurality of nanoparticles and an organic medium; comminuting the film to form a particulate; and applying the particulate to a substrate. The example process may also include providing a nanoparticle film having nanoparticles and voids located between the nanoparticles; contacting the film with a vapor containing an organic material; and curing the organic material to form the nanocomposite dielectric film. Various described techniques may provide nanocomposite dielectric materials with superior nanoparticle dispersion which may result in improved dielectric properties.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: November 18, 2014
    Assignee: Empire Technology Development LLC
    Inventor: Seth Miller
  • Patent number: 8877655
    Abstract: The present invention relates to a process and system for depositing a thin film onto a substrate. One aspect of the invention is depositing a thin film metal oxide layer using atomic layer deposition (ALD).
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: November 4, 2014
    Assignee: ASM America, Inc.
    Inventors: Eric J. Shero, Petri I. Raisanen, Sung-Hoon Jung, Chang-Gong Wang
  • Patent number: 8871656
    Abstract: Methods of depositing initially flowable dielectric films on substrates are described. The methods include introducing silicon-containing precursor to a deposition chamber that contains the substrate. The methods further include generating at least one excited precursor, such as radical nitrogen or oxygen precursor, with a remote plasma system located outside the deposition chamber. The excited precursor is also introduced to the deposition chamber, where it reacts with the silicon-containing precursor in a reaction zone deposits the initially flowable film on the substrate. The flowable film may be treated in, for example, a steam environment to form a silicon oxide film.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: October 28, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Abhijit Basu Mallick, Nitin K. Ingle
  • Patent number: 8872272
    Abstract: A method for fabricating a stress enhanced CMOS circuit includes forming a first plurality of MOS transistors at a first pitch and forming a second plurality of MOS transistors at a second pitch. The second pitch is larger than the first pitch. The method further includes depositing a single stress liner overlying the first and second plurality of MOS transistors. The single stress liner is the only stress liner deposited in the fabrication of the stress enhanced CMOS circuit. A stress enhanced CMOS circuit includes a first plurality of MOS transistors formed at a first pitch and a second plurality of MOS transistors formed at a second pitch. The second pitch is larger than the first pitch. The circuit further includes a single stress liner overlying the first and second plurality of MOS transistors. The single stress liner is the only stress liner formed on the stress enhanced CMOS circuit.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: October 28, 2014
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Stefan Flachowsky, Jan Hoentschel
  • Patent number: 8872339
    Abstract: A structure includes a substrate, a first supporting member over the substrate, a second supporting member over the substrate, and a layer of material over the substrate and covering the first supporting member and the second supporting member. The first supporting member has a first width, and the second supporting member has a second width. The first supporting member and the second supporting member are separated by a gap region. The first width is at least 10 times the second width, and a gap width of the gap region ranges from 5 to 30 times the second width.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: October 28, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chu Liu, Yi-Shien Mor, Kuei Shun Chen, Yu Lun Liu, Han-Hsun Chang, Shiao-Chian Yeh
  • Patent number: 8871594
    Abstract: According to a process for manufacturing an integrated power device, projections and depressions are formed in a semiconductor body that extend in a first direction and are arranged alternated in succession in a second direction, transversely to the first direction. Further provided are a first conduction region and a second conduction region. The first conduction region and the second conduction region define a current flow direction parallel to the first direction, along the projections and the depressions. To form the projections and the depressions, portions of the semiconductor body that extend in the first direction and correspond to the depressions, are selectively oxidized.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: October 28, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventors: Simone Dario Mariani, Andrea Paleari, Stephane Wen Yung Bach, Paolo Gattari
  • Patent number: 8846456
    Abstract: A substrate which has at least one component, such as a semiconductor chip, arranged on it is manufactured from a film made of plastic material laminated onto a surface of the substrate and of the at least one component, where the surface has at least one contact area. First, the film to be laminated onto the surface of the substrate and the at least one component, or a film composite including the film, is arranged in a chamber such that the chamber is split by the film or film composite into a first chamber section and a second chamber section, which is isolated from the first chamber section so as to be gastight. A higher atmospheric pressure is provided or produced in the first chamber section than in the second chamber section; and contact is made between the surface of the substrate arranged in the second chamber section and the at least one component and the film or the film composite, which contact brings about the lamination of the film onto the surface.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: September 30, 2014
    Assignee: Siemens Aktiengesellschaft
    Inventor: Karl Weidner
  • Patent number: 8835233
    Abstract: A method for fabricating a multiple-workfunction FinFET structure includes depositing a first workfunction material in a layer in a plurality of trenches of the FinFET structure and etching the first workfunction material layer so as to completely remove the first workfunction material layer from all but a first trench of the plurality of trenches. Further, the method includes depositing a second workfunction material in a layer in the plurality of trenches and etching the second workfunction material layer so as to completely remove the second workfunction material layer from all but a second trench of the plurality of trenches. Still further, the method includes depositing a third workfunction material in a layer in the plurality of trenches.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: September 16, 2014
    Assignee: GlobalFoundries, Inc.
    Inventors: Andy C. Wei, Akshey Sehgal, Bamidele S. Allimi
  • Patent number: 8810038
    Abstract: A semiconductor device includes: a board; a power wire formed on the board; a signal wire formed on the board; a ground wire formed on the board; an insulating layer covering the signal wire, the power wire and the ground wire; and a metal film formed on the insulating layer, wherein a thickness of the insulating layer covering the power wire is different from a thickness of the insulating layer covering the signal wire, and the metal film is connected to a ground potential.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: August 19, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Takafumi Shimada, Atsushi Kikuchi
  • Patent number: 8802490
    Abstract: Techniques related to nanocomposite dielectric materials are generally described herein. These techniques may be embodied in apparatuses, systems, methods and/or processes for making and using such material. An example process may include: providing a film having a plurality of nanoparticles and an organic medium; comminuting the film to form a particulate; and applying the particulate to a substrate. The example process may also include providing a nanoparticle film having nanoparticles and voids located between the nanoparticles; contacting the film with a vapor containing an organic material; and curing the organic material to form the nanocomposite dielectric film. Various described techniques may provide nanocomposite dielectric materials with superior nanoparticle dispersion which may result in improved dielectric properties.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: August 12, 2014
    Assignee: Empire Technology Development LLC
    Inventor: Seth Miller
  • Patent number: 8791003
    Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate and forming a gate structure on the semiconductor substrate. The gate includes a high-k dielectric material. In the method, a fluorine-containing liquid is contacted with the high-k dielectric material and fluorine is incorporated into the high-k dielectric material.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: July 29, 2014
    Assignee: Globalfoundries, Inc.
    Inventors: Dina Triyoso, Elke Erben, Robert Binder
  • Patent number: 8785325
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming first and second cores on a processed material, forming a covering material having a stacked layer includes first and second layers, the covering material covering an upper surface and a side surface of the first and second cores, removing the second layer covering the first core, forming a first sidewall mask having the first layer on the side surface of the first core and a second sidewall mask having the first and second layers on the side surface of the second core by etching the covering material, removing the first and second cores, and forming first and second patterns having different width in parallel by etching the processed material in condition of using the first and second sidewall masks.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: July 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Gaku Sudo
  • Patent number: 8779600
    Abstract: A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: July 15, 2014
    Assignee: International Business Machines Corporation
    Inventors: Son Van Nguyen, Griselda Bonilla, Alfred Grill, Thomas J. Haigh, Jr., Satyanarayana V. Nitta
  • Patent number: 8778807
    Abstract: A method of forming an integrated circuit structure includes providing a substrate; forming a first hard mask layer over the substrate; forming a second hard mask layer over the first hard mask layer; patterning the second hard mask layer to form a hard mask; and, after the step of patterning the second hard mask layer, baking the substrate, the first hard mask layer, and the hard mask. After the step of baking, a spacer layer is formed, which includes a first portion on a top of the hard mask, and a second portion and a third portion on opposite sidewalls of the hard mask. The method further includes removing the first portion of the spacer layer; removing the hard mask; and using the second portion and the third portion of the spacer layer as masks to pattern the first hard mask layer.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: July 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yu Lai, Cheng-Ta Wu, Neng-Kuo Chen, Cheng-Yuan Tsai
  • Patent number: 8778816
    Abstract: Methods for preparing a substrate for a subsequent film formation process are described. Methods for preparing a substrate for a subsequent film formation process, without immersion in an aqueous solution, are also described. A process is described that includes disposing a substrate into a process chamber, the substrate having a thermal oxide surface with substantially no reactive surface terminations. The thermal oxide surface is exposed to a partial pressure of water below the saturated vapor pressure at a temperature of the substrate to convert the dense thermal oxide with substantially no reactive surface terminations to a surface with hydroxyl surface terminations. This can occur in the presence of a Lewis base such as ammonia.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: July 15, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Tatsuya E. Sato, David Thompson, Jeffrey W. Anthis, Vladimir Zubkov, Steven Verhaverbeke, Roman Gouk, Maitreyee Mahajani, Patricia M. Liu, Malcolm J. Bevan
  • Patent number: 8778779
    Abstract: A method for producing semiconductor device includes: performing first, second and third exposures of a photoresist film formed on a semiconductor wafer via a mask; wherein: first, second and third shot regions respectively defined by the first, second and third exposures are aligned in a first direction; the mask has a shot region including a peripheral scribe region having a first and second side crossing the first direction; the photoresist film is of positive type, a first pattern is formed as a light shielding pattern disposed on the first side, and a second pattern is formed as a light transmitting region disposed on the second side; the first and second exposures are performed in such a manner that the first and second patterns do not overlap each other; and the second and third exposures are performed in such a manner that the first and second patterns overlap each other.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: July 15, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Mitsufumi Naoe
  • Patent number: 8759232
    Abstract: The present disclosure provides manufacturing techniques and semiconductor devices in which performance of P-channel transistors may be enhanced on the basis of a stress mechanism that involves the deposition of a dielectric bi-layer system. Contrary to conventional strategies, an additional pre-treatment may be performed prior to the deposition of an adhesion layer in a plasma-free process atmosphere, thereby enabling a reduced thickness of the adhesion layer and a higher internal stress level of the subsequent top layer.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: June 24, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Joerg Hohage, Hartmut Ruelke, Ralf Richter
  • Patent number: 8753984
    Abstract: A method of forming a silicon nitride film on the surface of an object to be processed, the method including forming a seed layer functioning as a seed of the silicon nitride film on the surface of the object to be processed by using at least an aminosilane-based gas, prior to forming the silicon nitride film on the surface of the object to be processed.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: June 17, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Hiroki Murakami, Yosuke Watanabe, Kazuhide Hasebe
  • Patent number: 8754400
    Abstract: A first nanoscale self-aligned self-assembled nested line structure having a sublithographic width and a sublithographic spacing and running along a first direction is formed from first self-assembling block copolymers within a first layer. The first layer is filled with a filler material and a second layer is deposited above the first layer containing the first nanoscale nested line structure. A second nanoscale self-aligned self-assembled nested line structure having a sublithographic width and a sublithographic spacing and running in a second direction is formed from second self-assembling block copolymers within the second layer. The composite pattern of the first nanoscale nested line structure and the second nanoscale nested line structure is transferred into an underlayer beneath the first layer to form an array of structures containing periodicity in two directions.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Timothy J. Dalton, Bruce B. Doris, Ho-Cheol Kim, Carl J. Radens
  • Patent number: 8741761
    Abstract: Methods of manufacturing three-dimensional semiconductor devices that may include forming a first spacer on a sidewall inside a first opening formed in a first stack structure, forming a sacrificial filling pattern on the spacer to fill the first opening, forming a second stack structure including a second opening exposing the sacrificial filling pattern on the first stack structure, forming a second spacer on a sidewall inside the second opening, removing the sacrificial filling pattern and removing the first spacer and the second spacer.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: June 3, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaegoo Lee, Byungkwan You, Youngwoo Park, Kwang Soo Seol
  • Patent number: 8741396
    Abstract: An amorphous carbon film, which has excellent etching resistance and is capable of reducing reflectance when a resist film is exposed to light, is form. A method for manufacturing a semiconductor device includes forming an object film to be etched on a wafer, supplying a process gas containing a CO gas and an N2 gas into a processing container, forming an amorphous carbon nitride film from the supplied CO gas and N2 gas, forming a silicon oxide film on the amorphous carbon nitride film, forming an ArF resist film on the silicon oxide film, patterning the ArF resist film, etching the silicon oxide film by using the ArF resist film as a mask, etching the amorphous carbon nitride film by using the silicon oxide film as a mask, and etching the object film to be etched by using the amorphous carbon nitride film as a mask.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: June 3, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Hiraku Ishikawa, Eiichi Nishimura
  • Patent number: 8735304
    Abstract: A method of forming a dielectric film including a zirconium oxide film includes: forming a zirconium oxide film on a substrate to be processed by supplying a zirconium material and an oxidant, the zirconium material including a Zr compound which includes a cyclopentadienyl ring in a structure, and forming a titanium oxide film on the zirconium oxide film by supplying a titanium material and an oxidant, the titanium material including a Ti compound which includes a cyclopentadienyl ring in a structure.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: May 27, 2014
    Assignees: Elpida Memory Inc., Tokyo Electron Limited
    Inventors: Yuichiro Morozumi, Takuya Sugawara, Koji Akiyama, Shingo Hishiya, Toshiyuki Hirota, Takakazu Kiyomura
  • Patent number: 8729626
    Abstract: A semiconductor device may include, but is not limited to: a semiconductor structure extending upwardly; a first insulating film covering at least a side surface of the semiconductor structure; a gate electrode extending upwardly, the gate electrode being adjacent to the first insulating film; and an insulating structure extending upwardly, the insulating structure being adjacent to the gate electrode.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: May 20, 2014
    Inventors: Yu Kosuge, Yasuhiko Ueda
  • Patent number: 8728955
    Abstract: A method of depositing a film on a substrate surface includes providing a substrate in a reaction chamber; selecting a silicon-containing reactant from a precursor group consisting of di-tert-butyl diazidosilane, bis(ethylmethylamido)silane, bis(diisopropylamino)silane, bis(tert-butylhydrazido)diethylsilane, tris(dimethylamido)silylazide, tris(dimethylamido)silylamide, ethylsilicon triazide, diisopropylaminosilane, and hexakis(dimethylamido)disilazane; introducing the silicon-containing reactant in vapor phase into the reaction chamber under conditions allowing the silicon-containing reactant to adsorb onto the substrate surface; introducing a second reactant in vapor phase into the reaction chamber while the silicon-containing reactant is adsorbed on the substrate surface, and wherein the second reactant is introduced without first sweeping the silicon-containing reactant out of the reaction chamber; and exposing the substrate surface to plasma to drive a reaction between the silicon-containing reactant and
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: May 20, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Adrien LaVoie, Mark J. Saly, Daniel Moser, Rajesh Odedra, Ravi Konjolia
  • Patent number: 8722841
    Abstract: There is provided a resist underlayer film having heat resistance that is used for a lithography process in the production of semiconductor devices, and a high refractive index film having transparency that is used for an electronic device. A polymer comprising a unit structure of Formula (1): wherein each of R1, R2, R3, and R5 may be a hydrogen atom, R4 may be phenyl group or naphthyl group. A resist underlayer film forming composition comprising the polymer, and a resist underlayer film formed from the composition. A high refractive index film forming composition comprising the polymer, and a high refractive index film formed from the composition.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: May 13, 2014
    Assignee: Nissan Chemical Industries, Ltd.
    Inventors: Daigo Saito, Hiroaki Okuyama, Hideki Musashi, Tetsuya Shinjo, Keisuke Hashimoto
  • Publication number: 20140117511
    Abstract: A passivation layer and a method of making a passivation layer are disclosed. In one embodiment the method for manufacturing a passivation layer includes depositing a first silicon based dielectric layer on a workpiece, the first silicon based dielectric layer comprising nitrogen, and depositing in-situ a second silicon based dielectric layer on the first silicon based dielectric layer, the second dielectric layer comprising oxygen.
    Type: Application
    Filed: October 30, 2012
    Publication date: May 1, 2014
    Applicant: Infineon Technologies AG
    Inventors: Kurt Matoy, Hubert Maier, Christian Krenn, Elfriede Kraxner Wellenzohn, Helmut Schoenherr, Juergen Steinbrenner, Markus Kahn, Fister Schlemitz Silvana, Christoph Brunner, Herbert Gietler, Uwe Hoeckele
  • Publication number: 20140106571
    Abstract: A plasma processing apparatus includes a process chamber housing defining a process chamber, a platen positioned in the process chamber for supporting a workpiece, a source configured to generate plasma in the process chamber, and a biasing system. The biasing system is configured to bias the platen to attract ions from the plasma towards the workpiece during a first processing time interval and configured to bias the platen to repel ions from the platen towards interior surfaces of the process chamber housing during a cleaning time interval. The cleaning time interval is separate from the first processing time interval and occurring after the first processing time interval.
    Type: Application
    Filed: October 11, 2012
    Publication date: April 17, 2014
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Bon-Woong Koo, Richard M. White