METHODS OF MANUFACTURING SEMICONDUCTOR STRUCTURES AND SEMICONDUCTOR STRUCTURES OBTAINED BY SUCH METHODS
In preferred embodiments, this invention provides a semiconductor structure that has a semi-conducting support, an insulating layer arranged on a portion of the support and a semi-conducting superficial layer arranged on the insulating layer. Electronic devices can be formed in the superficial layer and also in the exposed portion of the semi-conducting bulk region of the substrate not covered by the insulating layer. The invention also provides methods of fabricating such semiconductor structures which, starting from a substrate that includes a semi-conducting superficial layer arranged on a continuous insulating layer both of which being arranged on a semi-conducting support, by transforming at least one selected region of a substrate so as to form an exposed semi-conducting bulk region of the substrate.
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The present invention relates to methods of manufacturing semiconductor devices in a substrate comprising a semi-conducting superficial layer arranged on an insulating layer, both of which are arranged on a partially exposed semi-conducting bulk region. The present invention also relates to substrates manufactured by such methods.
BACKGROUND OF THE INVENTIONMicroelectronic devices are typically manufactured on either bulk semi-conductor substrates or on SOI substrates (Silicon on Insulator). It has also been proposed to use composite (or patterned) substrates comprising bulk areas and SOI areas. See, e.g., U.S. Pat. No. 6,955,971. The fabrication of such patterned substrates is generally difficult because it requires formation of local areas of a buried oxide next to bulk areas. In the case of wafer bonding methods, such local oxide areas can be formed either on the top wafer or the base wafer, and can give rise to so-called “dishing” problems. In the case of a SIMOX type methods (Separation by Implanted Oxygen), such local oxide areas are commonly formed in the original wafer, but the differential thermal expansion of silicon oxides versus silicon gives rise to stress, etc.
SUMMARY OF THE INVENTIONThe invention provides fabrication methods for patterned substrates having satisfactory crystalline quality, and the substrates fabricated by the provided methods.
In preferred embodiments, methods of the invention include providing a substrate comprising a semi-conducting support, a continuous insulating layer arranged on the support and a semi-conducting superficial layer arranged on the insulating layer; transforming the superficial layer and the insulating layer in at least one selected region of the substrate so as to form an exposed semi-conducting bulk region of the substrate; then forming electronic devices in or on the exposed semi-conducting bulk region of the substrate and in or on the superficial layer.
Substrates (or semiconductor structures) of the invention include a substrate comprising a semi-conducting support, an insulating layer disposed on a first face of the semi-conducting support and a semi-conducting superficial layer disposed on the insulating layer, wherein the first face of the semi-conducting support comprises an exposed semi-conducting bulk region.
Other features and advantages of the invention will become apparent from the following description and the appended drawings:
The preferred embodiments and particular examples described herein should be seen as examples of the scope of the invention, but not as limiting the present invention. The scope of the present invention should be determined with reference to the claims.
Methods of these embodiments comprise providing a substrate of
Support 1 and semi-conducting superficial layer 3 can comprise the same semi-conducting material, or different semi-conducting materials, or the same or different semi-conducting materials with different crystalline orientations. Electronic devices 6 formed respectively in exposed semi-conducting bulk region 12 of the substrate and in superficial layer 3 can be thus formed in different materials. The preferable semi-conducting materials for support 1 and superficial layer 3 are e.g. silicon, germanium, silicon-germanium, or III-V-type semi-conducting materials such as InP, GaN, or GaAs, optionally in a strained state. For instance, germanium could be chosen for PMOS transistors, and III-V-type semi-conducting materials for NMOS transistors, whereas silicon can be used for input-output-circuits and analog circuits.
A substrate with additional insulating layer 10 and additional semi-conducting superficial layer 11 is preferably manufactured by a SmartCut™. Then the following four layers are then removed in selected region 4 of the substrate: additional insulating layer 10, additional semi-conducting superficial layer 11, superficial layer 3 and insulating layer 2. In region 5 only additional insulating layer 10 and additional semi-conducting superficial layer 11 are removed. No layers are removed from additional selected region 15 so that electronic devices can be formed therein.
Generally, devices 6 (e.g., in
Height offset 9, the distance between the surface of exposed semi-conducting bulk region 12 of the substrate and the surface of superficial layer 3, is preferably less than the depth of focus of a lithography exposure corresponding to a predetermined image resolution made by image forming apparatus 8 along an axis Z. Therefore, a single lithography exposure can be sufficiently focused to at least the predetermined image resolution simultaneously on both exposed semi-conducting bulk region 12 of the substrate and on superficial layer 3. Accordingly, for formation of electronic devices in (or on) both of these regions, it is possible and advantageous either to carry out a single lithographic exposure or to carry out simultaneously two lithographic exposures. The depth of focus depends on the image forming apparatus used and on the resolution required by the process applied.
Height offset 9 is preferably less than the depth of focus of the selected lithography tool while taking into account the required image resolution for forming the smallest pattern. Specifically, height offset 9 is preferably less than 100 nm, or more preferably less than 50 nm. Indeed, when a higher precision is needed for small structures, e.g., for short gate lengths, the depth of focus is preferably also small and the height offset should thus preferably be no larger than the depth of focus. When a lower precision is suitable, a height offset of less than 100 nm might be sufficient.
For example,
For example, memory devices can be formed in superficial layer 3 (and possibly in additional superficial layer 11 in
This approach is not limited to the particular stacks of layers 1, 2, 3 and can also be implemented with any other substrates having several different levels, and in which electronic devices should be formed. This is for instance the case with a bulk substrate having two or more different surface levels.
Alternatively, two of more distinct lithography steps can be performed, especially when height offset 9 (
Following the lithography step or steps, formation of electronic devices typically further comprises one or more etching steps and/or one or more implantation steps. In preferred embodiments, the etching steps, as shown by arrow 17 in
In particular, the etching and/or implantation steps are preferably carried out simultaneously in embodiments where insulating layer 2 has a thickness less than 25 nm (more preferably between 2 nm and 25 nm, and even more preferably between 5 nm and 15 nm), and where superficial layer 3 has a thickness preferably less than 50 nm (more preferably between 5 nm and 50 nm, and even more preferably between 10 nm and 40 nm). Prior lithography steps are preferably also carried out simultaneously when the above mentioned of depth of focus conditions are satisfied.
In other embodiments, distinct etching and/or distinct implantation steps can be carried out for exposed bulk region 12 and for superficial layer 3. In still other embodiments, the lithography, etching, and/or implantation can be carried out in any combination of separate and distinct or simultaneous steps for exposed semi-conducting bulk region 12 and superficial layer 3.
Claims
1. A method of manufacturing a semiconductor device comprising:
- providing a substrate comprising a semi-conducting bulk support, a continuous insulating layer arranged on the support, and a semi-conducting superficial layer arranged on the insulating layer;
- transforming the superficial layer and the insulating layer so as to expose a selected region of the semi-conducting bulk support; and
- simultaneously forming electronic devices in or on the exposed region of the support and in or on the superficial layer.
2. The method of claim 1 wherein the step of transforming comprises removing the superficial layer and the insulating layer in the selected region.
3. The method of claim 1 wherein the insulating layer comprises silicon oxide, and wherein the step of transforming comprises dissolution of the insulating layer in the selected region.
4. The method of claim 1 wherein the step of forming comprises a lithography step during which selected portions of the exposed semi-conducting bulk region and of the superficial layer are irradiated by an image forming apparatus.
5. The method of claim 4 wherein the image forming apparatus has a depth of focus along an axis perpendicular to the substrate that corresponds to a predetermined image resolution, and wherein a height offset between the exposed semi-conducting bulk region and the superficial layer is less than the depth of focus.
6. The method of claim 5 wherein the height offset is less than 50 nm.
7. The method of claim 5 wherein the height offset corresponds to a combined thickness of the superficial layer and the insulating layer.
8. The method of claim 4 wherein the step of forming further comprises:
- etching of the exposed semi-conducting bulk region and the superficial layer; and
- implanting into the exposed semi-conducting bulk region and the superficial layer.
9. The method of claim 1 wherein the semi-conducting bulk support comprises an epitaxial surface layer with a density of crystalline defects of a size greater than 10 nm of less than 103/cm3.
10. The method of claim 1 wherein the substrate further comprises an additional insulating layer disposed on a surface of the superficial layer so as to cover an additional selected region of the surface of the superficial layer while leaving exposed another region of the surface of the superficial layer and an additional semi-conducting superficial layer disposed on the additional insulating layer.
11. The method of claim 10 wherein forming further comprises forming electronic devices simultaneously in or on the exposed semi-conducting bulk region, the superficial layer, and the additional superficial layer.
12. A semiconductor a substrate structure comprising:
- a semi-conducting bulk support;
- an insulating layer disposed on a surface of the semi-conducting bulk support so as to cover a selected region of the surface of the semi-conducting bulk support while leaving exposed another region of the surface of the semi-conducting bulk support; and
- a semi-conducting superficial layer disposed on the insulating layer.
13. The semiconductor structure of claim 12 further comprising electronic devices formed in the superficial layer and in the exposed region of the semi-conducting bulk support.
14. The semiconductor structure of claim 12 further comprising:
- an additional insulating layer disposed on a surface of the superficial layer so as to cover an additional selected region of the surface of the superficial layer while leaving exposed another region of the surface of the superficial layer; and
- an additional semi-conducting superficial layer disposed on the additional insulating layer.
15. The semiconductor structure of claim 14 further comprising electronic devices formed in the additional superficial layer, in the superficial layer, and in the exposed region of the semi-conducting bulk support.
16. The semiconductor structure of claim 12 wherein a combined thickness of the superficial layer and the insulating layer is less 50 nm.
17. The semiconductor structure of claim 12 wherein the semi-conducting support comprises an epitaxial surface layer with a density of crystalline defects of a size greater than 10 nm of less than 103/cm3.
Type: Application
Filed: May 18, 2009
Publication Date: Feb 24, 2011
Applicant: S.O.I Tec Silicon on Insulator Technologies (Bernin)
Inventors: Bich-Yen Nguyen (Austin, TX), Carlos Mazure (Bernin)
Application Number: 12/989,532
International Classification: H01L 21/30 (20060101); H01L 29/02 (20060101);