Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a first dielectric layer formed over the substrate. The semiconductor device structure also includes a first movable membrane formed over the first dielectric layer. In addition, the first movable membrane has a first corrugated portion and a first edge portion connecting to the first corrugated portion. The semiconductor device structure further includes a second dielectric layer formed over the first movable membrane. In addition, the first edge portion is sandwiched between the first dielectric layer and the second dielectric layer, the first corrugated portion is partially sandwiched between the first dielectric layer and the second dielectric layer and is partially exposed by a cavity, and a bottom surface of the first corrugated portion is lower than a bottom surface of the first edge portion.

Abstract: The present application provides a color film substrate, a display device, and a color film substrate fabricating method. The color film substrate comprises a display region and a non-display region, wherein the color film substrate in the non-display region comprises: a base; and a photoresist layer disposed on the base; a planarization layer disposed on a side of the photoresist layer away from the base; a support layer disposed on a side of the planarization layer away from the base; wherein a total thickness of the photoresist layer, the planarization layer, and the support layer is greater than or equal to a first thickness threshold.

Abstract: Alignment of devices formed on substrates that are to be bonded may be achieved through the use of scribe lines between the devices, where the scribe lines progressively increase or decrease in size from a center to an edge of one or more of the substrates to compensate for differences in the thermal expansion rates of the substrates. The devices on the substrates are brought into alignment as the substrates are heated during a bonding operation due to the progressively increased or decreased sizes of the scribe lines. The scribe lines may be arranged in a single direction in a substrate to compensate for thermal expansion along a single axis of the substrate or may be arranged in a plurality of directions to compensate for actinomorphic thermal expansion.

Abstract: Speed of plasma etching is regulated in regions prone to over-etching by providing an etch resistant structure, such as a metal saw bow, in the region. By adjusting dimensions, such as the length and width of the saw bow legs and an area defined by the saw bow legs, as well as a shape of the etch region through techniques such as chamfering, plasma etch speed in the region can be controlled with an intent to match the speed of etching in non-over-etched regions.

Abstract: An alignment structure is provided. The alignment structure includes a substrate, an alignment portion, and an extension portion. The alignment portion is disposed on the substrate. The extension portion is disposed on the substrate. The extension portion at least partially surrounds the alignment portion and is spaced apart from the alignment portion by a void. A side of the extension portion adjacent to the alignment portion and a side of the alignment portion adjacent to the extension portion are conformal to each other.

Abstract: Disclosed are a system for fabricating a semiconductor device and a method of fabricating a semiconductor device. The system may include a chamber, an extreme ultraviolet (EUV) source in the chamber and configured to generate an EUV beam, an optical system on the EUV source and configured to provide the EUV beam to a substrate, a substrate stage in the chamber and configured to receive the substrate, a reticle stage in the chamber and configured to hold a reticle that is configured to project the EUV beam onto the substrate, and a particle collector between the reticle and the optical system and configured to allow for a selective transmission of the EUV beam and to remove a particle.

Abstract: The disclosure provides an illumination system of a microlithographic projection device having an image plane, in which a mask can be arranged, and a first object plane, which is optically conjugate to the image plane. A first illumination optical unit illuminates the first object plane with first projection light so that the first projection light has a first illumination angle distribution in the image plane. A second illumination optical unit illuminates a second object plane, which is optically conjugate to the image plane, with second projection light so that the second projection light has a second illumination angle distribution differing from the first illumination angle distribution in the image plane. An optical integrator is arranged exclusively in the light path of the first projection light.

Abstract: A light emitting device includes an element mounting board including a base, a set of conductive patterns, one or more light emitting elements, and a cover member. The set of conductive patterns includes one or more first conductive layers and one or more second conductive layers made of a different material. The second conductive layers partially cover the first conductive layers. The set of conductive patterns defines one or more element mounting areas each including a part of the first conductive layers not covered by the second conductive layers, and external connectors each including one or more outer edge exposed parts where a part of an outer edge of a corresponding one of the first conductive layers is exposed from the second conductive layers. The cover member covers the light emitting elements and the element mounting areas. The cover member is spaced apart from the outer edge exposed parts.

Abstract: A monitor method for process control in a semiconductor fabrication process is disclosed. A first alignment mark is formed in a layer on a substrate, and its position is measured and stored in a first measurement data. A fabrication process is then performed. Afterwards, another measurement is performed to measure the position of the first alignment mark and to generate a second measurement data. Finally, an offset value between the position of the first alignment mark in the first measurement data and those in the second measurement data is calculated.

Abstract: A capacitor includes a semiconductor substrate. The capacitor also includes a first terminal having a fin disposed on a surface of the semiconductor substrate. The capacitor further includes a dielectric layer disposed onto the fin. The capacitor still further includes a second terminal having a FinFET compatible high-K metal gate disposed proximate and adjacent to the fin.

Abstract: A method of placing a work piece on a measuring device in which a work piece is placed on a table of a measuring device is provided. The method includes: using a retainer capable of holding the work piece above the table and a lifting/lowering device lifting and lowering a top surface of the table; holding the work piece above the table with the retainer; lifting the top surface of the table with the lifting/lowering device to bring the top surface of the table into contact with a bottom surface of the work piece; and, after a load of the work piece is borne by the table, releasing the hold of the retainer on the work piece.

Abstract: A method embodiment includes providing a reticle design data that specify a plurality of printable features that are formed on the wafer using the reticle and a plurality of nonprintable features that are not formed on the wafer using such reticle, wherein the reticle design data is usable to fabricate the reticle. A reduced design database is generated from the reticle design data and this reduced design database includes a description or map of the nonprintable features of the reticle, a description or map of a plurality of cell-to-cell regions of the reticle, and a grayscale reticle image that is rasterized from the reticle design data. The reduced design database, along with the reticle, is transferred to a fabrication facility so that the reduced design database is usable to periodically inspect the reticle in the fabrication facility.

Abstract: The inventive concepts provide a solar cell and a method of fabricating the same. The method includes preparing a substrate in a chamber, forming a light absorbing layer on the substrate by setting temperature in the chamber to a first temperature and by supplying a first source into the chamber, forming a buffer layer on the substrate by setting temperature in the chamber to a second temperature lower than the first temperature and by supplying the first source into the chamber, and forming a window layer on the substrate by supplying a second source different from the first source into the chamber.

Abstract: Some embodiments include a method of forming integrated circuitry. A first assembly is formed to have a first dielectric material, a first conductive pad and a conductive structure. The first assembly has a first surface which includes a surface of the first dielectric material, a surface of the first conductive pad and a surface of the conductive structure. A second assembly is formed to have a second dielectric material and a second conductive pad. The second assembly has a second surface which includes a surface of the second dielectric material and a surface of the second conductive pad. The first surface is placed directly against the second surface. The surface of the first dielectric material is bonded with the surface of the second dielectric material, and the surface of the first conductive pad is bonded with the surface of the second conductive pad.

Abstract: The present invention concerns a method for producing a volume object by lithography, comprising a projection of the projection image onto a plane to be illuminated of the layer of material, which involves: moving the mask in a movement having a component along an oblique axis forming an angle with the plane to be illuminated, and transforming a movement of the mask having a component along the oblique axis forming the angle with the plane to be illuminated into a displacement of the projection image on the plane to be illuminated along the first direction of the displacement contained in the plane to be illuminated by means of a mirror that reflects the projection image coming from the mask towards the plane to be illuminated.

Abstract: The inventive concepts provide a solar cell and a method of fabricating the same. The method includes preparing a substrate in a chamber, forming a light absorbing layer on the substrate by setting temperature in the chamber to a first temperature and by supplying a first source into the chamber, forming a buffer layer on the substrate by setting temperature in the chamber to a second temperature lower than the first temperature and by supplying the first source into the chamber, and forming a window layer on the substrate by supplying a second source different from the first source into the chamber.

Abstract: A mask has an inspection region virtually divided by a plurality of stripes. A position error-correcting unit is disposed on a stage in a region different from the mask, formed with patterns divided virtually by the plurality of stripes. A first deviation amount acquiring circuit acquires a first deviation amount from the optical image and the reference image of the position error correction unit. A second deviation amount acquiring circuit acquires a second deviation amount. A position correcting circuit corrects a positional relationship between the mask and the position error correction unit based on the first deviation amount, and obtains a fluctuation value of position coordinates of each pattern in the inspection region of the mask based on the second deviation amount and corrects the position coordinates.

Abstract: For a method for producing a circuit board consisting of a plurality of circuit board areas, wherein the individual circuit board areas comprise at least one layer made of an in insulating base material and a conducting pattern located on or in the base material, the following is provided: a substrate material, at least one registration mark formed in the substrate material, a first circuit board area arranged on the substrate material, at least one additional circuit board area, which substantially adjoins the first circuit board area or at least partially overlaps the first circuit board, the additional circuit board areas being oriented relative to the registration mark, and a plurality of connections of the conducting patterns of the first circuit board area and of the at least one additional circuit board area. Thus improved registration and orientation can be achieved when circuit board areas are coupled.

Abstract: The present disclosure relates to a structure and method to create a self-repairing dielectric material for semiconductor device applications. A porous dielectric material is deposited on a substrate, and exposed with treating agent particles such that the treating agent particles diffuse into the dielectric material. A dense non-porous cap is formed above the dielectric material which encapsulates the treating agent particles within the dielectric material. The dielectric material is then subjected to a process which creates damage to the dielectric material. A chemical reaction is initiated between the treating agent particles and the damage, repairing the damage. A gradient concentration resulting from the consumption of treating agent particles by the chemical reaction promotes continuous diffusion the treating agent particles towards the damaged region of the dielectric material, continuously repairing the damage.

Abstract: The invention is directed to a polymer thick film conductive composition comprising (a) a conductive silver-coated copper powder; and (b) an organic medium comprising two different resins and organic solvent, wherein the ratio of the weight of the conductive silver-coated copper powder to the total weight of the two different resins is between 5:1 and 45:1. The invention is further directed to a method of electrode grid and/or bus bar formation on thin-film photovoltaic cells using the composition and to cells formed from the method and the composition.

Abstract: A method of fabricating templated semiconductor nanowires on a surface of a semiconductor substrate for use in semiconductor device applications is provided. The method includes controlling the spatial placement of the semiconductor nanowires by using an oxygen reactive seed material. The present invention also provides semiconductor structures including semiconductor nanowires. In yet another embodiment, patterning of a compound semiconductor substrate or other like substrate which is capable of forming a compound semiconductor alloy with an oxygen reactive element during a subsequent annealing step is provided. This embodiment provides a patterned substrate that can be used in various applications including, for example, in semiconductor device manufacturing, optoelectronic device manufacturing and solar cell device manufacturing.

Abstract: A method to prevent movable structures within a MEMS device, and more specifically, in recesses having one or more dimension in the micrometer range or smaller (i.e., smaller than about 10 microns) from being inadvertently bonded to non-moving structures during a bonding process. The method includes surface preparation of silicon both structurally and chemically to aid in preventing moving structures from bonding to adjacent surfaces during bonding, including during high force, high temperature fusion bonding.

Abstract: The present invention provides a method and apparatus for fabricating piezoresistive polysilicon on a substrate by low-temperature metal induced crystallization by: (1) providing the substrate having a passivation layer; (2) performing, at or near room temperature in a chamber without breaking a vacuum or near-vacuum within the chamber, the steps of: (a) creating a metal layer on the passivation layer, and (b) creating an amorphous silicon layer on the metal layer, wherein the metal layer and the amorphous silicon layer have approximately the same thickness; (3) annealing the substrate, the passivation layer, the metal layer and the amorphous silicon layer at a temperature equal to or less than 600° C. and a period of time equal to or less than three hours to form a doped polysilicon layer below a residual metal layer; and (4) removing the residual metal layer to expose the doped polysilicon layer.

Abstract: Embodiments of the present invention generally relate to methods for lowering the dielectric constant of low-k dielectric films used in semiconductor fabrication. In one embodiment, a method for lowering the dielectric constant (k) of a low-k silicon-containing dielectric film, comprising exposing a porous low-k silicon-containing dielectric film to a hydrofluoric acid solution and subsequently exposing the low-k silicon-containing dielectric film to a silylation agent. The silylation agent reacts with Si—OH functional groups in the porous low-k dielectric film to increase the concentration of carbon in the low-k dielectric film.

Abstract: A production device (2) and a method for forming multilayered (3, 4, 5, 6, 7) modules, in particular solar modules (1), which have at least one translucent sheet-like layer (3, 6) and at least one solar- or light-active element is provided. The production device (2) forms the layer structure and has an applicator (33) for a connecting layer (5, 7) for the aforementioned layers (3, 4, 6). Furthermore, the device has a controllable curve(arch)-forming device (17) for bending and rolling a sheet-like layer (3, 6) while the layers are being applied.

Abstract: A method of forming a semiconductor device is disclosed. Provided is a substrate having at least one MOS device, at least one metal interconnection and at least one MOS device formed on a first surface thereof. A first anisotropic etching process is performed to remove a portion of the substrate from a second surface of the substrate and thereby form a plurality of vias in the substrate, wherein the second surface is opposite to the first surface. A second anisotropic etching process is performed to remove another portion of the substrate from the second surface of the substrate and thereby form a cavity in the substrate, wherein the remaining vias are located below the cavity. An isotropic etching process is performed to the cavity and the remaining vias.

Abstract: Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material on the first region formed using the first precursor, wherein the first material is different from a second material formed on a second region of the substrate.

Abstract: Method for making thin crystalline or polycrystalline layers. The method includes electrochemically etching a crystalline silicon template to form a porous double layer thereon, the double layer including a highly porous deeper layer and a less porous shallower layer. The shallower layer is irradiated with a short laser pulse selected to recrystallize the shallower layer resulting in a crystalline layer. Silicon is deposited on the recrystallized shallower layer and the silicon is irradiated with a short laser pulse selected to crystalize the silicon leaving a layer of crystallized silicon on the template. Thereafter, the layer of crystallized silicon is separated from the template. The process of the invention can be used to make optoelectronic devices.

Abstract: The present invention relates to a LED (light-emitting diode) phosphor and fabricating method thereof, and particularly relates to a LED phosphor having a light-emitting thin film (or photoluminescence thin film) made of an organic material and a zinc oxide microstructure (or nanostructure) and a method for fabricating the LED phosphor by hydrothermal method and combination of the organic material and the zinc oxide microstructure (or nanostructure). In this invention, the light-emitting thin film (or photoluminescence thin film) made of the organic material and the zinc oxide microstructure (or nanostructure) is applied instead of rare earth elements to fabricate the LED phosphor. Therefore, the cost of the LED phosphor and the white LED can be reduced and the processes for fabricating the LED phosphor and the white LED can be simplified.

Abstract: A backside illumination type solid-state imaging device includes stacked semiconductor chips which are formed such that two or more semiconductor chip units are bonded to each other, at least a first semiconductor chip unit is formed with a pixel array and a first multi-layered wiring layer, and a second semiconductor chip unit is formed with a logic circuit and a second multi-layered wiring layer, a connection wire which connects the first semiconductor chip unit and the second semiconductor chip unit, and a first shield wire which shields adjacent connection wires in one direction therebetween.

Abstract: Integrated Circuits and methods for reducing thermal neutron soft error rate (SER) of a digital circuit are provided by doping a protection layer on top of the metal layer and in physical contact with the metal layer of the digital circuit, wherein the protection layer is doped with additional thermal neutron absorbing material. The thermal neutron absorbing material can be selected from the group consisting of Gd, Sm, Cd, B, and combinations thereof. The protection layer may comprise a plurality of sub-layers among which a plurality of them containing additional thermal neutron absorbing material.

Abstract: A film deposition apparatus that laminates layers of reaction product by repeating cycles of sequentially supplying process gases that mutually reacts in a vacuum atmosphere includes a turntable receiving a substrate, process gas supplying portions supplying mutually different process gases to separated areas arranged in peripheral directions, and a separation gas supplying portion separating the process gases, wherein at least one process gas supplying portion extends between peripheral and central portions of the turntable and includes a gas nozzle discharging one process gas toward the turntable and a current plate provided on an upstream side to allow the separation gas to flow onto its upper surface, wherein a gap between the current plate and the turntable is gradually decreased from a central side of the turntable to a peripheral side of the turntable, and the gap is smaller on the peripheral side by 1 mm or greater.

Abstract: Provided is an apparatus that includes an integrated circuit located in a first region of a substrate having first and second opposing major surfaces and an alignment mark located in a second region of the substrate and extending through the substrate between the first and second surfaces.

Abstract: A method of depositing a film of forming a doped oxide film including a first oxide film containing a first element and doped with a second element on substrates mounted on a turntable including depositing the first oxide film onto the substrates by rotating the turntable predetermined turns while a first reaction gas containing the first element is supplied from a first gas supplying portion, an oxidation gas is supplied from a second gas supplying portion, and a separation gas is supplied from a separation gas supplying portion, and doping the first oxide film with the second element by rotating the turntable predetermined turns while a second reaction gas containing the second element is supplied from one of the first and second gas supplying portions, an inert gas is supplied from another one, and the separation gas is supplied from the separation gas supplying portion.

Abstract: An apparatus and method for combinatorial non-contact wet processing of a liquid material may include a source of a liquid material, a first reaction cell, a second reaction cell, a first plurality of gas jets disposed within an interior of the first reaction cell, the first plurality of gas jets configured to atomize the liquid material transferred to the interior of the first reaction cell, a second plurality of gas jets disposed within an interior of the second reaction cell, the second plurality of gas jets configured to atomize the liquid material transferred to the interior of the second reaction cell, a first vacuum element disposed along a periphery of the first reaction cell, and a second vacuum element disposed along a periphery of the at least a second reaction cell.

Abstract: An apparatus that comprises a device on a substrate and a crack stop in the substrate. Methods of forming a device are also disclosed. The methods may include providing a device, such as a semiconductor device, on a substrate having a first thickness, reducing the thickness of the substrate to a second thickness, and providing a crack stop in the substrate. Reducing the thickness of the substrate may include mounting the substrate to a carrier substrate for support and then removing the carrier substrate. The crack stop may prevent a crack from reaching the device.

Abstract: A plasma processing method is provided. The plasma processing method includes using the after-glow of a pulsed power plasma to perform conformal processing. During the afterglow, the equipotential field lines follow the contour of the workpiece surface, allowing ions to be introduced in a variety of incident angles, especially to non-planar surfaces. In another aspect of the disclosure, the platen may be biased positively during the plasma afterglow to attract negative ions toward the workpiece. Various conformal processing steps, such as implantation, etching and deposition may be performed.

Abstract: A method of fabricating a MEMS microphone includes: first providing a substrate having a first surface and a second surface. The substrate is divided into a logic region and a MEMS region. The first surface of the substrate is etched to form a plurality of first trenches in the MEMS region. An STI material is then formed in the plurality of first trenches. Subsequently, the second surface of the substrate is etched to form a second trench in the MEMS region, wherein the second trench connects with each of the first trenches. Finally, the STI material in the first trenches is removed.

Abstract: A method of manufacturing an integrated circuit (IC) for driving a flexible display includes depositing a pattern of spatially non-repetitive features in a first layer on a flexible substrate, said pattern of spatially non-repetitive features not substantially regularly repeating in both of two orthogonal directions (x,y) in the plane of the substrate; depositing a pattern of spatially repetitive features in a second layer on said first layer; aligning said second layer and said first layer so as to allow electrical coupling between said non-repetitive features and said repetitive features, wherein distortion compensation is applied during deposition of said repetitive features to enable said alignment.

Abstract: A semiconductor wafer, on the surface of which a silicon dioxide base material and an amorphous silicon thin film are formed in this order, is carried into a chamber. An insulated gate bipolar transistor (IGBT) is connected with a power supply circuit to a flash lamp, and the IGBT makes an energization period to the flash lamp to be 0.01 millisecond or more and 1 millisecond or less, consequently making a flash light irradiation time to be 0.01 millisecond or more and 1 millisecond or less. Since a flash heat treatment is performed with a remarkably short flash light irradiation time, the excessive heating of the thin film of amorphous silicon is suppressed and harmful influence such as the exfoliation of the film is prevented.

Abstract: Silicon on insulator structures having a high resistivity region in the handle wafer of the silicon on insulator structure are disclosed. Methods for producing such silicon on insulator structures are also provided. Exemplary methods involve creating a non-uniform thermal donor profile and/or modifying the dopant profile of the handle wafer to create a new resistivity profile in the handle wafer. Methods may involve one or more SOI manufacturing steps or electronic device (e.g., RF device) manufacturing steps.

Abstract: A semiconductor memory device includes at least one first semiconductor chip including a plurality of memory cells and a second semiconductor chip including a fuse circuit configured to repair defective cells among the memory cells of the at least one first semiconductor chip.

Abstract: A method of producing a hybrid substrate includes preparing a monocrystalline first substrate to obtain two surface portions. A temporary substrate is prepared including a mixed layer along which extends one surface portion and is formed of first areas and adjacent different second areas of amorphous material, the second areas forming at least part of the free surface of the first substrate. The first substrate is bonded to the other surface portion with the same crystal orientation as the first surface portion, by molecular bonding over at least the amorphous areas. A solid phase recrystallization of at least part of the amorphous areas according to the crystal orientation of the first substrate is selectively carried and the two surface portions are separated.

Abstract: Methods of transferring a layer of semiconductor material from a first donor structure to a second structure include forming recesses in the donor structure, implanting ions into the donor structure to form a generally planar, inhomogeneous weakened zone therein, and providing material within the recesses. The first donor structure may be bonded to a second structure, and the first donor structure may be fractured along the generally planar weakened zone, leaving the layer of semiconductor material bonded to the second structure. Semiconductor devices may be fabricated by forming active device structures on the transferred layer of semiconductor material. Semiconductor structures are fabricated using the described methods.

Abstract: An apparatus for electrostatic chucking and dechucking of a semiconductor wafer includes an electrostatic chuck with a number of zones. Each zone includes one or more polar regions around a lift pin that contacts a bottom surface of the semiconductor wafer. The apparatus also includes one or more controllers that control the lift pins and one or more controllers that control the polar regions. The controller for the lift pins receives data from one or more sensors and uses the data to adjust the upward force of the lift pins. Likewise, the controller for the polar regions receives data from the sensors and uses the data to adjust the voltage in the polar regions.

Abstract: The present invention provides a method of manufacturing a bonded wafer. The method includes ozone washing two silicon wafers to form an oxide film equal to or less than 2.2 nm in thickness on each surface of the two silicon wafers, and bonding the two silicon wafers through the oxide films formed to obtain a bonded wafer.

Abstract: A low temperature wafer bonding method and a bonded structure are provided. The method includes: providing a first substrate having a plurality of metal pads and a first dielectric layer close to the metal pads, where the metal pads and the first dielectric layer are on a top surface of the first substrate; providing a second substrate having a plurality of semiconductor pads and a second dielectric layer close to the semiconductor pads, where the semiconductor pads and the second dielectric layer are on a top surface of the second substrate; disposing at least one of the metal pads in direct contact with at least one of the semiconductor pads, and disposing the first dielectric layer in direct contact with the second dielectric layer; and bonding the metal pads with the semiconductor pads, and bonding the first dielectric layer with the second dielectric layer.

Abstract: A monolithically integrated MEMS pressure sensor and CMOS substrate using IC-Foundry compatible processes. The CMOS substrate is completed first using standard IC processes. A diaphragm is then added on top of the CMOS. In one embodiment, the diaphragm is made of deposited thin films with stress relief corrugated structure. In another embodiment, the diaphragm is made of a single crystal silicon material that is layer transferred to the CMOS substrate. In an embodiment, the integrated pressure sensor is encapsulated by a thick insulating layer at the wafer level. The monolithically integrated pressure sensor that adopts IC foundry-compatible processes yields the highest performance, smallest form factor, and lowest cost.

Abstract: A method for bonding a first substrate having a first surface to a second substrate having a second surface. This method includes the steps of holding the first substrate by at least two support points, positioning the first substrate and the second substrate so that the first surface and the second surface face each other, deforming the first substrate by applying between at least one pressure point and the two support points a strain toward the second substrate, bringing the deformed first surface and the second surface into contact, and progressively releasing the strain to facilitate bonding of the substrates while minimizing or avoiding the trapping of air bubbles between the substrates.

Abstract: A high-efficiency light emitting diode including: a semiconductor stack positioned on a support substrate, including a p-type compound semiconductor layer, an active layer, and an n-type compound semiconductor layer; an insulating layer disposed in an opening that divides the p-type compound semiconductor layer and active layer; a transparent electrode layer disposed on the insulating layer and the p-type compound semiconductor layer; a reflective insulating layer covering the transparent electrode layer, to reflect light from the active layer away from the support substrate; a p-electrode covering the reflective insulating layer; and an n-electrode is formed on top of the n-type compound semiconductor layer. The p-electrode is electrically connected to the transparent electrode layer through the insulating layer.