Method of Attaching an Interconnection Plate to a Semiconductor Die within a Leadframe Package
A method is disclosed for attaching an interconnection plate to semiconductor die within leadframe package. A base leadframe is provided with die pad for attaching semiconductor die. An interconnection plate is provided for attachment to the base leadframe and semiconductor die. Add a base registration feature onto base leadframe and a plate registration feature onto interconnection plate with the registration features designed to match each other such that, upon approach of the interconnection plate to base leadframe, the two registration features would engage and guide each other causing concomitant self-aligned attachment of the interconnection plate to base leadframe. Next, the interconnection plate is brought into close approach to base leadframe to engage and lock plate registration feature to base registration feature hence completing attachment of the interconnection plate to semiconductor die and forming a leadframe package.
This application is related to the following commonly assigned patent applications:
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- U.S. application Ser. No. 11/799,467 entitled “SEMICONDUCTOR PACKAGE HAVING DIMPLED PLATE INTERCONNECTIONS” by Ming Sun et al, publication# US20070290336, hereafter referred to as U.S. application Ser. No. 11/799,467
- US Patent Application Publication No. 20080087992 entitled “Semiconductor package having a bridged plate interconnection” by Shi Lei et al, hereafter referred to as US 20080087992
- Commonly assigned U.S. patent application Ser. No. 12/130,663 entitled “CONDUCTIVE CLIP FOR SEMICONDUCTOR DEVICE PACKAGE” by Shi Lei et al, hereafter referred to as U.S. application Ser. No. 12/130,663
- Commonly assigned U.S. patent application Ser. No. 12/237,953 entitled “Top Exposed Clip with Window Array” by Shi Lei et al, hereafter referred to as U.S. application Ser. No. 12/237,953
- Commonly assigned U.S. patent application Ser. No. 12/326,065 entitled “Top-side Cooled Semiconductor Package with Stacked Interconnection Plates and Method” by Kai Liu et al, hereafter referred to as U.S. application Ser. No. 12/326,065
whose content is incorporated herein by reference for any and all purposes.
This invention relates generally to the field of electronic system packaging. More specifically, the present invention is directed to packaging method of semiconductor dies.
BACKGROUND OF THE INVENTIONPackaging of power semiconductor dies of ever shrinking size and with ever reducing parasitic impedance has been driven by the consumer market on an ongoing basis. The following briefly reviews some related works.
FIG. A illustrates a prior art wherein two MOSFET semiconductor dies are packaged each with bond wires connected to its source and gate electrodes. While the associated assembly process is simple, the number of bond wires per package is limited by the package size owing to the significant size of wire bonding tools and technical constraints of the wire bonds—for example, bond wires should not cross each other. Additionally, the small cross section of bonding wires causes high connecting impedances (resistance and inductance) that in turn lower device current rating and can sometimes limit device operating frequency as well.
In U.S. Pat. No. 6,040,626 entitled “Semiconductor package” granted on Mar. 21, 2000 by Cheah et al, as illustrated in FIG. B, clip bonding for source electrical connection was described. Semiconductor package 110 includes a bottom plate portion 13 and terminals 12a, 12b. The semiconductor package 110 also includes a housing 22 formed from a moldable material. A beam portion 34 is integrally formed into one flowing member which extends from one lateral edge of a plate portion 30 and terminates at terminals 12b. A metalized region 19 defines a gate of a MOSFET die 16. The semiconductor die 16 includes a metalized region 18 defining a connection area for a top surface of the semiconductor die 16. The metalized region 19 is electrically coupled to one terminal 12b via wire bond 20. Thus, U.S. Pat. No. 6,040,626 employs a mixed connection to the MOSFET die 16 top surface, namely, a low resistance plate portion 30 for connecting to the source and a wire bond 20 for connecting to the gate 19. A gate runner (or bus) 19a couples the gate metalized region 19 to the source areas of the surface of the die 16. It is preferred that the plate portion 30 extend laterally beyond outermost portions of the gate runner 19a. It is also preferable that the plate portion 30 extends beyond and cover as much of the gate runner 19a as possible. This ensures that improved performance is achieved. While clip bonding, owing to its much larger cross section, offers lower connecting impedances hence high current rating and possibly high device operating frequency as well, its application to small package sizes is difficult as two internal connections are required per clip and small clips are hard to handle, align and position during the packaging process.
In U.S. Pat. No. 6,689,642 entitled “Semiconductor device and manufacturing method thereof” granted on Feb. 10, 2004 by Fukuda, as illustrated in FIG. C, a dual lead frame structure and assembly method for power MOSFET were described for reducing its on-state resistance and improving its production efficiency. The semiconductor package includes a lower frame 4 having a header 2 for fixing a semiconductor chip and corresponding external leads 3d, 3g, a semiconductor chip fixed on the header, an upper frame 7 having a connection electrode 6 fixed on a current passage electrode 5 formed on the top face of the semiconductor chip and the corresponding leads 3s, and a resin mold. This two-frame configuration provides extremely low on-state resistance and good production efficiency. The lower frame 4 itself is punched out from a copper material. The lower frame 4 includes a header 2 located in the center of the lower frame 4, three external leads 3d combined with the header 2 as one unit and extending from the header 2 to the outer frame 9, and an external lead 3g for another electrode with one end being close to the header 2 and another end being connected to the outer frame 9. Round index holes 12 are formed at both side edges of the outer frame 9 of the lower frame 4 with a constant interval for each side. These index holes are used for the positioning and the pitch-by-pitch transportation in the procedures of the manufacturing method. A square position-determining index hole for positioning the upper and lower frames 4, 7 is formed next to each round index hole 12 along the top side edge of the outer frame 9 of the lower frame. The round index holes 12 are formed at the locations corresponding to the lines connecting the centers of the headers 2 with a constant interval along the bottom side edge of the outer frame 9 of the lower frame 4. Two headers 2 and the corresponding external leads 3d are formed in one cell area 14 surrounded by the outer frame 9. The lower frame 4 has a 3.times.20 matrix of cell areas 14 between the top and bottom rows of index holes 12. Thus, one lower frame 4 has 60 cell areas and 120 headers 2 for fixing the semiconductor chips. The semiconductor chips are then fixed on each of the headers 2 in the cell areas 14 of the lower frame 4 by die bonding. That is, the semiconductor chips, such as power MOSFET bare chips, are fixed on the headers 2 of the lower frame 4 through the pre-form made of solder or silver paste using a die bonding instrument. During this procedure, the index holes 12 in the top and bottom side edges are used for the positioning of the headers 2 and for transporting the lower frame 4 by one pitch at a time. At the end, all the headers 2 of the lower frame 4 have a semiconductor chip fixed on themselves. Round index holes 12 are also formed at both side edges of the outer frame 9 of the upper frame 7 with a constant interval for each side, as in the case with the lower frame 4. These index holes are used for the positioning and the pitch-by-pitch transportation in the manufacturing method. A square position-determining index hole for positioning the upper and lower frames 4, 7 is formed next to each round index hole 12 along the top side edge of the outer frame 9 of the upper frame 7. The two position-determining index holes have an identical size and shape. Two connection electrodes 6 and the corresponding external leads 3s are formed in one cell area 14 surrounded by the outer frame 9. While the dual lead frame structure also offers high device current rating and lower connecting impedances, it entails a complicated assembly process. The assembly process either requires special machinery, or manual assembly, which greatly increases the cost and/or reduces the throughput.
U.S. application Ser. No. 11/799,467 disclosed a semiconductor package having dimpled plate interconnections. A source plate includes a plurality of dimples formed thereon. The dimples are concave with respect to a top surface of the source plate and include a through hole having an opening formed beyond a plane of a bottom surface thereof. Similarly, a gate plate includes a dimple that is concave with respect to a top surface of the gate plate and includes a through hole.
In US Patent Application 20080087992 entitled “Semiconductor package having a bridged plate interconnection” by Shi Lei et al, hereafter referred to as US 20080087992, a semiconductor package with a bridged source plate interconnection is disclosed for packaging a semiconductor die. A semiconductor package is illustrated that includes a leadframe having a die pad, a source contact portion and a gate contact portion. A bridged source plate includes a metal plate stamped or punched to form a bridge portion, valley portions on either side of the bridge portion, plane portions on either side of the valley portions and the bridge portion, and a connection portion depending from one of the plane portions.
In a commonly assigned U.S. patent application Ser. No. 12/130,663 with filing date May 30, 2008 and entitled “CONDUCTIVE CLIP FOR SEMICONDUCTOR DEVICE PACKAGE” by Shi Lei et al, hereafter referred to as U.S. application Ser. No. 12/130,663, a semiconductor device package with a conductive clip having separate parallel conductive fingers electrically connected to each other by conductive bridges is disclosed. A semiconductor device package is illustrated with its gate bond wire replaced with a gate clip. The device package includes a fused lead frame, a MOS device having top source, top gate and bottom drain located on top of the lead frame and a clip having separate parallel conductive fingers electrically connected to each other by conductive bridges. The clip is electrically bonded to the top source of the MOS device only at the bridges.
In a commonly assigned U.S. patent application Ser. No. 12/237,953 with filing date Sep. 24, 2008 and entitled “Top Exposed Clip with Window Array” by Shi Lei et al, hereafter referred to as U.S. application Ser. No. 12/237,953, a semiconductor device package with single stage clips is disclosed. Each single stage clip includes a metal sheet having arrays of windows thereon. The semiconductor device package includes a fused lead frame and a semiconductor device having contact regions on top and bottom surfaces. The semiconductor device may be a vertical metal oxide semiconductor (MOS) device having a top source contact, a top gate contact and a bottom drain contact. The semiconductor device is located on top of the lead frame with the bottom drain contact facing and making electrical contact with the main portion of the lead frame. The lead frame may be fused or non-fused. As an embodiment of U.S. application Ser. No. 12/237,953, the semiconductor device package includes single stage clips, which include two separate metal sheets having arrays of windows respectively.
In a commonly assigned U.S. patent application Ser. No. 12/326,065 entitled “Top-side Cooled Semiconductor Package with Stacked Interconnection Plates and Method” by Kai Liu et al, hereafter referred to as U.S. application Ser. No. 12/326,065, a top-side cooled semiconductor package with stacked interconnection plate is disclosed that includes a circuit substrate with terminal leads, a semiconductor die atop the circuit substrate, a low thermal resistance intimate interconnection plate for bonding and interconnecting a top contact area of the semiconductor die with the circuit substrate, a low thermal resistance stacked interconnection plate atop the intimate interconnection plate for top-side cooling, a molding encapsulant for encapsulating the package except for exposing a top surface of the stacked interconnection plate to maintain effective top-side cooling. The top portion of the stacked interconnection plate can include a peripheral overhang above the intimate interconnection plate. The peripheral overhang allows for a maximized exposed top surface area for heat dissipation independent of otherwise areal constraints applicable to the intimate interconnection plate. The stacked interconnection plate can be partially etched or three dimensionally formed to create the peripheral overhang.
In review of the above related works and the ongoing market demand of packaging power semiconductor dies with ever shrinking size and ever reducing parasitic impedance, it is desirable to further improve the fabrication and assembly process for packaging power semiconductor dies using interconnection plates.
SUMMARY OF THE INVENTIONA method is proposed for attaching an elevation-adaptive interconnection plate to a semiconductor die within a leadframe package. The package has numerous terminal leads for external electrical connection to it. The method includes:
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- a) Provide a base leadframe with terminal leads and a die pad on it for attaching the semiconductor die. Also, provide an interconnection plate for attachment to the base leadframe and the semiconductor die.
- b) Add a base registration feature onto the base leadframe and add a plate registration feature onto the interconnection plate. The base registration feature and the plate registration feature are shaped and sized to match each other such that, upon an approach of the interconnection plate to the base leadframe with the semiconductor die attached thereon, the plate registration feature and the base registration feature would engage and guide each other causing a concomitant self-aligned attachment of the interconnection plate to the base leadframe and the semiconductor die.
- c) Attach and bond the semiconductor die atop the die pad.
- d) Bring the interconnection plate into close approach to the base leadframe to engage and lock plate registration feature and base registration feature to each other hence completing attachment of the interconnection plate to the semiconductor die thus forming a leadframe package. Bond the interconnection plate to the semiconductor die. A molding encapsulant is then formed over the package in progress for passivation. Both base registration feature and plate registration feature can then be cut away from the leadframe package.
Multiple interconnection plate units may be thus individually aligned and attached to a base leadframe comprising several leadframe units.
In a more detailed embodiment, certain electrodes of the semiconductor die can instead be wire bonded to leads where it is not necessary to use interconnection plates.
As a refinement, the plate registration feature can be bonded onto the base registration feature with, for example, a solder joint.
To facilitate handling of the interconnection plate for a close approach to the base leadframe, a handling access area can be provided on it of sufficient size such that the interconnection plate can be handled with the tip of a pick up tool, for example a vacuum pick up tool, engaging the handling access area.
Under situations where the interconnection plate itself is too small to accommodate a handling access area, a separate handling access area of sufficient size can be appended to the interconnection plate such that the small sized interconnection plate can be handled with the tip of a pick up tool engaging the separate handling access area.
Under situations where the leadframe package is batch fabricated in multiple units on a common carrier frame, the appended separate handling access area can be shared among multiple leadframe package units on the common carrier frame.
In a particular embodiment, the appended separate handling access area is shared among two leadframe package units by orienting the two leadframe packages so they oppose each other referencing the handling access area.
Like the base registration feature and the plate registration feature, the separate handling access area can be cut away from the leadframe package after encapsulation.
As a refinement for engaging and locking plate registration feature and base registration feature to each other, a base registration hole and a plate registration hole can be made respectively on the base leadframe and the interconnection plate such that, upon attachment of the interconnection plate to the base leadframe, the two registration holes would line up with each other. Upon attachment of the interconnection plate to the base leadframe, a locking pin can then be inserted into the two registration holes to further lock the attachment in place.
As another refinement, both base leadframe and interconnection plate can be configured so that the base leadframe provides a first portion and the interconnection plate provides a second portion of the terminal leads.
These aspects of the present invention and their numerous embodiments are further made apparent, in the remainder of the present description, to those of ordinary skill in the art.
In order to more fully describe numerous embodiments of the present invention, reference is made to the accompanying drawings. However, these drawings are not to be considered limitations in the scope of the invention, but are merely illustrative.
FIG. A illustrates a prior art wherein MOSFET semiconductor dies are packaged with wire bonds connected to its source and gate electrodes;
FIG. B illustrates another prior art using clip bonding for source electrical connection;
FIG. C illustrates a third prior art of dual lead frame semiconductor device and associated assembly method for power MOSFET;
The description above and below plus the drawings contained herein merely focus on one or more currently preferred embodiments of the present invention and also describe some exemplary optional features and/or alternative embodiments. The description and drawings are presented for the purpose of illustration and, as such, are not limitations of the present invention. Thus, those of ordinary skill in the art would readily recognize variations, modifications, and alternatives. Such variations, modifications and alternatives should be understood to be also within the scope of the present invention. In this application, the terms interconnection plate and interconnection clip may be used interchangeably.
To match the plate registration features 35a and 35b of the dual interconnection plates 10, a base registration feature is added onto each base leadframe. Thus, the base leadframe 20a has an added base registration feature 30a, the base leadframe 20b has an added base registration feature 30b, the base leadframe 20c has an added base registration feature 30c and the base leadframe 20d has an added base registration feature 30d. To match the specific beam geometry of the plate registration features 35a and 35b as illustrated, the base registration feature 30a of base leadframe 20a is shaped and sized into a pair of ramped guiding tabs 32a, 34a. Likewise, the base registration feature 30b is shaped and sized into a pair of ramped guiding tabs 32b, 34b, etc. Furthermore, as can be seen from cross sectional views B-B and C-C, the ramped guiding tabs are tilted from vertical about the Y-axis.
In a manner similar to the above process,
Similarly,
As an example, the top view of
To those skilled in the art, by now it should become clear that, in addition to the specific geometries of base registration features and plate registration features illustrated above, the registration features can be designed with a large variety of other matched shapes and sizes to serve the same purpose of self-aligned attachment of interconnection plates to their corresponding semiconductor dies within a leadframe package. Some example shapes include round pins, round holes, square pins, square holes, cone-shaped pins, cone-shaped holes, spherical bumps, spherical cavities, spikes, wedges, etc. The geometric design for the base registration feature and the plate registration feature can be interchanged and modified as well. As another refinement, the base leadframe and the interconnection plate can be configured so that the base leadframe provides a first portion and the interconnection plate provides a second portion of the terminal leads. As another refinement, single interconnection plate can be used instead of a dual interconnection plates, for attaching to a single interconnection plate to a single semiconductor die at a time. As another refinement, multiple pickup tools can be used simultaneously to attach multiple clips to multiple dies. This can be performed using standard semiconductor packaging tools and requires no special equipment.
Regarding the heretofore disclosed handling access areas for facilitating the handling of interconnection plates, while they were illustrated as appendages to thus located away from the interconnection plates, it is pointed out that for those interconnection plates of sufficiently large size to accommodate a pick up tool the associated handling access area can be integrated into the main part of the interconnection plate as part of its built-in feature.
A method has been described for attaching an elevation-adaptive interconnection plate to a semiconductor die within a leadframe package by adding a base registration feature onto a base leadframe and adding a plate registration feature onto the interconnection plate such that the base registration feature and the plate registration feature are shaped and sized to match each other and to guide each other into the correct position. By now it should become clear to those skilled in the art that the numerous embodiments just described can be readily modified to suit other specific applications as well. While the description above contains many specificities, these specificities should not be constructed as accordingly limiting the scope of the present invention but as merely providing illustrations of numerous presently preferred embodiments of this invention. Any and all modifications that come within the meaning and range of equivalents within the claims are intended to be considered as being embraced within the spirit and scope of the present invention.
Claims
1. A method of attaching an elevation-adaptive interconnection plate to a semiconductor die within a leadframe package having a plurality of terminal leads for external electrical connection thereto, the method comprises:
- a) providing a base leadframe having a die pad for attaching the semiconductor die thereon and providing an interconnection plate for attachment to the base leadframe and the semiconductor die;
- b) adding a base registration means onto the base leadframe and adding a plate registration means, matching the base registration means, onto the interconnection plate such that, upon an approach of the interconnection plate to the base leadframe with the semiconductor die attached thereon, the plate registration means and the base registration means would engage and guide each other causing a concomitant self-aligned attachment of the interconnection plate to the base leadframe and the semiconductor die;
- c) attaching and bonding the semiconductor die atop the die pad; and
- d) bringing the interconnection plate into close approach to the base leadframe to engage and lock plate registration means and base registration means to each other hence completing attachment of the interconnection plate to the semiconductor die whereby forming a leadframe package.
2. The method of claim 1 further comprises bonding the interconnection plate to the semiconductor die.
3. The method of claim 2 further comprises wire bonding a number of pre-determined electrodes of the semiconductor die to the terminal leads.
4. The method of claim 2 further comprises forming a molding encapsulant over the package in progress for passivation.
5. The method of claim 2 further comprises bonding the plate registration means onto the base registration means.
6. The method of claim 5 wherein bonding the plate registration means onto the base registration means further comprises bonding them with a solder joint.
7. The method of claim 4 further comprises cutting away both base registration means and plate registration means from the leadframe package.
8. The method of claim 7 wherein bringing the interconnection plate further comprises providing a interconnection plate such that after cutting away both base registration means and plate registration means from the leadframe package, the leadframe package has leads formed from said interconnection plate.
9. The method of claim 8 wherein bringing the interconnection plate further comprises providing a interconnection plate such that said leads formed from said interconnection plate are approximately the same width as where the interconnection plate connects to the semiconductor die.
10. The method of claim 8 wherein bringing the interconnection plate further comprises providing a handling access area thereon of sufficient size such that the interconnection plate can be handled with a pick up tool engaging the handling access area.
11. The method of claim 1 wherein bringing the interconnection plate into close approach to the base leadframe further comprises bringing multiple interconnection plate units into close approach to the base leadframe, so that each interconnection plate unit may locally and independently engage and self-align with the base leadframe.
12. The method of claim 1 wherein providing a base leadframe further comprises providing a plurality of base leadframes on a common base leadframe carrier frame.
13. The method of claim 12 wherein bringing the interconnection plate into close approach to the base leadframe further comprises bringing multiple interconnection plate units into close approach to the common base leadframe carrier frame, so that each interconnection plate unit may locally and independently engage and self-align with the base leadframe.
14. The method of claim 1 wherein bringing the interconnection plate further comprises providing a handling access area thereon of sufficient size such that the interconnection plate can be handled with a pick up tool engaging the handling access area.
15. The method of claim 1 wherein, to facilitate handling of small sized interconnection plate, bringing the interconnection plate further comprises appending a separate handling access area of sufficient size to the interconnection plate such that the small sized interconnection plate can be handled with the tip of a pick up tool engaging the separate handling access area.
16. The method of claim 15, wherein the leadframe package is batch fabricated in multiple units on a common carrier frame, appending the separate handling access area further comprises sharing each handling access area among at least two leadframe package units on the common carrier frame.
17. The method of claim 16 wherein sharing each handling access area further comprises sharing it among two leadframe package units by orienting the two leadframe packages so they oppose each other referencing the handling access area.
18. The method of claim 15 further comprises cutting away the separate handling access area from the leadframe package.
19. The method of claim 1 wherein bringing the interconnection plate into close approach to the base leadframe further comprises:
- d1) making a base registration hole and a plate registration hole respectively on the base leadframe and the interconnection plate such that, upon attachment of the interconnection plate to the base leadframe, the two registration holes would line up with each other; and
- d2) upon attachment of the interconnection plate to the base leadframe, inserting a locking pin into the two registration holes to further lock the attachment in place.
20. The method of claim 1 wherein providing the base leadframe further comprises providing the plurality of terminal leads.
21. The method of claim 1 wherein providing the base leadframe further comprises providing a first portion of the plurality of terminal leads and providing the interconnection plate further comprises providing a second portion of the plurality of terminal leads.
22. An interim semiconductor package for forming a leadframe package, the interim semiconductor package comprises: whereby, upon an approach of the interconnection plate to the base leadframe, the plate registration means and the base registration means engage and guide each other causing a concomitant self-aligned attachment of the interconnection plate to the base leadframe and atop the semiconductor die thus forming the leadframe package.
- a) a base leadframe having a die pad with a semiconductor die bonded thereon and a base registration means; and
- b) an elevation-adaptive interconnection plate having a plate registration means matching the base registration means
23. The interim semiconductor package of claim 22 wherein said elevation-adaptive interconnection plate further comprises an appended separate handling access area to allow a pick-up tool to handle the interconnection plate during an assembly process.
24. The interim semiconductor package of claim 23 wherein the leadframe package is batch fabricated with multiple interconnection plate units on a common carrier frame.
Type: Application
Filed: Oct 27, 2009
Publication Date: Apr 28, 2011
Patent Grant number: 8076183
Inventors: Yan Xun Xue (Los Gatos, CA), Jun Lu (San Jose, CA), Le Shi (Shanghal), Liang Zhao (Shangal)
Application Number: 12/606,290
International Classification: H01L 23/495 (20060101); H01L 21/60 (20060101);