With Structure For Mounting Semiconductor Chip To Lead Frame (e.g., Configuration Of Die Bonding Flag, Absence Of A Die Bonding Flag, Recess For Led) Patents (Class 257/676)
  • Patent number: 11916000
    Abstract: A semiconductor device includes a first die pad, a second die pad, a first semiconductor element, a second semiconductor element, an insulating element, first terminals, second terminals, and a sealing resin. The sealing resin has a top surface, a bottom surface, and a first side surface connected to the top surface and the bottom surface. The first side surface includes a first region connected to the top surface, a second region connected to the bottom surface, and a third region connected to the first region and the second region, the plurality of first terminals being exposed to the third region. A surface roughness of each of the top surface, the bottom surface, the first region, and the second region is larger than a surface roughness of the third region.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: February 27, 2024
    Assignee: ROHM CO., LTD.
    Inventor: Hiroaki Matsubara
  • Patent number: 11908795
    Abstract: An embodiment is a method including forming a first package. The forming the first package includes forming a through via adjacent a first die, at least laterally encapsulating the first die and the through via with an encapsulant, and forming a first redistribution structure over the first die, the through via, and the encapsulant. The forming the first redistribution structure including forming a first via on the through via, and forming a first metallization pattern on the first via, at least one sidewall of the first metallization pattern directly overlying the through via.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, An-Jhih Su
  • Patent number: 11908828
    Abstract: Systems and methods for controlling contamination during thermocompression bonding are provided herein. The tool generally includes a bondhead having a first channel extending in a lateral direction from a first port along a second side toward a perimeter of the bondhead. In several examples, the bondhead includes a second channel fluidly coupled to a second port and extending in a lateral direction along an inset surface of the bondhead, where the second channel at least partially surrounds the first channel. In other examples, the tool includes a vacuum manifold having a vacuum opening positioned laterally outward from the bondhead. A first flow unit is coupled to the first channel and is configured to withdraw air. A second flow unit is coupled to the second port or the manifold to withdraw fluid and prevent outgassing bonding materials from entering the first channel, depositing on the bondhead, and/or contaminating neighboring semiconductor components.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Brandon P. Wirz, Jaekyu Song, Sui Chi Huang
  • Patent number: 11901326
    Abstract: An object is to provide a semiconductor device which suppresses poor bonding between a metal pattern and an electrode terminal due to insufficient temperature rise at the time of bonding the metal pattern and the electrode terminal. The electrode terminal is branched into a plurality of branch portions in a width direction on one end side of an extending direction thereof, of the plurality of branch portions, a first branch portion and a second branch portion are bonded on the metal pattern via a bonding material, respectively, the first branch portion has a wider width than that of the second branch portion, and the bonding material between the second branch portion and the metal pattern is thinner than the bonding material between the first branch portion and the metal pattern.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: February 13, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shinsuke Asada, Satoru Ishikawa, Yuki Yano, Shohei Ogawa, Kiyoshi Arai
  • Patent number: 11895930
    Abstract: A current sensor package, comprises a current path and a sensing device. The sensing device is spaced from the current path, and the sensing device is configured for sensing a magnetic field generated by a current flowing through the current path. Further, the sensing device comprises a sensor element. The sensing device is electrically connected to a conductive trace. An encapsulant extends continuously between the current path and the sensing device.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: February 6, 2024
    Assignee: Infineon Technologies AG
    Inventors: Rainer Markus Schaller, Volker Strutz
  • Patent number: 11894290
    Abstract: A power device for surface mounting has a leadframe including a die-attach support and at least one first lead and one second lead. A die, of semiconductor material, is bonded to the die-attach support, and a package, of insulating material and parallelepipedal shape, surrounds the die and at least in part the die-attach support and has a package height. The first and second leads have outer portions extending outside the package, from two opposite lateral surfaces of the package. The outer portions of the leads have lead heights greater than the package height, extend throughout the height of the package, and have respective portions projecting from the first base.
    Type: Grant
    Filed: January 5, 2023
    Date of Patent: February 6, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Cristiano Gianluca Stella, Fabio Vito Coppone, Francesco Salamone
  • Patent number: 11887916
    Abstract: In one example, an electronic device includes a substrate with a conductive structure and a substrate encapsulant. The conductive structure has a lead with a lead via and a lead protrusion. The lead via can include via lateral sides defined by first concave portions and the lead protrusion can include protrusion lateral sides defined by second concave portions. The substrate encapsulant covers the first concave portions at a first side of the substrate but not the second concave portions so that the lead protrusion protrudes from the substrate encapsulant at a second side of the substrate. An electronic component can be adjacent to the first side of the substrate and electrically coupled to the conductive structure. A body encapsulant encapsulates portions of the electronic component and the substrate. In some examples, the lead can further include a lead trace at the second side of the substrate. In some examples, the substrate can include a redistribution structure at the first side of the substrate.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: January 30, 2024
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Hyeong Il Jeon, Gi Jeong Kim, Yong Ho Son, Byong Jin Kim, Jae Min Bae, Seung Woo Lee
  • Patent number: 11887918
    Abstract: Disclosed is a packaging solution, such as a lead frame for circuit board packaging, a packaged integrated circuit board, a power chip, and a circuit board packaging method. The lead frame includes a plurality of frame units disposed in parallel in a first direction. The frame unit includes a hollow bezel, and a plurality of pins and connecting ribs that are disposed in the bezel. Each pin includes a first pin part and a second pin part that extend in a second direction and are integrally formed. The first pin part is disposed in the bezel, the first pin part is configured to electrically connect to a circuit board, and the second pin part is connected and fastened to the bezel. The second direction is perpendicular to the first direction. The connecting ribs are connected among the plurality of pins and the bezel.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: January 30, 2024
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Xuanwei Fang, Zhiqiang Xiang
  • Patent number: 11881494
    Abstract: A semiconductor package and a method of manufacturing thereof is disclosed. The package includes a package substrate having a die attach region with a die attached thereto. A protective cover is disposed over a sensor region of the die and attached to the die by a cover adhesive. The package includes a dam structure configured to protect components of the semiconductor package from contamination.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: January 23, 2024
    Assignee: UTAC HEADQUARTERS PTE. LTD.
    Inventors: Jeffrey Punzalan, Il Kwon Shim
  • Patent number: 11876061
    Abstract: Provided here are: an electrically-conductive semiconductor substrate with which a semiconductor circuit is formed; an insulating film deposited on a major surface of the electrically-conductive semi-conductor substrate; and a bonding pad having fixing parts fixed onto the insulating film, side wall parts rising up from the fixing parts, and an electrode part connected to the side wall parts and disposed in parallel to the major surface; wherein the electrode part forms, together with the insulating film, a gap region therebetween, and portions of the electrode part where it is connected to the side wall parts are configured to have at least one of: a positional relationship in which they sandwich therebetween a central portion of the electrode part in its bonding region to be bonded to a bonding wire; and a positional relationship in which they surround the central portion.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: January 16, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yasuki Aihara
  • Patent number: 11869830
    Abstract: A clip, a semiconductor package, and a method are disclosed. In one example the clip includes a die attach portion having a first main face and a second main face opposite to the first main face, and at least one through-hole extending between the first and second main faces and including a curved transition from an inner wall of the at least one through-hole to the first main face.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: January 9, 2024
    Assignee: Infineon Technologies AG
    Inventors: Michael Stadler, Thomas Bemmerl
  • Patent number: 11869844
    Abstract: A semiconductor device and a manufacturing method of the semiconductor device by which peeling off of a sealing resin and a wire from each other can be practically suppressed are disclosed. The semiconductor device includes a substrate, a main face wire, a semiconductor element that is conductive to the main face wire, a sealing resin having resin side faces directed in a direction crossing a thickness direction, the sealing resin sealing the main face wire and the semiconductor element, a through-wire that is conductive to the main face wire and having an exposed rear face exposed from the substrate, and a column conductor that is conductive to the main face wire and having an exposed side face exposed from the resin side faces. The column conductor is supported from the opposite sides thereof in the thickness direction by the substrate and the sealing resin.
    Type: Grant
    Filed: November 14, 2022
    Date of Patent: January 9, 2024
    Assignee: ROHM CO., LTD
    Inventor: Hiroyuki Shinkai
  • Patent number: 11862479
    Abstract: A method of making a semiconductor device includes mounting at least two semiconductor dies to a die pad of a leadframe in spaced apart relation to each other, the leadframe having a plurality of preformed leads, electrically connecting each semiconductor die to at least one preformed lead of the leadframe, forming a molding structure including at least part of the semiconductor dies and the preformed leads of the leadframe, and forming a trench in the molding structure in a space between the at least two semiconductor dies, the trench separating the die pad into first and second die pad portions.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: January 2, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Bernard Kaebin Andres Ancheta, Emerson Mamaril Enipin, John Carlo Cruz Molina
  • Patent number: 11862597
    Abstract: An asymmetric stackup structure for an SoC package substrate is disclosed. The package substrate may include a substrate with one or more insulating material layers. A first recess may be formed in an upper surface of the substrate. The recess may be formed down to a conductive layer in the substrate. An integrated passive device may be positioned in the recess. A plurality of build-up layers may be formed on top of the substrate. At least one via path may be formed through the build-up layers and the substrate to connect contacts on the lower surface of the substrate to contacts on the upper surface of the build-up layers.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: January 2, 2024
    Assignee: Apple Inc.
    Inventors: Yikang Deng, Taegui Kim, Yifan Kao, Jun Chung Hsu
  • Patent number: 11854948
    Abstract: A semiconductor package includes a package substrate including a redistribution layer; a semiconductor chip disposed on the package substrate and electrically connected to the redistribution layer; a wiring structure disposed on the semiconductor chip and having an upper surface on which pads are arranged; a vertical connection structure disposed between the package substrate and the wiring structure and electrically connecting the redistribution layer and the pads; and a passivation layer disposed on the wiring structure and having openings partially exposing a region of each of the pads. The pads include a first pad adjacent to a corner of the wiring structure, and a second pad closer to a center of the wiring structure than the first pad. A first width of the first pad is greater than a second width of the second pad. A contact layer is disposed in the opening on the first pad.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: December 26, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byungho Kim, Seongjin Shin
  • Patent number: 11854921
    Abstract: A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Sung-Feng Yeh, Ming-Fa Chen, Hsien-Wei Chen, Tzuan-Horng Liu
  • Patent number: 11848256
    Abstract: Embodiments of the present disclosure are directed to leadframe semiconductor packages having die pads with cooling fins. In at least one embodiment, the leadframe semiconductor package includes leads and a semiconductor die (or chip) coupled to a die pad with cooling fins. The cooling fins are defined by recesses formed in the die pad. The recesses extend into the die pad at a bottom surface of the semiconductor package, such that the bottom surfaces of the cooling fins of the die pad are flush or coplanar with a surface of the package body, such as an encapsulation material. Furthermore, bottom surfaces of the cooling fins of the die pad are flush or coplanar with exposed bottom surfaces of the leads.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: December 19, 2023
    Assignee: STMICROELECTRONICS, INC.
    Inventor: Jefferson Talledo
  • Patent number: 11848297
    Abstract: In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions spaced from the die mount portion; a semiconductor die over the die mount portion having bond pads on an active surface facing away from the package substrate; non-gold bond wires forming electrical connections between at least one of the bond pads and one of the lead portions of the package substrate; a bond stitch on bump connection formed between one of the non-gold bond wires and a bond pad of the semiconductor die, comprising a stitch bond formed on a flex stud bump; and dielectric material covering a portion of the package substrate, the semiconductor die, the non-gold bond wires, the stitch bond and the flex stud bump, forming a packaged semiconductor device.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: December 19, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Bo-Hsun Pan, Chien-Chang Li, Hung-Yu Chou, Shawn Martin O'Connor, Byron Lovell Williams, Jeffrey Alan West, Zi-Xian Zhan, Sheng-Wen Huang
  • Patent number: 11842951
    Abstract: A semiconductor device includes a semiconductor element, a first lead (1), a plurality of second leads and a sealing resin. The first lead includes a mounting portion mounting the semiconductor element, four connecting portions extending from four corners of the mounting portion, respectively, and four first terminal portions connected to front ends of the connecting portions, respectively. A part of each first terminal portion is exposed from the sealing resin. The second leads are arranged in a plural quantity between adjacent first terminal portions when viewed in a thickness direction. Each second lead includes a second terminal portion having a part exposed from the sealing resin, and a joining portion extending from the second terminal portion toward the mounting portion. A connecting portion width dimension of the connecting portion is greater than a joining portion width dimension of the joining portion of the second lead adjacent to the connecting portion.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: December 12, 2023
    Assignee: ROHM CO., LTD.
    Inventor: Ippei Yasutake
  • Patent number: 11842953
    Abstract: A method of attaching a metal clip to a semiconductor die includes: aligning a first bonding region of the metal clip with a first bond pad of the semiconductor die; and while the first bonding region of the metal clip is aligned with the first bond pad of the semiconductor die, forming a plurality of first wire bonds to the first bond pad of the semiconductor die through a plurality of openings in the first bonding region of the metal clip, the plurality of first wire bonds forming a joint between the metal clip and the first bond pad of the semiconductor die. Additional methods and related semiconductor packages produced from such methods are also described.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: December 12, 2023
    Assignee: Infineon Technologies AG
    Inventors: Mohd Kahar Bajuri, Joel Feliciano Del Rosario, Thai Kee Gan, Mohd Afiz Hashim, Mei Fen Hiew
  • Patent number: 11837531
    Abstract: A semiconductor device includes a chip carrier, a first semiconductor chip arranged on the chip carrier, the first semiconductor chip being located in a first electrical potential domain when the semiconductor device is operated, a second semiconductor chip arranged on the chip carrier, the second semiconductor chip being located in a second electrical potential domain different from the first electrical potential domain when the semiconductor device is operated, and an electrically insulating structure arranged between the first semiconductor chip and the second semiconductor chip, which is designed to galvanically isolate the first semiconductor chip and the second semiconductor chip from each other.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: December 5, 2023
    Assignee: Infineon Technologies AG
    Inventor: Rainer Markus Schaller
  • Patent number: 11830792
    Abstract: The semiconductor device includes first and second semiconductor elements. Each element has an obverse surface and a reverse surface, with a first electrode arranged on the reverse surface, and with a second electrode arranged on the obverse surface. The semiconductor device further includes: a first lead having an obverse surface and a reverse surface; an insulating layer covering the first lead, the first semiconductor element and the second semiconductor element; a first electrode connected to the second electrode of the first semiconductor element; and a second electrode connected to the first lead. The first semiconductor element and the first lead are bonded to each other with the reverse surface of the first semiconductor element facing the lead obverse surface. The second semiconductor element and the first lead are bonded to each other with the reverse surface of the second semiconductor element facing the lead reverse surface.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: November 28, 2023
    Assignee: ROHM CO., LTD.
    Inventor: Kentaro Nasu
  • Patent number: 11830842
    Abstract: A device assembly includes a functional substrate having one or more electronic components formed there. The functional substrate has a cavity extending from a first surface toward a second surface of the functional substrate at a location that lacks the electronic components. The device assembly further includes a semiconductor die placed within the cavity with a pad surface of the semiconductor die being opposite to a bottom of the cavity. The functional substrate may be formed utilizing a first fabrication technology and the semiconductor die may be formed utilizing a second fabrication technology that differs from the first fabrication technology.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: November 28, 2023
    Assignee: NXP USA., Inc.
    Inventors: Li Li, Lakshminarayan Viswanathan, Jeffrey Kevin Jones
  • Patent number: 11823911
    Abstract: The present invention relates to a process of a package-then-etch three-dimensional package structure electrically connected by plated copper pillars. The process comprises the following steps: taking a metal carrier; preplating a surface of the metal carrier with a copper layer; forming an outer metal pin by means of electroplating; performing plastic packaging with epoxy resin; forming a metal circuit layer by means of electroplating; forming a conductive metal pillar by means of electroplating; surface-mounting a chip; performing plastic packaging; surface-mounting a passive device; performing plastic packaging; etching and windowing the carrier; forming an anti-oxidant metal layer by means of electroplating; and performing cutting to obtain a finished product. The integration level and the reliability can be improved.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: November 21, 2023
    Assignee: JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Haishen Kong, Yubin Lin, Jinxin Shen, Xinfu Liang, Qingyun Zhou
  • Patent number: 11817423
    Abstract: Embodiments include a package substrate and semiconductor packages. A package substrate includes a first cavity in a top surface, first conductive pads on a first surface of the first cavity, a second cavity in a bottom surface, second conductive pads on a second surface of the second cavity, where the first surface is above the second surface, and a third cavity in the first and second cavities, where the third cavity vertically extends from the top surface to the bottom surface. The third cavity overlaps a first portion of the first cavity and a second portion of the second cavity. The package substrate may include conductive lines coupled to the first and second conductive pads, a first die in the first cavity, a second die in the second cavity, and interconnects in the third cavity that directly couple first die to the second die.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: November 14, 2023
    Assignee: Intel Corporation
    Inventor: Pooya Tadayon
  • Patent number: 11798868
    Abstract: A semiconductor die having a metal tab connected thereto. The metal tab includes at least one slot on at least one side of the metal tab, wherein the at least one slot i) creates an opening between at least two portions of the metal tab and ii) exposes the semiconductor die in relation to the metal tab. The semiconductor die can be a silicon (Si) die and the metal tab can be a copper (Cu) tab, where the at least one slot includes at least four slots corresponding to each of at least four sides of the metal, and wherein with respect to each of the at least four sides, each corresponding slot i) creates an opening between at least two portions of the Cu metal tab and ii) exposes the Si semiconductor die in relation to the Cu metal tab.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: October 24, 2023
    Inventor: Thomas Spann
  • Patent number: 11791288
    Abstract: Implementations of methods of forming a plurality of reinforced die may include forming a plurality of die on a substrate and patterning a metal gang frame to form a plurality of metal plates. The plurality of metal plates may correspond to the plurality of die. The method may include coupling the metal gang frame over the plurality of die and singulating the plurality of die. Each die of the plurality of die may include the corresponding metal plate from the plurality of metal plates coupled over the plurality of die.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: October 17, 2023
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Chee Hiong Chew, Erik Nino Tolentino, Yusheng Lin, Swee Har Khor
  • Patent number: 11791247
    Abstract: Semiconductor packages may include a lead frame, one or more semiconductor die coupled with the lead frame, and an interposer coupled with the lead frame and with at least one of the one or more semiconductor die. The interposer in implementations includes an electrically conductive material coupled with an electrically insulative material. The interposer may be coupled with the lead frame through the electrically insulative material such that the electrically conductive material is electrically isolated from the lead frame. The interposer may facilitate a gate node of the package being fully encapsulated within the package without being exposed through an encapsulant of the package. Fully encapsulating the gate node within the package may allow a contact pad of another node to have a larger area exposed through the encapsulant to provide greater heat transfer to a printed circuit board (PCB).
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: October 17, 2023
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Erwin Ian Vamenta Almagro, Maria Clemens Ypil Quinones, Romel N. Manatad, Maria Cristina Estacio, Elsie Agdon Cabahug
  • Patent number: 11791249
    Abstract: An isolated power converter package includes a leadframe including a first and second die pad, first and second supports connected to first leads, second leads, at least one downset pad, and at least one downset feature between the supports and downset pad. A first semiconductor die is on the first die pad and a second semiconductor die is on the second die pad. The transformer stack includes a top and bottom side magnetic sheet on respective sides of a laminate substrate including an embedded coil that has coil contacts. Edges of the laminate substrate are on the supports. Bond wires are between the first die bond pads and the second leads, between the second die bond pads and the second leads, between the first die bond pads and coil contacts, and between the second die bond pads and the coil contacts. The downset pad is exposed from a mold compound.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: October 17, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Vijaylaxmi Gumaste Khanolkar
  • Patent number: 11791296
    Abstract: In some examples, an electronic device comprises a first component having a surface, a second component having a surface, and a bond layer positioned between the surfaces of the first and second components to couple the first and second components to each other. The bond layer includes a set of metallic nanowires and a dielectric portion. The dielectric portion comprises a polymer matrix and dielectric nanoparticles.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: October 17, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Scott Robert Summerfelt, Benjamin Stassen Cook, Ralf Jakobskrueger Muenster, Sreenivasan Kalyani Koduri
  • Patent number: 11785853
    Abstract: Stack assembly for radio-frequency applications. In some embodiments, a radio-frequency (RF) module can include a packaging substrate configured to receive a plurality of components, and an electro-acoustic device mounted on the packaging substrate. The RF module can further include a die having an integrated circuit and mounted over the electro-acoustic device to form a stack assembly. The electro-acoustic device can be, for example, a filter device such as a surface acoustic wave filter. The die can be, for example an amplifier die such as a low-noise amplifier implemented on a silicon die.
    Type: Grant
    Filed: June 13, 2021
    Date of Patent: October 10, 2023
    Assignee: Skyworks Solutions, Inc.
    Inventors: Hardik Bhupendra Modi, Adarsh Karan Jaiswal, Anil K. Agarwal, Engin Ibrahim Pehlivanoglu
  • Patent number: 11784181
    Abstract: Embodiments may relate to a die with a front-end and a backend. The front-end may include a transistor. The backend may include a signal line, a conductive line, and a diode that is communicatively coupled with the signal line and the conductive line. Other embodiments may be described or claimed.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: October 10, 2023
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Adel A. Elsherbini, Feras Eid, Veronica Aleman Strong, Johanna M. Swan
  • Patent number: 11776863
    Abstract: A semiconductor device package includes a carrier, a first interposer disposed and a second interposer. The second interposer is stacked on the first interposer, and the first interposer is mounted to the carrier. The combination of the first interposer and the second interposer is substantially T-shaped.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: October 3, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hao-Chih Hsieh, Tun-Ching Pi, Sung-Hung Chiang, Yu-Chang Chen
  • Patent number: 11776882
    Abstract: A method includes: arranging a semiconductor device on a redistribution substrate, the device having a first power electrode and a control electrode on a first surface and a second power electrode on a second surface, the redistribution substrate having an insulating board having a first major surface and a second major surface having solderable contact pads, so that the first power electrode is arranged on a first conductive pad and the control electrode is arranged on a second conductive pad on the first major surface; arranging a contact clip such that a web portion is arranged on the second power electrode and a peripheral rim portion is arranged on a third conductive pad on the first major surface; and electrically coupling the first power electrode, control electrode and peripheral rim portion to the respective conductive pads and electrically coupling the web portion to the second power electrode.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: October 3, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Markus Dinkel, Petteri Palm, Eung San Cho, Josef Hoeglauer, Ralf Otremba, Fabian Schnoy
  • Patent number: 11770010
    Abstract: GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: September 26, 2023
    Assignee: Navitas Semiconductor Limited
    Inventors: Daniel M. Kinzer, Santosh Sharma, Ju Jason Zhang
  • Patent number: 11769714
    Abstract: Provided is a semiconductor device including: a bed having a bed surface; a semiconductor chip having a bottom surface larger than the bed surface, the semiconductor chip being provided such that a center of the bottom surface is disposed above the bed surface and the bottom surface having a first end and a second end; a joint material provided between the bed surface and the bottom surface; a plate-like first wire having a first surface and provided such that the first surface faces the first end; a plate-like second wire having a second surface and provided such that the second surface faces the second end; a first insulating film having a third surface and a fourth surface provided on an opposite side of the third surface, the third surface being in contact with the first end, the fourth surface being in contact with the first surface; and a second insulating film having a fifth surface and a sixth surface provided on an opposite side of the fifth surface, the fifth surface being in contact with the second
    Type: Grant
    Filed: July 5, 2021
    Date of Patent: September 26, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Daisuke Koike
  • Patent number: 11769247
    Abstract: An IC assembly including an exposed pad integrated circuit (“IC”) package having a thermal pad with a top surface and a bottom surface and with at least one peripheral surface portion extending transversely of and continuous with the bottom surface. The bottom surface and the at least one peripheral surface are exposed through a layer of mold compound. Also, methods of making an exposed pad integrated circuit (“IC”) package assembly. One method includes optically inspecting a solder bond bonding a thermal pad of an exposed pad IC package to a printed circuit board. Another method includes wave soldering an exposed pad of an IC package to a printed circuit board.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: September 26, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Reynaldo Corpuz Javier, Alok Kumar Lohia, Andy Quang Tran
  • Patent number: 11764152
    Abstract: Disclosed herein is an apparatus that includes a semiconductor substrate having a main surface extending in a first direction and a second direction different from the first direction and a conductive pattern formed over the main surface of the semiconductor substrate. The conductive pattern includes a first section extending in the first direction, a second section extending in the second direction, and a third section connected between the first and second sections. The third section of the conductive pattern has a first slit extending in a third direction different from the first and second directions.
    Type: Grant
    Filed: April 6, 2022
    Date of Patent: September 19, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Harunobu Kondo, Kazuteru Ishizuka, Wataru Nobehara, Ryosuke Yatsushiro, Makoto Saito
  • Patent number: 11764132
    Abstract: A semiconductor device according to an embodiment comprises a semiconductor element, a first terminal, a plurality of second terminals, and an encloser. The semiconductor element is rectangular. The first terminal has an upper surface to which a back surface of the semiconductor element is bonded. The second terminals are arranged around the first terminal. The second terminals are arranged at four corners of the encloser to be exposed from the bottom surface, and sides of the semiconductor element are opposed to the first side, the second side, the third side, and the fourth side, respectively. The first terminal is apart from the first side surface and the third side surface, a lower surface of the first terminal is exposed from the bottom surface, and the first terminal is partly exposed from the second side surface and the fourth side surface.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: September 19, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Haruhiko Iwabuchi
  • Patent number: 11764131
    Abstract: The present invention provides a small and thin semiconductor device. The semiconductor device flip-chip bonds a semiconductor chip 1 and a lead 6 via a metal bonding portion 5 and includes a sealing resin covering them. The metal bonding portion 5 is provided with a gold-rich bonding layer 5a on the side of a first electrode 3a of the semiconductor chip 1 and a gold-rich bonding layer 5b on the side of a second electrode 3b of the lead 6, and connection between the semiconductor chip 1 and the lead 6 is strengthened, so that the semiconductor device does not require an anchor portion.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: September 19, 2023
    Assignee: ABLIC Inc.
    Inventor: Koji Tsukagoshi
  • Patent number: 11756899
    Abstract: The present disclosure is directed to a lead frame design that includes a copper alloy base material coated with an electroplated copper layer, a precious metal, and an adhesion promotion compound. The layers compensate for scratches or surface irregularities in the base material while promoting adhesion from the lead frame to the conductive connectors, and to the encapsulant by coupling them to different layers of a multilayer coating on the lead frame. The first layer of the multilayer coating is a soft electroplated copper to smooth the surface of the base material. The second layer of the multilayer coating is a thin precious metal to facilitate a mechanical coupling between leads of the lead frame and conductive connectors. The third layer of the multilayer coating is the adhesion promotion compound for facilitating a mechanical coupling to an encapsulant around the lead frame.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: September 12, 2023
    Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Paolo Crema, Jürgen Barthelmes, Din-Ghee Neoh
  • Patent number: 11756908
    Abstract: A package substrate may include an insulation substrate, at least one redistribution layer (RDL) and a redistribution pad. The RDL may be included in the insulation substrate. The redistribution pad may extend from the RDL. The redistribution pad may include at least one segmenting groove in a radial direction of the redistribution pad. Thus, the at least one segmenting groove in the radial direction of the redistribution pad may reduce an area of the redistribution pad. Therefore, application of physical stress to a PID disposed over the redistribution pad may be suppressed, and thus generation of cracks in the PID may be reduced. Further, spreading of the cracks toward the redistribution pad from the PID may also be suppressed, and thus reliability the semiconductor package may be improved.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: September 12, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngkyu Lim, Gookmi Song, Sunguk Lee
  • Patent number: 11749588
    Abstract: A semiconductor device comprises at least one semiconductor die electrically coupled to a set of electrically conductive leads, and package molding material molded over the at least one semiconductor die and the electrically conductive leads. At least a portion of the electrically conductive leads is exposed at a rear surface of the package molding material to provide electrically conductive pads. The electrically conductive pads comprise enlarged end portions extending at least partially over the package molding material and configured for coupling to a printed circuit board.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: September 5, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Michele Derai, Roberto Tiziani
  • Patent number: 11749621
    Abstract: An electronic device includes a die attach pad with a set of cantilevered first leads for down bond connections, a set of second leads spaced apart from the die attach pad, a semiconductor die mounted to the die attach pad and enclosed by a package structure, a set of first bond wires connected between respective bond pads of the semiconductor die and at least some of the first leads, and a set of second bond wires connected between respective further bond pads of the semiconductor die and at least some of the second leads.
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: September 5, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ernesto Pentecostes Rafael, Jr., Dolores Babaran Milo, Michael Flores Milo
  • Patent number: 11749624
    Abstract: A semiconductor device and a method of making the same. The device includes an encapsulant. The device also includes a semiconductor die in the encapsulant. The device further includes electromagnetic radiation transmitting and receiving parts in the encapsulant. The device also includes an intermediate portion having a first surface and a second surface. The first surface is attached to the encapsulant. The device also includes an antenna portion attached to the second surface of the intermediate portion. The antenna portion includes one or more openings for conveying electromagnetic radiation. The intermediate portion includes one or more corresponding openings aligned with the openings of the antenna portion. Each opening of the antenna portion and each corresponding opening of the intermediate portion forms an electrically contiguous passage for conveying the electromagnetic radiation to the electromagnetic radiation transmitting and receiving parts in the encapsulant.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: September 5, 2023
    Assignee: NXP B.V.
    Inventors: Abdellatif Zanati, Michael B. Vincent
  • Patent number: 11742220
    Abstract: An embodiment device package includes a first die, a second die, and a molding compound extending along sidewalls of the first die and the second die. The package further includes redistribution layers (RDLs) extending laterally past edges of the first die and the second die. The RDLs include an input/output (I/O) contact electrically connected to the first die and the second die, and the I/O contact is exposed at a sidewall of the device package substantially perpendicular to a surface of the molding compound opposite the RDLs.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Feng-Cheng Hsu, Shuo-Mao Chen, Jui-Pin Hung, Shin-Puu Jeng
  • Patent number: 11729884
    Abstract: An LED lighting device is disclosed. The LED lighting device includes a first LED circuit and at least one additional LED circuit. The first LED circuit and the at least one additional LED circuit include at least two phosphor coated discretely packaged LEDs connected in series. The phosphor coated discretely packaged LEDs in the first LED circuit emit a different color of light than the phosphor coated discretely packaged LEDs in the at least one additional LED circuit. The LED lighting device also includes a switch configured to be actuated by an end user and provide the end user with a means to produce a change in brightness of at least one of the first LED circuit or the at least one additional LED circuit, or switch at least one of the first LED circuit and the at least one additional LED circuit on or off.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: August 15, 2023
    Assignee: Lynk Labs, Inc.
    Inventors: Michael Miskin, Robert L. Kottritsch
  • Patent number: 11728178
    Abstract: An electronic package and a method for fabrication the same are provided. The method includes: disposing an electronic component on a substrate; forming an encapsulant layer on the substrate to encapsulate the electronic component; and forming a shielding layer made of metal on the encapsulant layer. The shielding layer has an extending portion extending to a lateral side of the substrate along a corner of the encapsulant layer, without extending to a lower side of the substrate. Therefore, the present disclosure prevents the shielding layer from coming into contact with conductive pads disposed on the lower side of the substrate and thereby avoids a short circuit from occurrence.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: August 15, 2023
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shu-Chi Chang, Wei-Ping Wang, Hsien-Lung Hsiao, Kaun-I Cheng
  • Patent number: 11721616
    Abstract: A semiconductor package includes a die pad comprising a die attach surface, a first lead extending away from the die pad, one or more semiconductor dies mounted on the die attach surface, the one or more semiconductor dies comprising first and second bond pads that each face away from the die attach surface, and a distribution element that provides a first transmission path for a first electrical signal between the first lead and the first bond pad of the one or more semiconductor dies and a second transmission path for the first electrical signal between the first lead and the second bond pad of the one or more semiconductor dies. The distribution element comprises at least one integrally formed circuit element that creates a difference in transmission characteristics between the first and second transmission paths.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: August 8, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Stephan Voss, Edward Fuergut, Martin Gruber, Andreas Huerner, Anton Mauder
  • Patent number: 11715719
    Abstract: A semiconductor package is provided. The semiconductor package may include at least one semiconductor chip including a contact pad configured to conduct a current, a conductor element, wherein the conductor element is arranged laterally overlapping the contact pad and with a distance to the contact pad, at least one electrically conductive spacer, a first adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the contact pad, and a second adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the conductor element, wherein the conductor element is electrically conductively connected to a clip or is at least part of a clip, and wherein the spacer is configured to electrically conductively connect the contact pad with the laterally overlapping portion of the conductor element.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: August 1, 2023
    Assignee: Infineon Technologies AG
    Inventors: Edward Fuergut, Ralf Otremba, Irmgard Escher-Poeppel, Martin Gruber