With Structure For Mounting Semiconductor Chip To Lead Frame (e.g., Configuration Of Die Bonding Flag, Absence Of A Die Bonding Flag, Recess For Led) Patents (Class 257/676)
  • Patent number: 11069538
    Abstract: The one end portion of the connector of the semiconductor device includes: a horizontal portion; a first inclined portion that is connected to the horizontal portion and is located closer to the tip end side of the one end than the horizontal portion, and the first inclined portion having a shape inclined downward from the horizontal portion; and a control bending portion that is connected to the first inclined portion and positioned at the tip of the one end portion, and the control bending portion bent downwardly along the bending axis direction. The lower surface of the control bending portion is in contact with an upper surface of the second terminal.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: July 20, 2021
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Soichiro Umeda, Atsushi Kyutoku
  • Patent number: 11056458
    Abstract: A package and method of making a package is disclosed. In one example, the package includes an electronic chip having at least one pad, an encapsulant at least partially encapsulating the electronic chip, and an electrically conductive contact element extending from the at least one pad and through the encapsulant so as to be exposed with respect to the encapsulant. The electrically conductive contact element comprises a first contact structure made of a first electrically conductive material on the at least one pad and comprises a second contact structure made of a second electrically conductive material and being exposed with respect to the encapsulant. At least one of the at least one pad has at least a surface portion which comprises or is made of the first electrically conductive material.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: July 6, 2021
    Assignee: Infineon Technologies AG
    Inventors: Angela Kessler, Andreas Grassmann
  • Patent number: 11049796
    Abstract: A packaging device including a first semiconductor device, a thermal dissipating component, an encapsulation layer, a via, and a pad. The first semiconductor device includes a substrate, an active region, and an electrode. The active region is disposed between the substrate and the electrode. The substrate has a first surface opposite to the active region, and the electrode has a second surface opposite to the active region. The thermal dissipating component is disposed on the first surface of the substrate. The encapsulation layer encloses the second surface of the electrode and a part of the thermal dissipating component, such that another part of the thermal dissipating component is exposed by the encapsulation layer. The pad is disposed on the encapsulation layer. The via is disposed in the encapsulation layer and connects the pad to the electrode.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: June 29, 2021
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Hsin-Chang Tsai, Chia-Yen Lee, Peng-Hsin Lee
  • Patent number: 11037867
    Abstract: A semiconductor module has at least two semiconductor components which are arranged within a housing in each case between two electrical conduction elements and are electrically conductively connected to the electrical conduction elements. The electrical conduction elements respectively have a contact extension that is led out of the housing, wherein two contact extensions arranged in different planes are connected to one another outside the housing via a contact element, which forms a current path between the two contact extensions outside the housing.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: June 15, 2021
    Assignee: Robert Bosch GmbH
    Inventor: Thomas Proepper
  • Patent number: 11036269
    Abstract: A power module and a manufacturing method thereof are disclosed. The power module includes a substrate, a power device, a leading component and a molding component. The substrate includes a first side, a second side and a conductive wire. The power device is disposed on the substrate and electrically connected with the conductive wire. The leading component is disposed on the substrate and includes a first horizontal portion and a vertical portion connected with each other. The vertical portion is electrically connected with the conductive wire. The leading component includes a first contact surface and a second contact surface, which are non-coplanar. The molding component is disposed on the substrate and covers at least portion of the substrate and at least portion of the leading component. The first contact surface and the second contact surface are uncovered by the molding component.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: June 15, 2021
    Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.
    Inventors: Shouyu Hong, Yiqing Ye, Kai Lu, Qingdong Chen, Le Liang, Jianhong Zeng
  • Patent number: 11037895
    Abstract: An electronic component is provided that includes multiple conductive terminals and an insulator integrated with the conductive terminals. A leg part possessed by one of the conductive terminals and a leg part possessed by another one of the conductive terminals are disposed so as to vertically overlap each other. The leg part possessed by one of the conductive terminals and the leg part possessed by another one of the conductive terminals have different lengths, and the tip of the shorter leg part of the two is covered by a thick part of the insulator.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: June 15, 2021
    Assignee: Molex, LLC
    Inventors: Toshihiro Niitsu, Yoshiteru Nogawa
  • Patent number: 11031350
    Abstract: A leadframe having extensions around an outer edge of a die pad are disclosed. More specifically, leadframes are created with a flange formed at the outer edge of the die pad and extending away from the die pad. The flange is bent, such that it is positioned at an angle with respect to the die pad. Leadframes are also created with anchoring posts formed adjacent the outer edge of the die pad and extending away from the die pad. The anchoring posts have a central thickness that is less than a thickness of first and second portions opposite the central portion. When the leadframe is incorporated into a package, molding compound completely surrounds each flange or anchoring post, which increases the bond strength between the leadframe and the molding compound due to increased contact area. The net result is a reduced possibility of delamination at edges of the die pad.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: June 8, 2021
    Assignee: STMICROELECTRONICS, INC.
    Inventor: Jefferson Talledo
  • Patent number: 11031356
    Abstract: A semiconductor die package includes a semiconductor die, a film for improving die warpage bonded to a first face of the semiconductor die, a plurality of electrically conductive bumps formed on a second face of the semiconductor die, a substrate onto which the electrically conductive bumps of the second face of the semiconductor die are bonded to electrically connect the semiconductor die and the substrate, and a mold compound applied these components to form an exposed surface of the semiconductor die package that is coplanar with an exposed surface of the film.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: June 8, 2021
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventors: Jin Seong Kim, Byong Woo Cho, Cha Gyu Song
  • Patent number: 11011687
    Abstract: A light emitting diode (LED) device includes a semiconductor layer and one or more portions of a wafer on which the semiconductor layer was formed, the other portions of the wafer having been removed by an etching process. The semiconductor layer has a front surface that includes a light emitting area. The remnants of the wafer on which the semiconductor layer are disposed on the front surface of the semiconductor layer and define a trench. The trench is positioned such that the light emitting area emits light into the trench. The remnants of the wafer make the LED device more robust and the trench may reduce crosstalk with adjacent LED devices.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: May 18, 2021
    Assignee: Facebook Technologies, LLC
    Inventors: Allan Pourchet, Pooya Saketi, Daniel Brodoceanu, Oscar Torrents Abad
  • Patent number: 11011456
    Abstract: A lead frame includes a die pad having a surface, a first lead post, a first lead, a second lead post, and a second lead. The first lead post has a surface coplanar with the surface of the die pad and is in a first plane. The first lead is coupled to the first lead post. The second lead post is in a second plane different from the first plane. The second lead is coupled to the second lead post.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: May 18, 2021
    Assignee: Infineon Technologies AG
    Inventors: Thai Kee Gan, Lee Shuang Wang, Jo Ean Joanna Chye
  • Patent number: 11011297
    Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: May 18, 2021
    Assignee: ROHM CO., LTD.
    Inventors: Kosei Osada, Isamu Nishimura, Tetsuya Kagawa, Daiki Yanagishima, Toshiyuki Ishikawa, Michihiko Mifuji, Satoshi Kageyama, Nobuyuki Kasahara
  • Patent number: 11004742
    Abstract: In a described example, an integrated circuit (IC) package includes an IC die disposed on a die attach pad; a plurality of leads electrically connected to terminals on the IC die, the leads including a base metal; and molding compound material encapsulating portions of the IC die, the die attach pads, and the plurality of leads; the plurality of leads having a solder joint reinforcement tab. The solder joint reinforcement tabs include a first side, a second side opposite to the first side, a third side, a fourth side opposite to and in parallel to the third side, a fifth side forming an end portion of the solder joint reinforcement tab, the solder joint reinforcement tabs including a solderable metal layer on the second, third and fourth sides and on portions of the fifth side.
    Type: Grant
    Filed: March 19, 2017
    Date of Patent: May 11, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Makoto Shibuya
  • Patent number: 10998256
    Abstract: An apparatus includes a first die attach pad and a second die attach pad. A first die is attached to the first die attach pad and a second die is attached to the second die attach pad. The first die attach pad and the second die attach pad are separated by a gap. A first edge of the first die attach pad adjacent to the gap is thinner than a second edge of the first die attach pad. The first edge of the first die attach pad is opposite the second edge of the first die attach pad. A first edge of the second die attach pad adjacent to the gap is thinner than a second edge of the second die attach pad. The first edge of the second die attach pad is opposite the second edge of the second die attach pad.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: May 4, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Enis Tuncer
  • Patent number: 10991659
    Abstract: Packages including substrate-less integrated components and methods of fabrication are described are described. In an embodiment, a packaging method includes attaching a ground structure to a carrier and a plurality of components face down to the carrier and laterally adjacent to the ground structure. The plurality of components are encapsulated within a molding compound, and the carrier is removed exposing a plurality of component terminals and a plurality of ground structure terminals. A plurality of packages are singulated.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: April 27, 2021
    Assignee: Apple Inc.
    Inventors: Flynn P. Carson, Jun Chung Hsu, Meng Chi Lee, Shatki S. Chauhan
  • Patent number: 10991680
    Abstract: A semiconductor package comprises a land grid array substrate, a first VDMOSFET, a second VDMOSFET, and a molding encapsulation. The land grid array substrate comprises a first metal layer, a second metal layer, a third metal layer, a plurality of vias, and a resin. A series of drain pads at a bottom surface of the semiconductor package follow a “drain 1, drain 2, drain 1, and drain 2” pattern. A method for fabricating a semiconductor package. The method comprises the steps of providing a land grid array substrate; mounting a first VDMOSFET and a second VDMOSFET on the land grid array substrate; applying a wire bonding process; forming a molding encapsulation; and applying a singulation process.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: April 27, 2021
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN), LTD.
    Inventors: Yan Xun Xue, Yueh-Se Ho, Long-Ching Wang, Madhur Bobde, Xiaobin Wang, Lin Chen
  • Patent number: 10985091
    Abstract: This invention provides a semiconductor package, the semiconductor package includes: a semiconductor chip having a connection pad; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure disposed on the semiconductor chip and the encapsulant. The connection structure comprises a first insulation layer, a first redistribution layer disposed on the first insulation layer, and a second insulation layer disposed on the first insulation layer and covering the first redistribution layer. The first redistribution layer has one or more openings. The openings have a shape having a plurality of protrusions, respectively, and B/A is 1.5 or less, where A refers to a thickness of the first redistribution layer, and B refers to a thickness of a region of the second insulation layer covering the first redistribution layer.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: April 20, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Daeyeun Choi, Jaemok Jung, Eunjin Kim, Chilwoo Kwon
  • Patent number: 10971478
    Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a first die on a board, attaching an interposer on a top surface of the first die, and attaching a second die on the top surface of the first die that is adjacent the interposer, wherein the second die is offset from a center region of the first die. A first wire conductive structure may be attached to the second die that extends from the second die to a top surface of the interposer. A second wire conductive structure is attached to the interposer and extends from the interposer to the board.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventor: Aiping Tan
  • Patent number: 10971433
    Abstract: A surface mounted type leadframe includes a conductive base and an insulating material layer. The conductive base includes at least three connecting pads spaced apart from each other. First surface of the connecting pads are configured to form die bonding regions, and second surfaces of the connecting pads opposite to the first surfaces are configured to form soldering regions. The insulating material layer at least partially covers the first surfaces, surrounds the die bonding regions, and is filled in a gap between each two adjacent connecting pads. A photoelectric device with multi-chips adopting the surface mounted type leadframe is also provided.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: April 6, 2021
    Assignee: KAISTAR LIGHTING (XIAMEN) CO., LTD.
    Inventor: Jingqiong Zhang
  • Patent number: 10971434
    Abstract: Disclosed is a device including a lead frame having a body with a top surface and a bottom surface and lead fingers. Each lead finger has a first end and a second end. A semiconductor die is coupled to the body. A first flag is a first exposed portion of the body and integral with the first end of a first lead finger. The first flag and the first lead finger are a continuous material. A second flag is a second exposed portion of the body and integral with the first end of a second lead finger. The second flag and the second lead finger are a continuous material. An encapsulant covers the die, the bottom surface of the body, the first end of the lead fingers and a portion of the top surface of the body. The flags are separated and electrically isolated from one another by the encapsulant.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: April 6, 2021
    Assignee: Silanna Asia Pte Ltd
    Inventors: Ariel Tan, Ren Huei Tzeng
  • Patent number: 10964613
    Abstract: A device includes a die comprising a sensor. The device also includes a substrate that is coupled to the die via the electrical coupling. The device further includes a packaging container. The packaging container and the substrate form a housing for the die. The packaging container comprises an opening that exposes at least a portion of the die to an environment external to the housing. The exposed surfaces of the die, interior of the housing, the electrical coupling, and the substrate to the environment external to the housing through the opening are coated with a conformal film. The conformal film prevents liquid, e.g., water, gas, etc., contact to the exposed surfaces of the die, the electrical coupling and the substrate.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: March 30, 2021
    Assignee: InvenSense, Inc.
    Inventor: Calin Miclaus
  • Patent number: 10957613
    Abstract: A semiconductor module includes a base plate made of a metal, an insulating frame provided on a peripheral edge portion of the base plate, a lead made of a metal and provided on the frame, and a semiconductor device mounted on the base plate in a space surrounded by the frame, wherein the frame is fixed to the base plate by a bonding material containing silver, the frame has concave portions formed in an inner portion which is a corner portion on a space side and an outer portion which is a corner portion on a side opposite to the inner portion in a surface thereof which faces the base plate, and the concave portions are filled with a coating material.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: March 23, 2021
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Tomoki Ohno
  • Patent number: 10950527
    Abstract: A chip mounting portion included in a semiconductor device has a region including a semiconductor chip in plan view. When an average surface roughness of the region is “Ra”, 0.8 ?m?Ra?3.0 ?m holds.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: March 16, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shoji Hashizume, Yasushi Takahashi
  • Patent number: 10937763
    Abstract: A semiconductor package includes a leadframe having a first island and second island each having an upper surface corresponding with an upper surface of the leadframe. One or more tie bars couple the first island with the second island. At least one tie bar has a protrusion extending from the upper surface of the leadframe and configured to substantially prevent a flow of a solder between the first and second islands. A first die couples with the leadframe at the first island and a second die couples with the leadframe at the second island. At least one of the tie bars has a recess at a lower surface of the leadframe. The leadframe includes a slit between the first and second island.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: March 2, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Masakazu Watanabe
  • Patent number: 10923457
    Abstract: A multi-die module includes a first die with a first device and a second die with a second device. The multi-die module also includes a contactless coupler configured to convey signals between the first device and the second device. The multi-die module also includes a coupling loss reduction structure.
    Type: Grant
    Filed: December 23, 2018
    Date of Patent: February 16, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Benjamin Stassen Cook, Bichoy Bahr, Baher Haroun
  • Patent number: 10916622
    Abstract: In various embodiments, the present disclosure provides capacitors and methods of forming capacitors. In one embodiment, a capacitor includes a substrate, a first electrode on the substrate, a second electrode, and a first dielectric layer. A portion of the first electrode is exposed in a contact region. The first dielectric layer includes a first dielectric region between the first electrode and the second electrode, and a second dielectric region between the first dielectric region and the contact region. The second dielectric region is contiguous to the first dielectric region, and a surface of the second dielectric region defines a surface path between the first electrode and the contact region. The second dielectric region has a plurality of grooves that increase a spatial extension of said surface path.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: February 9, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventors: Davide Giuseppe Patti, Giuseppina Valvo, DelfoNunziato Sanfilippo
  • Patent number: 10910294
    Abstract: A packaged electronic device includes a substrate comprising a die pad and a lead spaced apart from the die. An electronic device is attached to the die pad top side. A conductive clip is connected to the substrate and the electronic device, and the conductive clip comprises a plate portion attached to the device top side with a conductive material, a clip connecting portion connected to the plate portion and the lead, and channels disposed to extend inward from a lower side of the plate portion above the device top side. The conductive material is disposed within the channels. In another example, the plate portion comprises a lower side having a first sloped profile in a first cross-sectional view such that an outer section of the first sloped profile towards a first edge portion of the plate portion is spaced away from the electronic device further than an inner section of the first sloped profile towards a central portion of the plate portion. Other examples and related methods are also disclosed herein.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: February 2, 2021
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventor: Kenji Nishikawa
  • Patent number: 10910295
    Abstract: The present disclosure is directed to a leadframe package having solder wettable sidewalls that is formed using a pre-molded leadframe and methods of manufacturing the same. A metal plated leadframe with a plurality of recesses and a plurality of apertures is placed into a top and bottom mold tool. A molding compound is then formed in the plurality of recesses and apertures in the leadframe to form a pre-molded leadframe. A plurality of die and wires are coupled to the pre-molded leadframe and the resulting combination is covered in an encapsulant. Alternatively, a bare leadframe can be processed and the metal layer can be applied after encapsulation. A saw or other cutting means is used for singulation to form leadframe packages. Each resulting leadframe package has a solder wettable sidewall for improving the strength of solder joints between the package and a circuit board.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: February 2, 2021
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Aaron Cadag, Ernesto Antilano, Jr., Ela Mia Cadag
  • Patent number: 10903138
    Abstract: A semiconductor device includes a substrate constituted of an insulator, a first conductor film provided on a surface of the substrate; a semiconductor chip including a first electrode and a second electrode, the first electrode being connected to the first conductor film; and an external connection terminal including an inner end portion and an outer end portion. The inner end portion is located between the substrate and the semiconductor chip and is connected to the second electrode. The external connection terminal further includes an intermediate portion located between the inner end portion and the outer end portion and joined to the surface of the substrate. A distance between the intermediate portion of the external connection terminal and the substrate is greater than a distance between the inner end portion of the external connection terminal and the substrate.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: January 26, 2021
    Assignee: DENSO CORPORATION
    Inventors: Akinori Sakakibara, Takanori Kawashima
  • Patent number: 10903172
    Abstract: A semiconductor package formed utilizing multiple etching steps includes a lead frame, a die, and a molding compound. The lead frame includes leads and a die pad. The leads and the die pad are formed from a first conductive material by the multiple etching steps. More specifically, the leads and the die pad of the lead frame are formed by at least three etching steps. The at least three etching steps including a first etching step, a second undercut etching step, and a third backside etching step. The second undercut etching step forming interlocking portions at an end of each lead. The end of the lead is encased in the molding compound. This encasement of the end of the lead with the interlocking portion allows the interlocking portion to mechanically interlock with the molding compound to avoid lead pull out. In addition, by utilizing at least three etching steps the leads can be formed to have a height that is greater than the die pad of the lead frame.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: January 26, 2021
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Aaron Cadag, Lester Joseph Belalo, Ela Mia Cadag
  • Patent number: 10902867
    Abstract: An approach to forming an electronic device assembly that includes a plurality of interconnect pads on an electronic device, an interconnect die with a first set of interconnect pads adjacent to a first edge of the interconnect die connecting to a second set of interconnect pads adjacent to a second edge of the interconnect die, where a first set of connections between the plurality of interconnects on the electronic device and the first set of interconnect pads on the interconnect die occurs. Furthermore, the electronic assembly includes a second set of connections between the second set of interconnects on the interconnect die and a set of interconnect pads on a flex cable.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: January 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Robert Biskeborn, Calvin Shyhjong Lo
  • Patent number: 10886201
    Abstract: A substrate includes a first metal layer, a second metal layer, a third metal layer and an insulation layer surrounding the first metal layer, the second metal layer and the third metal layer. The first power component is electrically connected to the first metal layer. The second power component is electrically connected to the second metal layer. The shortest distance between the first metal layer exposed to a second surface of the insulation layer and the second metal layer exposed to the second surface is a first distance, the shortest distance between a first metal layer of the insulation layer exposed to the first surface and the second metal layer exposed to the first surface is a second distance, and a ratio value of the first distance to the second distance ranges between 1.25 and 1.4.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: January 5, 2021
    Assignee: EPISTAR CORPORATION
    Inventors: Shu-Han Yang, Sheng-Che Chiou, Jai-Tai Kuo, Po-Chang Chen
  • Patent number: 10886213
    Abstract: A semiconductor device has a coil and wirings under the coil. In addition, a distance between the upper face of the wirings and the bottom face of the coil is 7 ?m or larger, and the wirings have a plurality of linear wiring parts each wiring width of which is 1 ?m or smaller. In addition, the linear wiring parts do not configure a loop wiring, and the coil and the linear wiring parts are overlapped with each other in planar view.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: January 5, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Teruhiro Kuwajima, Yasutaka Nakashiba, Akira Matsumoto, Akio Ono, Tetsuya Iida
  • Patent number: 10886198
    Abstract: A device comprises a base, a die, leads, and an electrically-insulating die housing covering the die. The base comprises a die mounting section in which the die is mounted. The leads extend away from the die mounting section and are electrically connected to the die. The base further comprises a base mounting section and a recessed section. The recessed section comprises a recess between the die mounting section and the base mounting section. The base further comprises a first side, a second side opposing the first side, and a thickness measured between the first and second sides. The thickness of the base throughout the recessed section is less than the thickness of the base throughout the base mounting section. The base further comprises an opening extending at least through the base mounting section from the first side to the second side.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: January 5, 2021
    Assignee: CREE, INC.
    Inventors: Sung Chul Joo, Bradley Millon, Erwin Cohen
  • Patent number: 10866120
    Abstract: A sensor, which is based on a coupling between a printed circuit board inductance and a number of attachment inductances that are applied using SMD technology.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: December 15, 2020
    Assignee: Continental Teves AG & Co. oHG
    Inventor: Heinrich Acker
  • Patent number: 10861810
    Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Fan Huang, Hui-Chi Chen, Kuo-Chin Chang, Chien-Huang Yeh, Hong-Seng Shue, Dian-Hau Chen, Yen-Ming Chen
  • Patent number: 10854590
    Abstract: An apparatus is described that includes a semiconductor die package. The semiconductor die package includes a semiconductor die package substrate having a top side and a bottom side. The semiconductor die package includes I/O balls on the bottom side of the semiconductor die package substrate. The I/O balls are to mount to a planar board. The semiconductor die package includes a first semiconductor die mounted on the bottom side of the semiconductor die package substrate. The first semiconductor die is vertically located between the bottom side of the semiconductor die package substrate and a second semiconductor die that is a part of the semiconductor die package.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: December 1, 2020
    Assignee: Intel IP Corporation
    Inventors: Sven Albers, Klaus Reingruber, Richard Patten, Georg Seidemann, Christian Geissler
  • Patent number: 10840161
    Abstract: A method of manufacturing a semiconductor package substrate includes forming a trench in one surface of a base substrate formed of a conductive material, performing a first filling operation of filling the trench with resin, performing a first curing operation of semi-curing the resin filled in the first filling operation, performing a second filling operation of additionally filling resin on a semi-cured resin, performing a second curing operation of fully curing the resin, removing the resin exposed from the trench, and etching an opposite surface of the base substrate to expose at least part of the resin filling the trench.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: November 17, 2020
    Assignee: HAESUNG DS CO., LTD.
    Inventors: In Seob Bae, Hyeok Jin Jeon
  • Patent number: 10832992
    Abstract: A method includes providing a carrier, depositing a die attach material on the carrier, and arranging a semiconductor die on the die attach material, wherein a main surface of the semiconductor die facing the die attach material at least partly contacts the die attach material, wherein immediately after arranging the semiconductor die on the die attach material, a first maximum extension of the die attach material over edges of the main surface is less than about 100 micrometers.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: November 10, 2020
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Giovanni Ragasa Garbin, Chen Wen Lee, Benjamin Reichert, Peter Strobel
  • Patent number: 10832999
    Abstract: Packaging methods for semiconductor devices are disclosed. A method of packaging a semiconductor device includes providing a workpiece including a plurality of packaging substrates. A portion of the workpiece is removed between the plurality of packaging substrates. A die is attached to each of the plurality of packaging substrates.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: November 10, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Wei Huang, Wei-Hung Lin, Chih-Wei Lin, Chun-Cheng Lin, Meng-Tse Chen, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 10832993
    Abstract: A leadless multichip semiconductor device includes a metal substrate having a through-hole aperture with an outer ring for holding a bottom semiconductor die with an inner row and an outer row of metal pads. The bottom semiconductor die has a back side metal (BSM) layer on its bottom side and a top side with bond pads mounted top side up on the ring. A metal die attach layer is directly between the BSM layer and walls of the metal substrate providing a die attachment that fills a bottom portion of the aperture. Bond wires are between the inner metal pads and the bond pads. A top semiconductor die has top bond pads mounted top side up on a dielectric adhesive on the bottom semiconductor die. Pins connect the top bond pads to the outer metal pads. A mold compound provides isolation between adjacent ones of the metal pads.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: November 10, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nazila Dadvand, Sreenivasan Koduri, Benjamin Stassen Cook
  • Patent number: 10825756
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor chip, and a die pad. The die pad has a first surface. The semiconductor chip is bonded on the first surface using a paste including a metal particle. A concave structure is provided in the first surface. The concave structure is positioned directly under each of a plurality of sides of the semiconductor chip and extends along each of the plurality of sides.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: November 3, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hideharu Kojima, Yoshiharu Takada
  • Patent number: 10818601
    Abstract: A semiconductor device includes a semiconductor substrate SB and a wiring structure formed on a main surface of the semiconductor substrate SB. The uppermost first wiring layer among a plurality of wiring layers included in the wiring structure includes a pad PD, and the pad PD has a first region for bonding a copper wire and a second region for bringing a probe into contact with the pad. A second wiring layer that is lower by one layer than the first wiring layer among the plurality of wiring layers included in the wiring structure includes a wiring line M6 arranged immediately below the pad PD, the wiring line M6 is arranged immediately below a region other than the first region of the pad PD, and no conductor pattern in the same layer as a layer of the wiring line M6 belong is formed immediately below the first region of the pad PD.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: October 27, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshinori Deguchi, Akinobu Watanabe
  • Patent number: 10811579
    Abstract: An optoelectronic component includes a light emitting semiconductor chip, including an emission side and comprising an underside, wherein the optoelectronic component is configured to emit light via the emission side, the optoelectronic component including an insulating layer, the light emitting semiconductor chip is embedded into the insulating layer, the light emitting semiconductor chip including two electrical contact locations, the contact locations face away from the emission side, a first and a second electrically conductive contact layer are provided, respectively, an electrically conductive contact layer electrically conductively connects to a contact location of the semiconductor chip, the electrically conductive contact layers are arranged in the insulating layer, the first electrically conductive contact layer adjoins a first side face of the optoelectronic component, and the second electrically conductive contact layer adjoins a second side face of the optoelectronic component.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: October 20, 2020
    Assignee: OSRAM OLED GmbH
    Inventors: Dominik Scholz, Siegfried Herrmann
  • Patent number: 10797011
    Abstract: A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads, forming a conductive pillar in each of the openings of the resist layer, forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer, filling molten solder in each of the openings in which the conductive layers has been formed and removing the resist layer.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: October 6, 2020
    Assignee: International Business Machines Corporation
    Inventors: Toyohiro Aoki, Takashi Hisada, Hiroyuki Mori, Eiji Nakamura, Yasumitsu Orii
  • Patent number: 10790219
    Abstract: According to one embodiment, a semiconductor package includes a die pad, a semiconductor chip, a lead frame, and an insulating part. The semiconductor chip is provided on the die pad. The lead frame is separated from the die pad. The lead frame is electrically connected to a terminal of the semiconductor chip. The lead frame includes a first part and a second part disposed between the first part and the die pad. An upper surface of the first part is located below an upper surface of the second part. The insulating part is provided on the die pad, the semiconductor chip, and the second part. The insulating part seals the semiconductor chip.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: September 29, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihisa Imori, Kenji Yamada
  • Patent number: 10784186
    Abstract: A semiconductor module includes a die pad frame; a semiconductor chip disposed in a chip region on an upper surface of the die pad frame, the semiconductor chip having an upper surface on which a first electrode is disposed and a lower surface on which a second electrode is disposed; a conductive connection member for die pad disposed between the second electrode of the semiconductor chip and the upper surface of the die pad frame, the conductive connection member for die pad electrically connecting the second electrode of the semiconductor chip and the upper surface of the die pad frame; a first clip frame disposed on the upper surface of the semiconductor chip; a first clip conductive connection member disposed between the first electrode on the semiconductor chip and a lower surface of the first clip frame, the first clip conductive connection member electrically connecting the first electrode of the semiconductor chip and the lower surface of the first clip frame; and a sealing resin for sealing the semic
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: September 22, 2020
    Assignee: KATOH ELECTRIC CO., LTD.
    Inventors: Hiroyoshi Urushihata, Takashi Shigeno, Eiki Ito, Wataru Kimura, Hirotaka Endo, Toshio Koike, Toshiki Kouno
  • Patent number: 10777479
    Abstract: A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an element-mounting region between them. An inner lead portion has first inner leads connected to the first outer leads and second inner leads connected to the second outer leads. At least either the first or second inner leads are routed in the element-mounting region. An insulation resin is filled in the gaps between the inner leads located on the element-mounting region. A semiconductor device is configured with semiconductor elements mounted on both the top and bottom surfaces of the lead frame.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: September 15, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Yoshiaki Goto
  • Patent number: 10777507
    Abstract: A semiconductor device having a plurality of wiring layers including a first wiring layer and a second wiring layer, with the first wiring layer being the uppermost layer and including a pad PD that has a first region for bonding a copper wire, and a second region for bringing a probe into contact with the pad. The second wiring layer is one layer below the first wiring layer and includes a first wiring line arranged immediately below the second region of the pad, the second wiring layer having no conductor pattern at a region overlapping with the first region of the pad PD.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: September 15, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshinori Deguchi, Akinobu Watanabe
  • Patent number: 10777489
    Abstract: A semiconductor module includes a die pad frame; a semiconductor chip disposed in a chip region on an upper surface of the die pad frame, the semiconductor chip having an upper surface on which a first electrode is disposed and a lower surface on which a second electrode is disposed; a conductive connection member for die pad disposed between the second electrode of the semiconductor chip and the upper surface of the die pad frame, the conductive connection member for die pad electrically connecting the second electrode of the semiconductor chip and the upper surface of the die pad frame; and a sealing resin for sealing the semiconductor chip, the die pad frame, and the conductive connection member for die pad.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: September 15, 2020
    Assignee: KATOH ELECTRIC CO., LTD.
    Inventors: Hiroyoshi Urushihata, Takashi Shigeno, Eiki Ito, Wataru Kimura, Hirotaka Endo, Toshio Koike, Toshiki Kouno
  • Patent number: 10777490
    Abstract: A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. The bonding surface includes a first region to which a bonding portion of the wire is bonded, a second region to which another bonding portion of the wire is bonded, and a third region between the first region and the second region. A width of the third region is smaller than a width of the first region and a width of the second region.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: September 15, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Yukihiro Sato, Toshinori Kiyohara