With Structure For Mounting Semiconductor Chip To Lead Frame (e.g., Configuration Of Die Bonding Flag, Absence Of A Die Bonding Flag, Recess For Led) Patents (Class 257/676)
  • Patent number: 10354943
    Abstract: An example multi-branch terminal for an integrated circuit (IC) package is described herein. An example multi-branch terminal of an integrated circuit (IC), may include a first branch that may include an active bonding with a chip of the IC, wherein the active bonding may include a wire bonded to the chip of the IC; and a second branch that may include a passive bonding with the chip of the IC, wherein the passive bonding may include a capacitor bonded to the second branch and a first terminal of the IC.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: July 16, 2019
    Assignee: Infineon Technologies AG
    Inventors: Thomas Stoek, Chii Shang Hong, Chiew Li Tai, Edmund Sales Cabatbat
  • Patent number: 10347566
    Abstract: A carrier and the clip are used to produce a packaging having a lead frame by connection to the chip using sintering of the solidified sintering pastes in one work step. The carrier may be a lead frame and a clip for at least one semiconductor element has at least one functional surface for connecting to the semiconductor element and a plurality of connections. The material of the earlier or of the clip includes a metal and a layer made of a solidified sintering paste. The sintering paste may contain silver and/or a silver compound. The sintering paste is arranged on the functional surface. The carrier or clip and the layer made of sintering paste form an intermediate product that can be connected to the semiconductor element.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: July 9, 2019
    Assignee: HERAEUS DEUTSCHLAND GMBH & CO. KG
    Inventors: Michael Benedikt, Thomas Krebs, Michael Schäfer, Wolfgang Schmitt, Andreas Hinrich, Andreas Klein, Alexander Brand, Martin Bleifuss
  • Patent number: 10339257
    Abstract: In a layout design of a printed circuit board, more accurate bypass capacitor arrangement that has taken into consideration a wiring within a package of an IC is implemented. An information processing apparatus according to the present invention includes: a die pad specifying unit configured to specify a power source pad of a die and a ground pad of the die from design information on a printed circuit board; a bypass capacitor specifying unit configured to specify a bypass capacitor that is arranged on the printed circuit board from the design information; and a unit configured to derive an evaluation value for evaluating the arrangement of the specified bypass capacitor based on the design information, information on the specified power source pad of the die and ground pad of the die, and information on the specified bypass capacitor.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: July 2, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Toshitaka Nojima, Toshisato Sadamatsu, Shinichi Hama
  • Patent number: 10340309
    Abstract: A light emitting device includes a substrate and a plurality of light emitting cells disposed on the substrate. Each light emitting cell includes a first semiconductor layer and a second semiconductor layer, an active layer between the first and the second semiconductors, a conductive material on the second semiconductor layer, an inclined surface, a first insulation layer overlaps each light emitting cell, an electrically conductive material overlaps the first insulation layer to couple two of the plurality of light emitting cells, and a second insulation layer overlaps the electrically conductive material. A light-transmitting material is used in both the first insulation layer and the second insulation layer. The inclined surface is continuous and has a slope of approximately 20° to approximately 80° from a horizontal plane based on the substrate.
    Type: Grant
    Filed: February 18, 2018
    Date of Patent: July 2, 2019
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Jong Lam Lee, Jae Ho Lee, Yeo Jin Yoon, Eu Jin Hwang, Dae Won Kim
  • Patent number: 10340207
    Abstract: According to one embodiment, a semiconductor package includes a die pad, a semiconductor chip, a lead frame, and an insulating part. The semiconductor chip is provided on the die pad. The lead frame is separated from the die pad. The lead frame is electrically connected to a terminal of the semiconductor chip. The lead frame includes a first part and a second part disposed between the first part and the die pad. An upper surface of the first part is located below an upper surface of the second part. The insulating part is provided on the die pad, the semiconductor chip, and the second part. The insulating part seals the semiconductor chip.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: July 2, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihisa Imori, Kenji Yamada
  • Patent number: 10325895
    Abstract: It is an object of the present invention to provide a semiconductor module in which a bonded portion has high reliability, and that has a small area. A semiconductor module includes a plurality of metal plates extending in a horizontal direction and stacked in a vertical direction, at least one switching element, and at least one circuit element. The at least one switching element is bonded between two of the plurality of metal plates, facing each other in a vertical direction. The at least one circuit element is bonded between two of the plurality of metal plates, facing each other in a vertical direction. Disposed between the plurality of metal plates is an insulating material. At least one of the plurality of metal plates is bonded to the at least one switching element and the at least one circuit element.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: June 18, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kenta Nakahara
  • Patent number: 10319698
    Abstract: A microelectronic device package including multiple layers of stacked die. Multiple die layers in the package can include two or more die. At least two die in a first layer will be laterally spaced from one another to define a first gap extending in a first direction; and at least two die in a second layer will be laterally spaced from one another to define a second gap extending in a second direction that is angularly offset from the first direction. The first and second directions can be perpendicular to one another.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Min Suet Lim, Jackson Chung Peng Kong
  • Patent number: 10312182
    Abstract: A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: June 4, 2019
    Assignee: ADVANCED INTERCONNECT SYSTEMS LIMITED
    Inventors: Haruki Ito, Nobuaki Hashimoto
  • Patent number: 10312212
    Abstract: An apparatus for enhancing the thermal performance of semiconductor packages effectively. The concept of this invention is to provide silicon nanowires on the backside of an integrated circuit die to directly attach the die to the substrate, thereby improving the interface between die and substrate, and thus enhancing thermal performance and enhancing reliability by improving adhesion.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: June 4, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Rongwei Zhang
  • Patent number: 10297534
    Abstract: A single chip integrated circuit (IC) package includes a die pad, and a spacer ring on the die pad defining a solder receiving area. A solder body is on the die pad within the solder receiving area. An IC die is on the spacer ring and is secured to the die pad by the solder body within the solder receiving area. Encapsulating material surrounds the die pad, spacer ring, and IC die. For a multi-chip IC package, a dam structure is on the die pad and defines multiple solder receiving areas. A respective solder body is on the die pad within a respective solder receiving area. An IC die is within each respective solder receiving area and is held in place by a corresponding solder body. Encapsulating material surrounds the die pad, dam structure, and plurality of IC die.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: May 21, 2019
    Assignee: STMICROELECTRONICS PTE LTD
    Inventor: Wing Shenq Wong
  • Patent number: 10297539
    Abstract: The melting of die-bonding solder material is prevented even when soldering a surface-mount component formed using the die-bonding solder material on a printed circuit board using a mounting solder material. The surface-mount component formed using (Sn—Sb)-based solder material having high melting point as the solder material for die pad, the (Sn—Sb)-based solder material containing Cu not more than a predetermined quantity of Cu constituent and a main ingredient thereof being Sn, is soldered on a board terminal portion of a circuit board using (Sn—Ag—Cu—Bi)-based solder material as the mounting solder material with the solder material being applied on the terminal portion. The melting of die-bonding solder material is prevented even at the heating temperature (240 degrees C. or less) of a reflow furnace.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: May 21, 2019
    Assignee: Senju Metal Industry Co., Ltd.
    Inventors: Minoru Ueshima, Minoru Toyoda
  • Patent number: 10290563
    Abstract: The specification discloses a technique for preventing a bonding material from reaching the upper and lower surfaces of a semiconductor chip in bonding the semiconductor chip using the bonding material. A die pad of the technique disclosed in the specification includes the following: a die pad substrate; a first projection disposed on the upper surface of the die pad substrate, the first projection having a pedestal shape; a second projection disposed on the upper surface of the die pad substrate so as to surround at least part of the first projection in a plan view, the second projection having a bank shape; and a third projection disposed on the upper surface of the die pad substrate so as to surround at least part of the second projection in a plan view, the third projection having a bank shape.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: May 14, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kazuhiko Sakutani
  • Patent number: 10290608
    Abstract: Methods and apparatus for a signal isolator having first and second dies separated by a voltage barrier region, wherein transmit and receive paths of the first and second dies provide bi-directional transfer of feedback and/or diagnostic signals between the first and second die. In embodiments, transmitter refresh signals and receiver refresh signals are exchanged to detect fault conditions.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: May 14, 2019
    Assignee: Allegro MicroSystems, LLC
    Inventors: Alexander Latham, Joseph James Judkins, III
  • Patent number: 10283438
    Abstract: A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: May 7, 2019
    Assignee: ADVANCED INTERCONNECT SYSTEMS LIMITED
    Inventors: Haruki Ito, Nobuaki Hashimoto
  • Patent number: 10278281
    Abstract: A MEMS thermal stress isolation system is disclosed. The MEMs thermal stress isolation system is a MEMS embedded hardware implementation designed to isolate the sensitive sensor die from external stresses caused by rigid attachment to packaging and to allow the sensor to perform with improved immunity to the negative impacts of rigid sensor packaging attachment. A planar, micro-etched interface structure is integrated into the MEMS wafer stack, which serves as the mechanical connection between the MEMS sensor and the external packaging.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: April 30, 2019
    Assignee: Garmin International, Inc.
    Inventors: Kirill V. Shcheglov, Nolan F. Maggipinto, David Smukowski, Chien-Heng Sun
  • Patent number: 10276531
    Abstract: The present disclosure relates to a semiconductor device. In some embodiments, the semiconductor device has a first plurality of conductive pads arranged over a first substrate. A conductive solder material is arranged over and is electrically connected to the first plurality of conductive pads. A first boundary structure separates each conductive pad of the first plurality of conductive pads from an adjacent conductive pad of the first plurality of conductive pads. A die is arranged over the first substrate. The die has outermost sidewalls that are laterally separated from first and second ones of the first plurality of conductive pads by the first boundary structure.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien Ling Hwang, Yeong-Jyh Lin, Bor-Ping Jang, Hsiao-Chung Liang
  • Patent number: 10269745
    Abstract: A package includes a corner, a device die, a molding material molding the device die therein, and a plurality of bonding features. The plurality of bonding features includes a corner bonding feature at the corner, wherein the corner bonding feature is elongated. The plurality of bonding features further includes an additional bonding feature, which is non-elongated.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsien-Wei Chen
  • Patent number: 10269775
    Abstract: A semiconductor device has a first board (10); and an intermediate layer (20) being provided on the first board (10) and having a plurality of connectors (31), (41). The first board (10) has a positioning section (5) that positions the intermediate layer (20). The intermediate layer (10) is provided with a positioning insertion section (37), (47), into which the positioning section (5) is inserted.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: April 23, 2019
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventor: Kosuke Ikeda
  • Patent number: 10262923
    Abstract: A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: April 16, 2019
    Assignee: ADVANCED INTERCONNECT SYSTEMS LIMITED
    Inventors: Haruki Ito, Nobuaki Hashimoto
  • Patent number: 10247585
    Abstract: A component for a sensor having a sensor element and having an output interface for the outputting of an electrical signal, which is dependent on a physical variable, from the sensor element to the output interface, including—a circuit with at least one first signal path for receiving the electrical signal from the sensor element and for conducting the electrical signal to the output interface, and a second signal path, which differs from the first signal path, for conducting the electrical signal to the output interface, —wherein an activity of the first signal path or of the second signal path is dependent on a position of the component in the sensor.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: April 2, 2019
    Assignee: Continental Teves AG & oHG
    Inventors: Svenja Raukopf, Jakob Schillinger, Michael Schulmeister
  • Patent number: 10243515
    Abstract: A semiconductor device includes an electronic component that includes an oscillator and has terminals on one face. A semiconductor chip is electrically connected to the electronic component and also includes terminals on one face thereof. The electronic component and the semiconductor chip are mounted to a mounting base such that the terminals of the electronic component and the terminals of the semiconductor chip face in the same direction. First bonding wires are connected to the terminals of the semiconductor chip, and second bonding wires having an apex height smaller than that of the first bonding wires connect the terminals of the electronic component to the terminals of the semiconductor chip. A sealing member completely seals within at least the electronic component.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: March 26, 2019
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventors: Kengo Takemasa, Yuichi Yoshida, Toshihisa Sone, Kazuya Yamada, Akihiro Takei
  • Patent number: 10243126
    Abstract: A light emitting device mounting board block includes: a lead frame having a plate-shape, the lead frame having a first surface, and a second surface located opposite to the first surface; and a resin molded body located on the first surface of the lead frame, the resin molded body having a recessed portion therein. The resin molded body includes a first lateral wall, a second lateral wall, a third lateral wall and a fourth lateral wall, the first and second lateral walls extending in a length direction, the third and fourth lateral walls extending in a width direction.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: March 26, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Hideaki Tosuke, Hideki Hayashi
  • Patent number: 10236243
    Abstract: An electronic component includes an electronic device, a mounting member for mounting the electronic device and having a first connecting portion electrically coupled to the electronic device and a second connecting portion, and a sealing member covering the electronic device and the first connecting portion. The mounting member includes a substrate having a mounting surface mounting the electronic device, a first conductive layer disposed on the mounting surface, and a second conductive layer. The first conductive layer includes a first conductive pattern having the first connecting portion and a second conductive pattern having the second connecting portion and spaced apart from the first conductive pattern in a second direction along the mounting surface. The second conductive pattern is connected to the first conductive pattern through a third conductive pattern included in the second conductive layer. The sealing member does not cover the second conductive pattern.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: March 19, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takashi Miyake, Masamichi Masuda
  • Patent number: 10237977
    Abstract: A method includes forming a multi-stacked electronic device having two or more electronic components, each of the electronic components includes a leadframe, the leadframes of each electronic component are physically joined together using a non-solder metal joining process to form a joint, and the joint is located outside a solder connection region.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: March 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ai Kiar Ang, Michael Lauri
  • Patent number: 10229893
    Abstract: A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: March 12, 2019
    Assignee: VISHAY-SILICONIX
    Inventors: Frank Kuo, Suresh Belani
  • Patent number: 10217731
    Abstract: A method produces a plurality of optoelectronic modules, and includes: A) providing a metallic carrier assembly with a plurality of carrier units; B) applying a logic chip, each having at least one integrated circuit, to the carrier units; C) applying emitter regions that generate radiation, which can be individually electrically controlled; D) covering the emitter regions and the logic chips with a protective material; E) overmolding the emitter regions and the logic chips so that a cast body is formed, which joins the carrier units, the logic chips and the emitter regions to one another; F) removing the protective material and applying electrical conductor paths to the upper sides of the logic chips and to a cast body upper side; and G) dividing the carrier assembly into the modules.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: February 26, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Frank Singer, Thomas Schwarz, Stefan Grötsch
  • Patent number: 10217713
    Abstract: The present disclosure provides for embodiments of packaged semiconductor devices. In one embodiment, a packaged semiconductor device for a die includes an exposed structure. The die has an active surface and a backside surface opposite the active surface. A first surface of the exposed structure is joined to die attach material, and the die attach material is further joined to the backside surface of the die. The exposed structure includes a plurality of openings through the exposed structure within a perimeter of the die, and the die is exposed through the plurality of openings.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: February 26, 2019
    Assignee: NXP USA, Inc.
    Inventors: Sheila F. Chopin, Thomas H. Koschmieder, Varughese Mathew
  • Patent number: 10211130
    Abstract: A semiconductor device includes a plurality of leads, a semiconductor element electrically connected to the leads and supported by one of the leads, and a sealing resin covering the semiconductor element and a part of each lead. The sealing resin includes a first edge, a second edge perpendicular to the first edge, and a center line parallel to the first edge. The reverse surfaces of the respective leads include parts exposed from the sealing resin, and the exposed parts include an outer reverse-surface mount portion and an inner reverse-surface mount portion that are disposed along the second edge of the sealing resin. The inner reverse-surface mount portion is closer to the center line of the sealing resin than is the outer reverse-surface mount portion. The outer reverse-surface mount portion is greater in area than the inner reverse-surface mount portion.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: February 19, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Katsuhiro Iwai
  • Patent number: 10211132
    Abstract: A leadframe (100) comprises a frame (101) of sheet metal in a first planar level, where the frame has metallic leads (110) and a first metallic pad (120) extending inward from the frame, and the first pad is tied to the frame by first metallic straps (120a). The leadframe further has a second metallic pad (130) in a second planar level parallel to and spaced from the first level, where the second pad is tied by second metallic straps (132) to the frame. In addition, the leadframe has a third metallic pad (140) in a third planar level parallel to and spaced from the second level and additively from the first level, where the third pad is tied by third metallic straps (131) to the second pad.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: February 19, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chia-Yu Chang, Chih-Chien Ho, Steven Su
  • Patent number: 10192756
    Abstract: A method of processing a lead frame having at least one electrically conductive contact section includes forming a depression in the at least one electrically conductive contact section so that a first electrically conductive contact subsection and a second electrically conductive contact subsection are formed, which are delimited from one another by the depression, and forming a housing made of a housing material, which housing includes a housing frame that at least partially embeds the lead frame, formation of the housing including introduction of housing material into the depression so that a housing frame section formed by the housing material introduced into the depression is formed between the first and second electrically conductive contact subsections to mechanically stabilize the first and second electrical conductive contact subsections by the housing frame section.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: January 29, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Daniel Richter, Brendan Holland
  • Patent number: 10191706
    Abstract: A communication apparatus including a near field wireless communication unit which holds communication information regarding a communication sets a communication mode to be used for a wireless communication unit supporting a longer field wireless communication than a wireless communication using a near field wireless communication unit in accordance with write information written from an external apparatus to the near field wireless communication unit.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: January 29, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventor: Eiji Kadota
  • Patent number: 10193044
    Abstract: A light emitting device package can include a base including a flat top surface; first and second electrical circuit layers on the flat top surface; a light emitting diode on a region of the flat top surface; an optical member to pass light; and a guiding member having a closed loop shape surrounding the region for guiding the optical member, in which the first and second electrical circuit layers respectively include first and second portions disposed between the flat top surface and a bottom surface of the guiding member, in which the first and second electrical circuit layers respectively include first and second extension portions that respectively extend from the first and second portions to locations outside of an outer edge of the guiding member in different directions.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: January 29, 2019
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Jun Seok Park
  • Patent number: 10186498
    Abstract: A semiconductor package includes a leadframe having a first island and second island each having an upper surface corresponding with an upper surface of the leadframe. One or more tie bars couple the first island with the second island. At least one tie bar has a protrusion extending from the upper surface of the leadframe and configured to substantially prevent a flow of a solder between the first and second islands. A first die couples with the leadframe at the first island and a second die couples with the leadframe at the second island. At least one of the tie bars has a recess at a lower surface of the leadframe. The leadframe includes a slit between the first and second island.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: January 22, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Masakazu Watanabe
  • Patent number: 10170615
    Abstract: A semiconductor device includes a source region and a drain region of a first conductivity type. The source region and the drain region are arranged in a first direction parallel to a first main surface of a semiconductor substrate. The semiconductor device further includes a layer stack having a drift layer of the first conductivity type and a compensation layer of a second conductivity type. The drain region is electrically connected with the drift layer. The semiconductor device also includes a connection region of the second conductivity type extending into the semiconductor substrate, the connection region being electrically connected with the compensation layer, wherein the buried semiconductor portion does not fully overlap with the drift layer.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: January 1, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Anton Mauder, Andreas Meiser, Till Schloesser
  • Patent number: 10163766
    Abstract: A leadless package with wettable flanks is formed by providing a substrate and plating a metal layer onto the substrate to form a contact on the substrate extending across a saw street. An encapsulant is deposited over the contact. The substrate is removed to expose the contact and encapsulant. The encapsulant and contact are singulated. In some embodiments, the substrate includes a ridge, and the contact is formed over the ridge.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: December 25, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Darrell D. Truhitte, James P. Letterman, Jr.
  • Patent number: 10157869
    Abstract: Embodiments of the present disclosure are directed towards a method of assembling an integrated circuit package. In embodiments the method may include providing a wafer having an unpatterned passivation layer to prevent corrosion of metal conductors embedded in the wafer. The method may further include laminating a dielectric material on the passivation layer to form a dielectric layer and selectively removing dielectric material to form voids in the dielectric layer. These voids may reveal portions of the passivation layer disposed over the metal conductors. The method may then involve removing the portions of the passivation layer to reveal the metal conductors. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: December 18, 2018
    Assignee: Intel Corporation
    Inventors: Thorsten Meyer, Gerald Ofner, Teodora Ossiander, Frank Zudock, Christian Geissler
  • Patent number: 10147856
    Abstract: A composite substrate includes a plate-like lead frame having a plurality of supporting leads and a plurality of element containers supported by the supporting leads. The plurality of element containers each has a first electrode lead, a second electrode lead, and a resin molded body integrated with the first electrode lead and the second electrode lead, and within the resin molded body, the first electrode lead, the second electrode lead, and the supporting lead are held spaced apart from one another. At least one of the plurality of element containers has a wire that connects the first electrode lead and the supporting lead and is covered with the resin molded body.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: December 4, 2018
    Assignee: NICHIA CORPORATION
    Inventors: Motohisa Nogi, Saiki Yamamoto
  • Patent number: 10147857
    Abstract: Disclosed are a light emitting device package. The light emitting device package includes a body having recess; a first lead frame including a first and second portions on a first region of the body; a second lead frame including a third and fourth portions on a second region of the body; a third lead frame between the first and second lead frame. The body has a length of the first direction greater than a width of the second direction, wherein the second portion of the first lead frame extends toward the second lead frame and has a small width, and wherein the fourth portion of the second lead frame extends toward the first lead frame. A first light emitting device is disposed on the first portion of the first lead frame and a second light emitting device is disposed on the third portion of the second lead frame.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: December 4, 2018
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Dong Yong Lee
  • Patent number: 10141248
    Abstract: On the assumption that a pair of hanging parts is provided in a lead frame and a clip includes a main body part and a pair of extension parts, the pair of the extension parts is mounted and supported on the pair of the hanging parts. Accordingly, the clip is mounted on a lead (one point) and the pair of the hanging parts (two points), and the clip is supported by the three points.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: November 27, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Akira Muto, Koji Bando, Yukihiro Sato, Kazuhiro Mitamura
  • Patent number: 10121737
    Abstract: The invention relates to an electronic component, namely a printed circuit board element comprising a first semiconductor component (14) which is arranged on an upper side of an electrically conductive intermediate plate (16) such that a connector pad (18) of the semiconductor component (14) is electrically contacted with the intermediate plate (16) and comprising a second semiconductor component (15) which is arranged on a lower side of the intermediate plate (16). The second semiconductor component (15) comprises a first connector pad (17) and a second connector pad (19), wherein both connector pads (17, 19) are aligned in the direction of the intermediate plate (16) and wherein the first connector pad (17) is contacted with the intermediate plate (16), and wherein the second connector pad (19) is not contacted with the intermediate plate (16). Moreover, the invention relates to a method for producing such a printed circuit board element.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: November 6, 2018
    Assignee: SCHWEIZER ELECTRONIC AG
    Inventors: Thomas Gottwald, Christian Roessle
  • Patent number: 10121750
    Abstract: A sensor chip package assembly and an electronic device having the sensor chip package assembly are disclosed, where the sensor chip package assembly includes: a metal substrate (100) which has a bonding pad region (11) and a placement region (12), the bonding pad region having a plurality of metal bonding pads (13); a sensor chip (200) which is located on an upper surface of the metal substrate, and the sensor chip having a plurality of sensor chip bonding pads (21); an electrical connection assembly (300) which electrically connects a metal bonding pad and a sensor chip bonding pad; and a packaging material cover (400) which covers the metal substrate, the sensor chip and the electrical connection assembly, where any two adjacent metal bonding pads are spaced in an insulated manner by the packaging material cover.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: November 6, 2018
    Assignee: Shenzhen Goodix Technology Co., Ltd.
    Inventors: Yuping Liu, Wei Long
  • Patent number: 10115705
    Abstract: A semiconductor package and manufacturing method thereof are disclosed and may include a first semiconductor device comprising a first bond pad on a first surface of the first semiconductor device, a first encapsulant material surrounding side edges of the first semiconductor device, and a redistribution layer (RDL) formed on the first surface of the first semiconductor device and on a first surface of the encapsulant material. The RDL may electrically couple the first bond pad to a second bond pad formed above the first surface of the encapsulant material. A second semiconductor device comprising a third bond pad on a first surface of the second semiconductor device may face the first surface of the first semiconductor device and be electrically coupled to the first bond pad on the first semiconductor device. The first surface of the first semiconductor device may be coplanar with the first surface of the encapsulant material.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: October 30, 2018
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Jin Young Kim, No Sun Park, Yoon Joo Kim, Choon Heung Lee, Jin Han Kim, Seung Jae Lee, Se Woong Cha, Sung Kyu Kim, Glenn Rinne
  • Patent number: 10115251
    Abstract: A sophisticated semiconductor device is provided. A semiconductor device including an IPD chip and an MCU chip which are included in one package. The IPD chip includes: a power transistor that drives an external load; a gate drive circuit that drives the power transistor; and a protection circuit that protects the power transistor from having a breakdown. The MCU chip includes an arithmetic processing unit that performs arithmetic processing based on detected data output from the protection circuit, and a storage unit that stores a program for the arithmetic processing unit. The MCU chip has a function of controlling operation of the power transistor according to the detected data.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: October 30, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Osamu Soma, Akira Uemura
  • Patent number: 10109563
    Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: October 23, 2018
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Rennier Rodriguez, Aiza Marie Agudon, Jefferson Talledo, Moonlord Manalo, Ela Mia Cadag, Rammil Seguido
  • Patent number: 10109609
    Abstract: A connection structure is provided that includes a semiconductor substrate, a first layer arranged on the semiconductor substrate, the first layer being configured to provide shielding against radioactive rays, a second layer arranged on the first layer, the second layer including solder including Pb, and an electrically conductive member arranged on the second layer.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: October 23, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Josef Höglauer, Jürgen Schredl, Xaver Schlögel, Klaus Schiess
  • Patent number: 10109779
    Abstract: A light emitting device includes a base member including a resin-molded body having an upper surface, a lower surface and a front surface, and formed with a groove-shaped recess in the front surface across the front surface from the upper surface to the lower surface. A lead can be embedded in the resin-molded body. A light emitting element is provided, and can include a light emitting element chip and a reflecting layer limiting a light-emitting region to a predetermined range. The reflecting layer can be disposed on or over a side surface of the light emitting element. The light emitting element is disposed on a bottom surface of the recess such that the reflecting layer is spaced apart from a side wall of the recess.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: October 23, 2018
    Assignee: NICHIA CORPORATION
    Inventor: Tsuyoshi Okahisa
  • Patent number: 10103096
    Abstract: A semiconductor device (10) of the present invention includes at least one circuit unit (41, 42, 43) which includes: a device main body (20); and a power supply terminal (31, 32, 33), an output terminal (34, 35, 36), and a ground terminal (37, 38, 39) which protrude from the device main body (20). The output terminal (34, 35, 36) protrudes from the device main body (20) in an opposite direction to the ground terminal (37, 38, 39). The power supply terminal (31, 32, 33) protrudes in a same direction as the ground terminal (37, 38, 39) and is positioned so as to be shifted in a direction orthogonal to an arrangement direction of the output terminal (34, 35, 36) and the ground terminal (37, 38, 39).
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: October 16, 2018
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventor: Yoshihiro Kamiyama
  • Patent number: 10103129
    Abstract: A data storage device includes a controller and a multi-stack chip package. A method is used to operate the data storage device. The multi-stack chip package includes a first semiconductor chip arranged on a package substrate, a second semiconductor chip arranged on the first semiconductor chip, and a third semiconductor chip is arranged between the first and second semiconductor chips. The controller can control the first to third semiconductor chips by using a feature parameter measured from each semiconductor chip and a target value that may be originally designed by a memory vendor.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: October 16, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-seop Shim, Jaehong Kim
  • Patent number: 10090298
    Abstract: An integrated packaging structure is provided. In the package structure, an integrated component body has a first source region, a second source region, a first setting region, and a second setting region, which are separated from each other. A first MOSFET die and a second MOSFET die are located on the first setting region and the second setting region respectively, and have a top surface, a source electrode pad and a gate electrode pad. The source electrode pad and the gate electrode pad are exposed from the top surface and spaced apart from each other. A first source connection element is connected to the source electrode pad of the first MOSFET die and the first source region. A second source connection element is connected to the source electrode pad of the second MOSFET die and the second source region. A gate connection element is connected to the gate electrode pad and a gate region of the integrated component body.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: October 2, 2018
    Assignee: TAIWAN SEMICONDUCTOR CO., LTD.
    Inventors: Chien-Chung Chen, Sen Mao, Hsin-Liang Lin
  • Patent number: 10083898
    Abstract: An improvement is achieved in the reliability of a semiconductor device. After a resin sealing portion is formed to seal a die pad, a semiconductor chip mounted over the die pad, a plurality of leads, and a plurality of wires electrically connecting a plurality of pad electrodes of the semiconductor chip with the leads, the resin sealing portion and the leads are cut with a rotary blade to manufacture the semiconductor device. In the semiconductor device, at least a portion of each of first and second leads is exposed from a lower surface of the sealing portion. End surfaces of the first and second leads as the respective cut surfaces thereof are exposed from each of side surfaces of the sealing portion as the cut surfaces of the resin sealing portion.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: September 25, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Tadatoshi Danno, Tsukasa Matsushita, Atsushi Nishikizawa