With Structure For Mounting Semiconductor Chip To Lead Frame (e.g., Configuration Of Die Bonding Flag, Absence Of A Die Bonding Flag, Recess For Led) Patents (Class 257/676)
  • Patent number: 11462481
    Abstract: A fan-out packaging structure includes a redistribution layer and a positioning sheet formed on the redistribution layer. The positioning sheet defines at least one opening penetrating opposite sides of the positioning sheet. At least one chip is mounted in the at least one opening. The redistribution layer comprises at least one conductive circuit. The at least one chip is electrically coupled to a corresponding one conductive circuit.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: October 4, 2022
    Assignee: Kore Semiconductor Co., Ltd.
    Inventors: Ying-Chieh Pan, Hsiang-Hua Lu, Ching-Yu Ni
  • Patent number: 11462467
    Abstract: A lead frame includes a die paddle and a plurality of leads. The leads surround the die paddle. Each of the leads includes an inner lead portion and an outer lead portion connecting to the inner lead portion. The inner lead portion is adjacent to and spaced apart from the die paddle. A bottom surface of the inner lead portion is higher than a bottom surface of the outer lead portion. The bottom surface of the inner lead portion includes one or more supporting members disposed thereon. The one or more supporting members have a convex surface facing away from the inner lead portion.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: October 4, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chia Hsiu Huang, Chun Chen Chen, Wei Chih Cho, Shao-Lun Yang, Yu-Shun Hsieh
  • Patent number: 11462448
    Abstract: A step-type stacked chip packaging structure based on a resin spacer that includes: a plastic packaging material, a circuit board, a resin spacer, a first chip, a second chip and an electrical connection assembly. The resin spacer, the first chip, and the second chip are stacked on the circuit board respectively. The second chip is stacked on the first chip in a stepped manner. The circuit board, the first chip and the second chip are electrically connected together through the electrical connection assembly. The resin spacer uses a fiber glass fabric as its base material, a weight percent of the fiber glass fabric is 10-60 wt %, and the following components are attached to the fiber glass fabric as a percentage by the total weight of the resin spacer: 8-40 wt % of epoxy resin, 10-30 wt % of quartz powder, 2-10 wt % of aluminum oxide, 1-8 wt % of calcium oxide, and 1-8 wt % of curing agent.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: October 4, 2022
    Assignee: SU ZHOU DREAM TECHNOLOGY CO., LTD.
    Inventor: Guohong Yang
  • Patent number: 11462505
    Abstract: A method of forming a packaged semiconductor device includes attaching a backside surface of a semiconductor die to a major surface of a package substrate. A first conductive connector is formed over a portion of an active surface of the semiconductor die and a portion of the major surface of the package substrate. A first conductive connection between a first bond pad of the semiconductor die and a first substrate pad of the package substrate is formed by way of the first conductive connector. A bond wire connects a second bond pad of the semiconductor die to a second substrate pad of the package substrate. The first bond pad located between the second bond pad and an edge of the semiconductor die.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: October 4, 2022
    Assignee: NXP USA, INC.
    Inventor: Jinbang Tang
  • Patent number: 11462498
    Abstract: A semiconductor package includes a frame having a wiring structure and having a recess portion, a semiconductor chip having an active surface with a connection pad disposed thereon and disposed in the recess portion, an encapsulant sealing the semiconductor chip, and a redistribution layer having a first via connected to the connection and a second via connected to a portion of the wiring structure. The semiconductor chip includes a protective insulating film disposed on the active surface and having an opening exposing a region of the connection pad, and a redistribution capping layer connected to the region of the connection pad and extending onto the protective insulating film, and a surface of the redistribution capping layer is substantially the same level as a surface of the portion of the wiring structure, exposed from the first surface.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: October 4, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yong Jin Park, Sang Kyu Lee, Moon Il Kim, Myung Sam Kang, Jeong Ho Lee, Young Gwan Ko
  • Patent number: 11462504
    Abstract: A semiconductor apparatus includes: a metal plate; a semiconductor device mounted on the metal plate; an external terminal electrically connected to the semiconductor device or the metal plate; a metal wire wire-bonded to the semiconductor device, the metal plate or the external terminal; and a package covering and resin-sealing the semiconductor device, the metal plate and the metal wire, wherein the metal wire is bonded to a top-layer electrode of the semiconductor device at a first bond and a second bond, and the metal wire includes a low loop that is positioned between the first bond and the second bond, is adjacent to at least one of the first bond and the second bond and is not in contact with the top-layer electrode.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: October 4, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Koichi Tokubo
  • Patent number: 11437310
    Abstract: Provided is a connection structure for a semiconductor package which includes: a first passivation layer having an opening; a first conductive pattern that penetrates the first passivation layer and protrudes upwardly from the first passivation layer; a second passivation layer on the first passivation layer and covering the first conductive pattern; a second conductive pattern on the second passivation layer and electrically connected to the first conductive pattern; a third passivation layer on the second passivation layer and covering the second conductive pattern; and an external terminal in the opening and electrically connected to the first conductive pattern, wherein the first conductive pattern is thicker than the second conductive pattern.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: September 6, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jongyoun Kim
  • Patent number: 11430669
    Abstract: A method of manufacturing a chip package is provided. The method includes patterning at least one chip pad of a chip to form a patterned structure in the at least one chip pad, the patterned structure including at least one predefined recess, and encapsulating the chip with encapsulating material, thereby filling the at least one predefined recess.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: August 30, 2022
    Assignee: Infineon Technologies AG
    Inventor: Petteri Palm
  • Patent number: 11430718
    Abstract: Lead frames for semiconductor device packages may include lead fingers proximate to a die-attach pad. A convex corner of the die-attach pad, or of the lead fingers proximate to a geometric center of the lead frame may be rounded to exhibit a radius of curvature of at least two times a greatest thickness of the die-attach pad, the thickness measured in a direction perpendicular to a major surface of the die-attach pad. A shortest distance between the die-attach pad and a largest of the lead fingers may be at least two times the greatest thickness of the die-attach pad.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: August 30, 2022
    Assignee: Microchip Technology Incorporated
    Inventor: Behrooz Mehr
  • Patent number: 11410945
    Abstract: A semiconductor package having a partial outer metal layer and packaging method thereof is disclosed. In the method, a specific packaging substrate or a specific positioning plate is used to package multiple semiconductor devices and a partial outer metal layer is quickly formed on an encapsulation of each semiconductor device in the same step.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: August 9, 2022
    Assignee: Powertech Technology Inc.
    Inventors: Shih-Chun Chen, Sheng-Tou Tseng, Kun-Chi Hsu, Chin-Ta Wu, Ying-Lin Chen, Ting-Yeh Wu
  • Patent number: 11410964
    Abstract: Systems and methods for controlling contamination during thermocompression bonding are provided herein. The tool generally includes a bondhead having a first channel extending in a lateral direction from a first port along a second side toward a perimeter of the bondhead. In several examples, the bondhead includes a second channel fluidly coupled to a second port and extending in a lateral direction along an inset surface of the bondhead, where the second channel at least partially surrounds the first channel. In other examples, the tool includes a vacuum manifold having a vacuum opening positioned laterally outward from the bondhead. A first flow unit is coupled to the first channel and is configured to withdraw air. A second flow unit is coupled to the second port or the manifold to withdraw fluid and prevent outgas sing bonding materials from entering the first channel, depositing on the bondhead, and/or contaminating neighboring semiconductor components.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: August 9, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Brandon P. Wirz, Jaekyu Song, Sui Chi Huang
  • Patent number: 11398564
    Abstract: According to one embodiment, a semiconductor device includes first and second metal members, and a semiconductor element. The first metal member is electrically connected to a first terminal. The semiconductor element includes first and second electrodes, first to third semiconductor regions, and a gate electrode. The second metal member is provided on the second electrode, and electrically connected to the second electrode and a second terminal. The semiconductor element includes a first portion that overlaps the second metal member in the first direction, and a second portion that does not overlap the second metal member in the first direction. A length in the second direction of the first semiconductor region between an adjacent pair of the gate electrodes is greater than a length in the second direction of the first semiconductor region between an adjacent pair of the gate electrodes.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: July 26, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Masatoshi Arai
  • Patent number: 11398417
    Abstract: Embodiments of the present disclosure are directed to leadframe semiconductor packages having die pads with cooling fins. In at least one embodiment, the leadframe semiconductor package includes leads and a semiconductor die (or chip) coupled to a die pad with cooling fins. The cooling fins are defined by recesses formed in the die pad. The recesses extend into the die pad at a bottom surface of the semiconductor package, such that the bottom surfaces of the cooling fins of the die pad are flush or coplanar with a surface of the package body, such as an encapsulation material. Furthermore, bottom surfaces of the cooling fins of the die pad are flush or coplanar with exposed bottom surfaces of the leads.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: July 26, 2022
    Assignee: STMICROELECTRONICS, INC.
    Inventor: Jefferson Talledo
  • Patent number: 11393774
    Abstract: In various embodiments, the present disclosure provides semiconductor devices, packages, and methods. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and an encapsulant on the die pad and the lead. A plurality of cavities extends into at least one of the die pad or the lead to a depth from a surface of the at least one of the die pad or the lead. The depth is within a range from 0.5 ?m to 5 ?m. The encapsulant extends into the plurality of cavities. The cavities facilitate improved adhesion between the die pad or lead and the encapsulant, as the cavities increase a surface area of contact with the encapsulant, and further increase a mechanical interlock with the encapsulant, as the cavities may have a rounded or semi-spherical shape.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: July 19, 2022
    Assignee: STMicroelectronics, Inc.
    Inventor: Ian Harvey Arellano
  • Patent number: 11394313
    Abstract: A power conversion apparatus includes N semiconductor modules respectively including a switch part including first and second semiconductor switches coupled in series, and an output terminal coupled to a node that connects the first and second semiconductor switches, where N is an integer greater than or equal to 3, wherein the N semiconductor modules are arranged so that the output terminals thereof are adjacent to each other. The power conversion apparatus further includes an output bar to couple the output terminals of the N semiconductor modules so that a parasitic inductance of a current path coupling the output terminals of first and second semiconductor modules among the N semiconductor modules, and a parasitic inductance of a current path coupling the output terminals of the first and third semiconductor modules among the N semiconductor modules, are approximately balanced.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: July 19, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Hong-fei Lu
  • Patent number: 11387173
    Abstract: A first lead terminal, a second lead terminal provided parallel to the first lead terminal, and a tie bar connecting the first lead terminal and the second lead terminal are provided. The tie bar includes a first narrow-width section touching the first lead terminal, a second narrow-width section touching the second lead terminal, and a wide-width section having a larger width than the first narrow-width section and the second narrow-width section and connecting the first narrow-width section and the second narrow-width section. The wide-width section has a through-hole formed between the first narrow-width section and the second narrow-width section.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: July 12, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ken Sakamoto, Taketoshi Shikano, Hiroshi Kawashima
  • Patent number: 11380828
    Abstract: A light-emitting device includes a carrier, a light-emitting unit disposed on the carrier, a reflective element arranged on the light-emitting unit, and an optical element arranged on the carrier and surrounding the light-emitting unit.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: July 5, 2022
    Assignee: EPISTAR CORPORATION
    Inventors: Min-Hsun Hsieh, Shih-An Liao
  • Patent number: 11379062
    Abstract: A display panel and a testing method thereof, the display panel including a product region and a cutting region, and the product region including a display sub-region and a non-display sub-region. The display panel includes a flexible substrate, a thin film transistor layer, an organic light-emitting layer, a encapsulation layer, and a touch layer. The touch layer includes touch electrodes and touch leads. An end of each of the touch leads is connected to a corresponding touch electrode, the other end of each of the touch leads extends from the non-display sub-region to the cutting region, and a density of the touch leads in the cutting region is less than a density of the touch leads in the non-display sub-region.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: July 5, 2022
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Dan Lin, Qibing Dai, Minlun Liu
  • Patent number: 11380608
    Abstract: A semiconductor module includes a substrate on which first, second, and third circuit boards that are electrically isolated from each other are formed; a semiconductor element arranged on the first circuit board; a connecting member that bridges an upper surface electrode of the semiconductor element and the second circuit board so as to electrically connect the upper surface electrode to the second circuit board; a wire that electrically connects the third circuit board to a first electrode that is located outside of where the first, second and third circuit boards are located in a plan view; and a sealing resin that covers and seals the substrate, the semiconductor element, the connecting member, and the wire, wherein the wire is wired from the third circuit board to the first electrode so as to cross the semiconductor element at a vertical position lower than an upper surface of the connecting member.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: July 5, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Hayato Nakano
  • Patent number: 11373939
    Abstract: Implementations of power modules may include: a substrate having a first side and a second side. The power module may include a plurality of leads coupled to a second side of the substrate and a molding compound over a portion of five or more surfaces of the substrate. The power module may also include an opening extending from a first side of the substrate to an outer edge of the molding compound. The opening may be configured to receive a coupling device and the coupling device may be configured to couple with a heat sink or a package support.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: June 28, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jinchang Zhou, Asif Jakwani, Chee Hiong Chew, Yusheng Lin, Sravan Vanaparthy, Silnore Tejero Sabando
  • Patent number: 11373937
    Abstract: A semiconductor device according to an embodiment comprises a semiconductor element, a first terminal, a plurality of second terminals, and an encloser. The semiconductor element is rectangular. The first terminal has an upper surface to which a back surface of the semiconductor element is bonded. The second terminals are arranged around the first terminal. The second terminals are arranged at four corners of the encloser to be exposed from the bottom surface, and sides of the semiconductor element are opposed to the first side, the second side, the third side, and the fourth side, respectively. The first terminal is apart from the first side surface and the third side surface, a lower surface of the first terminal is exposed from the bottom surface, and the first terminal is partly exposed from the second side surface and the fourth side surface.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: June 28, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Haruhiko Iwabuchi
  • Patent number: 11373941
    Abstract: A semiconductor device includes a semiconductor chip, first and second source terminals and a Kelvin terminal, wherein the semiconductor chip includes a first source electrode coupled to the first source terminal through a first connecting portion, a second source electrode coupled to the second source terminal through a second connecting portion, a Kelvin pad coupled to the Kelvin terminal and formed independently of the first source electrode, a power MOSFET that has a source coupled to the first source electrode, a sense MOSFET that has a source coupled to the second source electrode, a source pad formed on a portion of the first source electrode and coupled to the first connecting portion, a plurality of source potential extraction ports formed around a connection point between the first connecting portion and the source pad and a plurality of wires coupled between the source potential extraction ports and the Kelvin pad.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: June 28, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshimasa Uchinuma, Yusuke Ojima
  • Patent number: 11367666
    Abstract: Provided is a semiconductor package. More particularly, the present invention relates to a clip, a lead frame, and a substrate used in a semiconductor package having engraved patterns formed on surfaces thereof so as to increase an adhesive force and a corrosion resistant performance, thereby improving reliability of the semiconductor package, and the semiconductor package including the same.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: June 21, 2022
    Assignee: JMJ Korea Co., Ltd.
    Inventors: Yun Hwa Choi, Jeong Hun Cho, Soon Seong Choi
  • Patent number: 11367675
    Abstract: A method for manufacturing a semiconductor device includes: fixing a semiconductor chip to a first part of a leadframe; bonding one connector member to a first terminal of the semiconductor chip, a second terminal of the semiconductor chip, a second part of the leadframe, and a third part of the leadframe; forming a sealing member; and separating a first conductive part of the connector member and a second conductive part of the connector member by removing at least a section of the portion of the connector member exposed outside the sealing member, the first conductive part being bonded to the first terminal and the second part, the second conductive part being bonded to the second terminal and the third part.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: June 21, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Katsuya Sato, Kakeru Yamaguchi, Tetsuya Yamamoto
  • Patent number: 11362021
    Abstract: Provided is a pressurized semiconductor package including a lead frame including a pad board and a first terminal, a semiconductor chip, pressurizing members stacked to pressurize the semiconductor chip, and a package housing. The semiconductor chip is physically pressurized by the pressurizing members and is electrically connected to improve durability of the semiconductor package and to simplify a manufacturing process.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: June 14, 2022
    Assignee: JMJ Korea Co., Ltd.
    Inventors: Yun Hwa Choi, Jeonghun Cho
  • Patent number: 11342289
    Abstract: The present disclosure relates to a semiconductor package, that may include a package substrate, a base die arranged on and electrically coupled to the package substrate, and at least one power plane module arranged on the package substrate at a periphery of the base die. The power plane module may include a top surface and a bottom surface, and at least one vertical interleaving metal layer electrically coupled at the bottom surface to the package substrate. The semiconductor package may further include a semiconductor device including a first section disposed on the base die, and a second section disposed on the power plane module, wherein the second section of the semiconductor device may be electrically coupled to the at least one vertical interleaving metal layer at the top surface of the power plane module.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: May 24, 2022
    Assignee: INTEL CORPORATION
    Inventors: Jenny Shio Yin Ong, Bok Eng Cheah, Jackson Chung Peng Kong, Seok Ling Lim, Kooi Chi Ooi
  • Patent number: 11328984
    Abstract: Multi-die integrated circuit packages and methods of manufacturing the same are disclosed. An example integrated circuit package includes a first leadframe, a first die on a first side of the first leadframe, and a second die on a second side of the first leadframe opposite the first side. The example integrated circuit package further includes external second leadframe separate from the first leadframe.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 10, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: You Chye How, Huay Yann Tay, Franklin Santos Marcelino
  • Patent number: 11320464
    Abstract: A chip package according to one embodiment includes a magnetic field sensor and a chip housing. The chip housing is a rectangular parallelepiped body. A solenoid coil is wound around four outer surfaces of the chip housing. The magnetic field sensor is disposed in the chip package. A plurality of first electrode pads connected to the solenoid coil and a plurality of second electrode pads connected to the magnetic field sensor are disposed on one mounting surface.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: May 3, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Jia Liu
  • Patent number: 11322431
    Abstract: A semiconductor package includes a die pad; a plurality of external connection terminals located around the die pad; a semiconductor chip located on a top surface of the die pad and electrically connected with the plurality of external connection terminals; and a sealing member covering the die pad, the plurality of external connection terminals and the semiconductor chip and exposing an outer terminal of each of the plurality of external connection terminals. A side surface of the outer terminal of each of the plurality of external connection terminals includes a first area, and the first area is plated.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: May 3, 2022
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventor: Masafumi Suzuhara
  • Patent number: 11322437
    Abstract: A flip chip interconnection including a circuit board is disclosed. The circuit board includes a substrate, inner leads, a T-shaped circuit line and a dummy pattern. The inner leads, the T-shaped circuit line and the dummy pattern are located on an inner bonding area of the substrate. The T-shaped circuit line includes a main segment, a branch segment and a connection segment that is connected to the main segment and the branch segment. The main segment and the branch segment are extended along a lateral direction and a longitudinal direction, respectively. The dummy pattern is located between the connection segment and the inner leads.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: May 3, 2022
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Yu-Chen Ma, Hsin-Hao Huang, Wen-Fu Chou, Gwo-Shyan Sheu
  • Patent number: 11322427
    Abstract: A chip on film package including a chip and a flexible film. The chip includes bumps disposed on the chip and is mounted on the flexible film. The flexible film includes first vias, second vias, upper leads and lower leads. The first vias and the second vias penetrate the flexible film and are arranged on two opposite sides of a reference line respectively. A distance between one of the first vias and one of the second vias, which are closer to a first side of the chip, is longer than that between another one of the first vias and another one of the second, which are further from the first side. The upper leads are disposed on the upper surface connected between the vias and the bumps. The lower leads are disposed on the lower surface and connected to the vias.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: May 3, 2022
    Assignee: Novatek Microelectronics Corp.
    Inventors: Hsien-Wen Lo, Wen-Ching Huang
  • Patent number: 11317046
    Abstract: An imaging element includes: an imaging unit in which a plurality of pixel groups including a plurality of pixels that output pixel signals according to incident light are formed, and on which incident light corresponding to mutually different pieces of image information is incident; a control unit that controls, for each of the pixel groups, a period of accumulating in the plurality of pixels included in the pixel group; and a readout unit that is provided to each of the pixel groups, and reads out the pixel signals from the plurality of pixels included in the pixel group.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: April 26, 2022
    Assignee: NIKON CORPORATION
    Inventors: Shiro Tsunai, Hironobu Murata
  • Patent number: 11317541
    Abstract: An electronic component module includes a second terminal electrode that is independent of a first terminal electrode in terms of potential. A second electronic component is mounted on a board, with a first surface thereof facing the board. A heat transfer portion is disposed on a second surface of the second electronic component, the heat transfer portion being connected to both the first terminal electrode and the second terminal electrode. A heat dissipation portion is connected to the board via the first terminal electrode, the second terminal electrode, and the heat transfer portion.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: April 26, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shinichiro Kuroiwa, Yukihiro Fujita, Tadateru Yamada
  • Patent number: 11302652
    Abstract: A semiconductor package includes a metallic pad and leads spaced from the metallic pad by a gap, the metallic pad including a roughened surface. The semiconductor package further includes a semiconductor die including bond pads, and an adhesive between the roughened surface of the metallic pad and the semiconductor die, therein bonding the semiconductor die to the metallic pad, wherein the adhesive includes a resin. The metallic pad further includes a groove surrounding the semiconductor die on the roughened surface, the groove having a surface roughness less than a surface roughness of the roughened surface of the metallic pad.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: April 12, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: ChienHao Wang, Bob Lee, YuhHarng Chien
  • Patent number: 11302664
    Abstract: A method of manufacturing a die package structure includes steps described below. A conductive substrate with a plurality of trenches is provided. A die is disposed in each of the trenches. A conductive layer is formed covering the dies and the conductive substrate. A patterned photoresist layer with a plurality of openings is formed exposing a plurality of areas of the conductive layer. A mask is formed on each of the areas of the conductive layer. The patterned photoresist layer is removed after forming the masks. By using the masks, the conductive layer and the conductive substrate under thereof are selectively etched to a predetermined depth to form a plurality of conductive bumps and a plurality of electrodes, in which a remaining of the conductive substrate includes a bottom substrate, the electrodes and the conductive bumps. An upper sealing layer is formed covering the bottom substrate and the dies.
    Type: Grant
    Filed: May 31, 2020
    Date of Patent: April 12, 2022
    Assignee: Comchip Technology Co., Ltd.
    Inventors: Chien-Chih Lai, Hung-Wen Lin
  • Patent number: 11302569
    Abstract: A method for manufacturing a semiconductor device according to the present invention includes the steps of (a) preparing a lead frame including a power chip die pad to which two terminals are connected, a control element die pad to which one terminal is connected, and tie bar portions connecting between a plurality of terminals including the two terminals, (b) placing a power chip and a free wheel diode on the power chip die pad and placing ICs on the control element die pad, (c) encapsulating in a mold resin to allow the tie bar portions to be exposed outside and a plurality of terminals including the two terminals and the one terminal to protrude outward, and (d) removing the tie bar portions other than the tie bar portions connecting the two terminals.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: April 12, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shuhei Yokoyama, Seiya Sugimachi, Maki Hasegawa, Kosuke Yamaguchi, Shogo Shibata
  • Patent number: 11293603
    Abstract: An apparatus includes a coverlay layer having a void therein. A backing layer is disposed against a first side of the coverlay layer. A transmission layer is disposed against a second side of the coverlay layer opposite the first side such that a chamber is formed within the void between the transmission layer and the backing layer. The transmission layer includes a first area having a first level of light transmissivity and a second area having a second level of light transmissivity that is greater than the first level of light transmissivity. The transmission layer is oriented so that at least a portion of each of the first area and the second area overlaps the void. A light source is positioned in the chamber between the first area of the transmission layer and the backing layer.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: April 5, 2022
    Assignee: Rohinni, LLC
    Inventors: Cody Peterson, Monica Hansen, Justin Wendt, Clint Adams, Andrew Huska
  • Patent number: 11296069
    Abstract: In one general aspect, a device can include a leadframe including at least one of an external input terminal or an external output terminal, an interposer made of an insulating material, and a redistribution layer coupled to the interposer and made of a conductive material. The redistribution layer can include a plurality of traces. The device can also include a semiconductor die disposed between the redistribution layer and the leadframe.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: April 5, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Elsie Agdon Cabahug, Marie Clemens Ypil Quinones, Maria Cristina Estacio, Romel Nogas Manatad, Chung-Lin Wu, Jerome Teysseyre
  • Patent number: 11289447
    Abstract: A method of die and clip attachment includes providing a clip, a die and a substrate, laminating a sinterable silver film on the clip and the die, depositing a tack agent on the substrate, placing the die on the substrate, placing the clip on the die and the substrate to create a substrate, die and clip package, and sintering the substrate, die and clip package.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: March 29, 2022
    Assignees: Alpha Assembly Solutions, Inc., Advanced Packaging Center BV
    Inventors: Oscar Khaselev, Eef Boschman
  • Patent number: 11288476
    Abstract: The present invention generally relates to a fingerprint sensor package comprising a substrate having thereon a plurality of electrical connection pads, a fingerprint sensor arranged on the substrate and electrically connected to at least one of the electrical connection pads, a bond wire loop formed from a bond wire having two ends of which at least one end is mechanically and electrically attached to a first one of the electrical connection pads, and a force sensing member in electrical contact with the first electrical connection pad via an upper portion of the bond wire loop, and in electrical contact with a second one of the electrical connection pads different from the first electrical connection pad, wherein an electrical property of the force sensing member is alterable in response to a deformation of the force sensing member.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: March 29, 2022
    Assignee: FINGERPRINT CARDS ANACATUM IP AB
    Inventors: Hanna Nilsson, Karl Lundahl
  • Patent number: 11282807
    Abstract: In some examples, a system comprises a set of nanoparticles and a set of nanowires extending from the set of nanoparticles.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: March 22, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Benjamin Stassen Cook, Ralf Jakobskrueger Muenster, Sreenivasan Kalyani Koduri
  • Patent number: 11251098
    Abstract: In the semiconductor device, a screw has a head section embedded in a case groove section provided in a frame placing stage of a case to cause side and front surfaces of the head section to be covered by the case, thereby fixing the screw to the case. A threaded section passes through a frame through hole of a frame exposed section disposed above the head section to protrude upward to be exposed on a side facing away from the base plate.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: February 15, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yosuke Nakata
  • Patent number: 11244877
    Abstract: Provided is a sealing structure including a housing that houses a heat generating member or a heat dissipation member thereinside, and a resin that is filled in the housing. In a sectional view, the housing includes a first recess portion in a position facing the heat generating member or the heat dissipation member.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: February 8, 2022
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuya Nakatsuka, Shinya Kawakita, Susumu Ishida, Isamu Yoshida, Osamu Ikeda
  • Patent number: 11239195
    Abstract: In some examples, a system comprises a first component having a first surface, a first set of nanoparticles coupled to the first surface, and a first set of nanowires extending from the first set of nanoparticles. The system also comprises a second component having a second surface, a second set of nanoparticles coupled to the second surface, and a second set of nanowires extending from the second set of nanoparticles. The system further includes an adhesive positioned between the first and second surfaces. The first and second sets of nanowires are positioned within the adhesive.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: February 1, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sreenivasan Kalyani Koduri, Benjamin Stassen Cook, Ralf Jakobskrueger Muenster
  • Patent number: 11233186
    Abstract: There is provided a semiconductor light-emitting device including: a main lead including a main surface; a semiconductor light-emitting element mounted on the main surface of the main lead; a bonding material that bonds the semiconductor light-emitting element to the main surface of the main lead; a sub lead arranged in a first direction with respect to the main lead and including a main surface facing the same side as the main surface of the main lead; a first wire including a first end connected to the main surface of the sub lead and a second end connected to the semiconductor light-emitting element; a resin case including a case main surface facing the same direction as the main surfaces of the main lead and the sub lead and supporting the main lead and the sub lead.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: January 25, 2022
    Assignee: ROHM CO., LTD.
    Inventors: Dai Miyazaki, Masahiko Kobayakawa
  • Patent number: 11227817
    Abstract: Generally described, one or more embodiments are directed to a leadframe package having a plurality of leads, a die pad, a semiconductor die coupled to the die pad, and encapsulation material. An inner portion of the die pad includes a perimeter portion that includes a plurality of protrusions that are spaced apart from each other. The protrusions aid in locking the die pad in the encapsulation material. The plurality of leads includes upper portions and base portions. The base portion of the plurality of leads are offset (or staggered) relative to the plurality of protrusions of the die pad. In particular, the base portions extend longitudinally toward the die pad and are located between respective protrusions. The upper portions of the leads include lead locks that extend beyond the base portions in a direction of adjacent leads. The lead locks and the protrusion in the die pad aid in locking the leads and the die pad in the encapsulation material.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: January 18, 2022
    Assignee: STMICROELECTRONICS, INC.
    Inventor: Jefferson Talledo
  • Patent number: 11227822
    Abstract: A semiconductor device includes a first lead having a base extending in a first direction, and an IC on the base. The semiconductor device also includes a second lead, a third lead and fourth leads. The second lead includes a first belt-like section on one side of the base in the first direction, extending in a second direction, and paired second belt-like sections extending in the first direction from the first belt-like section. The third lead is on one side in the first direction. The fourth leads are on one side of the third lead in the first direction. First switching elements are bonded to the third lead. Second switching elements are respectively bonded to the fourth leads. The base overlaps with the first belt-like section 121 when viewed in the first direction. At least a part of the base is between the second belt-like sections.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: January 18, 2022
    Assignee: ROHM CO., LTD.
    Inventor: Shigeru Hirata
  • Patent number: 11227775
    Abstract: According to an embodiment of the disclosure, a method of fabricating a carrier for a wafer level package (WLP) by using a lead frame, wherein the lead frame is fabricated by forming a trench and a post by performing first half etching on an upper surface of a base substrate comprising a conductive material, filling the first-half-etched surface with resin of an insulating material, removing the resin exposed to outside of the trench so that an upper surface of the trench and an upper surface of the resin are at a same level, and performing second half etching on a lower surface of the base substrate, in which a memory chip is attached to the lower surface of the base substrate.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: January 18, 2022
    Assignee: HAESUNGDS CO., LTD.
    Inventors: Dong Young Pyeon, Sung Il Kang, Jong Hoe Ku, In Seob Bae
  • Patent number: 11227810
    Abstract: An electronic module has a rear surface-exposed conductor 10, 20, 30 having a rear surface-exposed part 12, 22, 32 whose rear surface is exposed; an electronic element 15, 25 provided on a front surface of the rear surface-exposed conductor 10, 20, 30; and a connector 60 configure to connect the rear surface-exposed conductor 10, 20, 30 and the electronic element 15, 25 or two rear surface-exposed conductors 10, 20, 30 each other. A groove 150 is provided on the front surface of the rear surface-exposed conductor 10, 20, 30. The sealing part 90 is provided with a press hole or a press impression 110, 120, 130 used to press the rear surface-exposed conductor 10, 20, 30. In an in-plane direction, a center portion of the press hole or the press impression 110, 120, 130 is provided on the side opposite to the connector 60 or the electronic element 15, 25 with respect to the groove 150.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: January 18, 2022
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventor: Yoshihiro Kamiyama
  • Patent number: 11217514
    Abstract: In a power semiconductor device, power semiconductor elements are mounted on a large die pad and the like. The large die pad is joined to a power lead via a lead stepped portion. The large die pad has a first end portion and a second end portion located with a distance therebetween in the X axis direction. In the Y axis direction, the lead stepped portion is joined to the first end portion side relative to a central line between the first end portion and the second end portion. The large die pad is inclined such that a distance between the large die pad and the first main surface of the molding resin is longer from the first end portion toward the second end portion.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: January 4, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takamasa Iwai, Shingo Sudo, Yuichiro Suzuki