With Structure For Mounting Semiconductor Chip To Lead Frame (e.g., Configuration Of Die Bonding Flag, Absence Of A Die Bonding Flag, Recess For Led) Patents (Class 257/676)
  • Patent number: 10735673
    Abstract: According to the disclosure, a relationship of Tgp>Tgf, ?f1<?PCB1, and (Tgp?To)×?PCB1<(Tgf?To)×?f1+(Tgp?Tgf)×?f2 or a relationship of Tgp<Tgf, ?PCB1<?f1, and (Tgf?To)×?f1<(Tgp?To)×?PCB1+(Tgf?Tgp)×?PCB2 is satisfied, where linear expansion coefficients in an in-plane direction of the substrate at a temperature below a glass transition temperature Tgp of the substrate and at a temperature above the glass transition temperature Tgp of the substrate are denoted as ?PCB1 and ?PCB2, respectively, linear expansion coefficient of the frame at a temperature below a glass transition temperature Tgf of the frame and at a temperature above the glass transition temperature Tgf of the frame are denoted as ?f1 and ?f2, respectively, and a room temperature is denoted as To.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: August 4, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Koichi Shimizu, Tadashi Kosaka, Shuichi Chiba, Kazuya Notsu, Hisatane Komori, Satoru Hamasaki, Yu Katase
  • Patent number: 10727166
    Abstract: A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: July 28, 2020
    Assignee: Advanced Interconnect Systems Limited
    Inventors: Haruki Ito, Nobuaki Hashimoto
  • Patent number: 10720379
    Abstract: The base of an integrated circuit package comprises a first side, and a second side opposing the first side. The base further comprises, a base mounting section, a die mounting section, and a recessed section. The recessed section comprises a recess between the die mounting section and the base mounting section. The base further comprises an opening extending through the base from the first side to the second side. At least a portion of the recess intersects with the opening.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: July 21, 2020
    Assignee: CREE, INC.
    Inventors: Sung Chul Joo, Bradley Millon, Erwin Cohen
  • Patent number: 10714418
    Abstract: An electronic device (e.g., integrated circuit) and method of making the electronic device is provided that reduces a strength of an electric field generated outside a package of the electronic device proximate to the low voltage lead pins. The electronic device includes a low voltage side and a high voltage side. The low voltage side includes a low voltage die attached to a low voltage die attach pad. Similarly, the high voltage side includes a high voltage die attached to a high voltage die attach pad. Lead pins are attached to each of the low and high voltage attach pads and extend out from a package of the electronic device in an inverted direction.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: July 14, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chang-Yen Ko, J K Ho
  • Patent number: 10685946
    Abstract: An elastomeric interface layer (elayer) is formed over multiple light emitting diode (LED) dies by depositing photoresist materials across multiple LED dies, and using the LED dies as a photolithography mask to facilitate formation of the elayer on each LED die. The elayer facilitates adhesive attachment of each LED die with a pick and place head (PPH), allowing the LED dies to be picked up and placed onto a display substrate including control circuits for sub-pixels of an electronic display. In some embodiments, the LED dies are micro-LED (?LED) dies.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: June 16, 2020
    Assignee: Facebook Technologies, LLC
    Inventors: Daniel Brodoceanu, Oscar Torrents Abad
  • Patent number: 10685895
    Abstract: The present invention provides a power module and a manufacturing method thereof. The power module includes a carrier board and a lead component stacked relative to the carrier board. The lead component includes an initial plane, plural first pins and plural second pin. The initial plane includes a vertical projection overlapping with the carrier board. The first pins are electrically connected to the carrier board and vertical to the initial plane. The second pins are electrically connected to the carrier board and vertical to the initial plane. An isolation gap is disposed in the initial plane and located between the first pins and the second pins. The initial plane is separated into a first plane and a second plane by the isolation gap, so as to electrically isolate the first pins and the second pins from each other.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: June 16, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Pengkai Ji, Shouyu Hong, Zhenqing Zhao, Jianhong Zeng
  • Patent number: 10685831
    Abstract: A semiconductor structure includes providing a substrate including a first surface and a second surface opposite to the first surface. The first surface is a functional surface. The method also includes forming a plastic seal layer on the first surface of the substrate, and performing a thinning-down process on the second surface of the substrate after forming the plastic seal layer. The plastic seal layer provides support for the substrate during the thinning-down process, and thus warping or cracking of the plastic seal layer 240 may be avoided. In addition, the plastic seal layer can also be used as a material for packaging the substrate. Therefore, after the thinning-down process, the plastic seal layer does not need to be removed. As such, the fabrication process is simplified, and the production cost is reduced.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: June 16, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Fu Cheng Chen, Jian Gang Lu
  • Patent number: 10679928
    Abstract: A power module includes a first die pad, a first switching element, a second die pad, a second switching element, an integrated circuit element, an encapsulation resin, and a lead frame assembly. The encapsulation resin encapsulates the first switching element, the second switching element, and the integrated circuit element. The lead frame assembly includes an outer lead and an inner lead. The lead frame assembly includes a first lead frame and a second lead frame. The first lead frame includes a first inner lead connected to the first die pad and a first outer lead connected to the first inner lead. The second lead frame includes a second inner lead connected to the second die pad and a second outer lead connected to the second inner lead.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: June 9, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Yasumasa Kasuya, Hiroaki Matsubara, Hiroshi Kumano, Toshio Nakajima, Shigeru Hirata, Yuji Ishimatsu
  • Patent number: 10680146
    Abstract: A method for manufacturing a light emitting device includes: preparing a wavelength conversion member; preparing a light emitting element comprising a pair of electrodes at a second face side of the light emitting element; forming a light transmissive member, which includes: disposing a liquid resin material on a second main face of the wavelength conversion member, disposing the light emitting element on the liquid resin material such that (i) a first face of the light emitting element is opposed to the second main face of the wavelength converting member, (ii) a portion of a first lateral face of the light emitting element and a portion of a second lateral face of the light emitting element are covered by the liquid resin material, and (iii) a first corner of the light emitting element is exposed from the liquid resin material, and curing the liquid resin material; and forming a covering member.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: June 9, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Ikuko Baike, Ryo Suzuki
  • Patent number: 10672691
    Abstract: A packaged semiconductor device has a thin profile, two face-to-face mounted power semiconductor device dice, and no internal bond wires. A first semiconductor device die is mounted so that a gate pad is bonded to the bottom of a first lead, and so that a source pad is bonded to the bottom of a second lead. A second semiconductor device die identical to the first is mounted so that a gate pad is bonded to the top of the first lead, and so that a source pad is bonded to the top of the second lead. The backside drain electrodes of both dice are electrically coupled to a third lead. The third lead in one example has a forked-shape, and the two dice are disposed entirely between the two tines of the fork. After encapsulation, the three leads extend parallel to each other from a body portion of the package.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: June 2, 2020
    Assignee: Littelfuse, Inc.
    Inventor: Nathan Zommer
  • Patent number: 10665766
    Abstract: An elongated lead frame (100) for a plurality of solid state light emitters (116), an elongated lighting assembly and a method of manufacturing an elongated lead frame are provided. The elongated lead frame comprises a first patterned layer (310) of an electrically conductive material and a second patterned layer (320) of an electrically isolating material. The first patterned layer comprising two electrically conductive tracks (102) that comprise first structures (316, 316?) for a first layer of a stack of light emitter islands and two electrically conductive connections between the first structures, at least one of the electrically conductive tracks comprises in between pairs of neighboring first structures a winded portion for forming a flexible electrically conductive connection in between the pairs of neighboring first structures.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: May 26, 2020
    Assignee: SIGNIFY HOLDING B.V.
    Inventors: Gerard Kums, Norbertus Antonius Maria Sweegers, Floris Maria Hermansz Crompovets, Christian Kleijnen
  • Patent number: 10643933
    Abstract: Provided are a semiconductor package substrate and a manufacturing method thereof having improved pattern accuracy and product reliability with simple manufacturing processes. The semiconductor package substrate includes a base substrate having a conductive material, and including a first area, on which chips are mounted, including first recesses or first trenches in a surface, and a second area contacting the first area and including dummy recesses or dummy trenches in a surface; and a resin filled in the first recesses or the first trenches and the dummy recesses or the dummy trenches.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: May 5, 2020
    Assignee: Haesung DS CO., LTD.
    Inventors: In Seob Bae, Sung Il Kang
  • Patent number: 10636823
    Abstract: An image sensor assembly, a method of manufacturing the same, and a camera module are provided. The image sensor assembly includes an image sensor including a pixel region provided on a surface of the image sensor, a cover disposed above the pixel region, a spacer disposed on a surface of the cover and the spacer being configured to maintain a distance between the image sensor and the cover, and an adhesive configured to fixedly attach the spacer to the image sensor, wherein the spacer comprises a first and a second member disposed parallel to and at a distance from each other.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: April 28, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kang Hyun Lee, Sung Min Song, Jung Gon Choi, Heung Woo Park, Jae Hyun Lim
  • Patent number: 10636726
    Abstract: A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: April 28, 2020
    Assignee: Advanced Interconnect Systems Limited
    Inventors: Haruki Ito, Nobuaki Hashimoto
  • Patent number: 10629351
    Abstract: To inhibit a decrease in inductance of an inductor in a plurality of semiconductor chips that are stacked. A semiconductor device includes: first and second semiconductor chips that are stacked; a first inductor; an arrangement-restricted region; and a circuit. In the semiconductor device, the first inductor is arranged in the first semiconductor chip. The arrangement-restricted region is provided in a region of the second semiconductor chip corresponding to the first inductor. The circuit is arranged in a region of the second semiconductor chip not corresponding to the arrangement-restricted region.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: April 21, 2020
    Assignee: SONY CORPORATION
    Inventor: Takanori Saeki
  • Patent number: 10622288
    Abstract: A semiconductor device includes a semiconductor element, leads, and an encapsulation resin covering a portion of each of the leads and the semiconductor element. Each of the leads includes an external connection portion projecting from a side surface of the encapsulation resin. The external connection portion of at least one of the leads has opposite ends in a width-wise direction that extends along the side surface of the encapsulation resin. The external connection portion includes two recesses arranged toward a center in the width-wise direction from the opposite ends. The two recesses extend from a distal surface toward the encapsulation resin. The opposite ends in the width-wise direction define an end connection part. The external connection portion includes a part between the two recesses defining a center connection part.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: April 14, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Koshun Saito
  • Patent number: 10608146
    Abstract: A method includes providing a metallic auxiliary carrier and forming metallic structure elements on the auxiliary carrier by carrying out at least one metal deposition process with the aid of at least one masking layer. Provision is furthermore made for arranging a reflective embedding material enclosing the metallic structure elements on the auxiliary carrier and removing the auxiliary carrier, such that a carrier comprising the structure elements and the embedding material and comprising two opposite main sides is provided. The main sides of the carrier are formed by the structure elements and the embedding material. The method furthermore includes arranging radiation-emitting semiconductor chips on the carrier, arranging a conversion material for radiation conversion on the carrier provided with the semiconductor chips, and carrying out a singulation process of forming separate radiation-emitting components.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: March 31, 2020
    Assignee: OSRAM OLED GmbH
    Inventors: Markus Richter, Tamas Lamfalusi
  • Patent number: 10600769
    Abstract: An electronic component is provided. The electronic component includes a substrate, an III-V die and a silicon die. The III-V die is disposed on the substrate. The silicon die is stacked to the III-V and electrically connected to the III-V die.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: March 24, 2020
    Assignee: AIROHA TECHNOLOGY GROUP
    Inventors: Heng-Chih Lin, Chien-Kuang Lee
  • Patent number: 10593612
    Abstract: One or more embodiments are directed to quad flat no-lead (QFN) semiconductor packages, devices, and methods in which one or more electrical components are positioned between a die pad of a QFN leadframe and a semiconductor die. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and at least one electrical component that has a first contact on the die pad and a second contact on the lead. A semiconductor die is positioned on the at least one electrical component and is spaced apart from the die pad by the at least one electrical component. The device further includes at least one conductive wire, or wire bond, that electrically couples the at least one lead to the semiconductor die.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: March 17, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Cristina Somma, Fulvio Vittorio Fontana
  • Patent number: 10586750
    Abstract: The present invention relates to a stackable power module, comprising a module body having a top side and a bottom side provided with top and bottom contact pads, each of the top contact pads electrically connected to a corresponding bottom contact pad; at least one power semiconductor device embedded in the module body, at least one conductive structure connecting the power semiconductor device to a respective top and/or bottom contact pad, wherein the at least one conductive structure has a thermal capacity sufficient to take up an amount of heat generated during a switching cycle of the at least one power semiconductor device without increasing temperature above a critical threshold.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: March 10, 2020
    Assignee: HS ELEKTRONIK SYSTEME GMBH
    Inventor: Richard Sinning
  • Patent number: 10574918
    Abstract: An imaging element includes: an imaging unit in which a plurality of pixel groups including a plurality of pixels that output pixel signals according to incident light are formed, and on which incident light corresponding to mutually different pieces of image information is incident; a control unit that controls, for each of the pixel groups, a period of accumulating in the plurality of pixels included in the pixel group; and a readout unit that is provided to each of the pixel groups, and reads out the pixel signals from the plurality of pixels included in the pixel group.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: February 25, 2020
    Assignee: NIKON CORPORATION
    Inventors: Shiro Tsunai, Hironobu Murata
  • Patent number: 10566931
    Abstract: A quartz crystal oscillator as an electronic component includes a base section as a first substrate having a lower surface as a first surface, a first lead terminal connected to the first surface, and a second lead terminal connected to the first surface, and the first lead terminal and the second lead terminal intersect each other when viewed in a first direction along the first surface.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: February 18, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Manabu Kondo
  • Patent number: 10559523
    Abstract: A semiconductor package includes a die pad; a plurality of external connection terminals located around the die pad; a semiconductor chip located on a top surface of the die pad and electrically connected with the plurality of external connection terminals; and a sealing member covering the die pad, the plurality of external connection terminals and the semiconductor chip and exposing an outer terminal of each of the plurality of external connection terminals. A side surface of the outer terminal of each of the plurality of external connection terminals includes a first area, and the first area is plated.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: February 11, 2020
    Assignee: J-Devices Corporation
    Inventor: Masafumi Suzuhara
  • Patent number: 10546806
    Abstract: A semiconductor apparatus includes a first semiconductor element, a second semiconductor element, and a metal pattern formed on the second semiconductor element. The metal pattern includes a first connection connected to the first semiconductor element and a second connection connected to a first terminal portion of the first semiconductor element and positioned away from the first connection. A first electrically conductive path formed between the first and second connections has a larger electric resistance than an electric resistance of a second electrically conductive path formed between the second connection and the first terminal portion.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: January 28, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hiroyuki Nakamura
  • Patent number: 10541153
    Abstract: An electronics package includes an insulating substrate, an electrical component having a back surface coupled to a first surface of the insulating substrate, and an insulating structure surrounding at least a portion of a perimeter of the electrical component. A first wiring layer extends from the first surface of the insulating substrate and over a sloped side surface of the insulating structure to electrically couple with at least one contact pad on an active surface of the electrical component. A second wiring layer is formed on a second surface of the insulating substrate and extends through at least one via therein to electrically couple with the first wiring layer.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: January 21, 2020
    Assignee: General Electric Company
    Inventors: Christopher James Kapusta, Raymond Albert Fillion, Risto Ilkka Sakari Tuominen, Kaustubh Ravindra Nagarkar
  • Patent number: 10541229
    Abstract: Apparatuses and methods for semiconductor die heat dissipation are described. For example, an apparatus for semiconductor die heat dissipation may include a substrate and a heat spreader. The substrate may include a thermal interface layer disposed on a surface of the substrate, such as disposed between the substrate and the heat spreader. The heat spreader may include a plurality of substrate-facing protrusions in contact with the thermal interface layer, wherein the plurality of substrate-facing protrusions are disposed at least partially through the thermal interface layer.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: January 21, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Sameer S. Vadhavkar, Xiao Li, Anilkumar Chandolu
  • Patent number: 10529657
    Abstract: The instant disclosure provides a method for manufacturing a package structure of a folding magnetic coupling isolator. The method includes providing a leadframe structure including a frame body and a first and a second leadframes connected to the frame body, the first and second leadframes including first and second chip-mounting portions, first and second coil portions, and a plurality of first and second pins and floated pins; disposing the first and second chips on the first and second chip-mounting portions and establishing electrical connections between the first and second chips and the first and second pins; and rotating the first leadframe relative to the frame body and moving the first leadframe to a position above or under the second leadframe, thereby electrically isolating the first leadframe from the second leadframe. The first coil portion and the second coil portion are aligned with and magnetically coupled to each other.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: January 7, 2020
    Assignee: LITE-ON SINGAPORE PTE. LTD.
    Inventor: You-Fa Wang
  • Patent number: 10515877
    Abstract: A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. The bonding surface includes a first region to which a bonding portion of the wire is bonded, a second region to which another bonding portion of the wire is bonded, and a third region between the first region and the second region. A width of the third region is smaller than a width of the first region and a width of the second region.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: December 24, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Yukihiro Sato, Toshinori Kiyohara
  • Patent number: 10515914
    Abstract: Foundation layers and methods of forming a foundation layer are described. Die pads are formed over a die. A dielectric layer is formed over die pads and the die. The dielectric layer is then recessed to expose top portions of the die pads. A first plurality of sintered conductive vias are formed over the die pads. The first sintered conductive vias are coupled to at least one of the die pads. In addition, a photoresist layer may be formed over the dielectric layer and the top portions of the die pads. Via openings are formed in the photoresist layer. A second plurality of sintered conductive vias may then be formed over the first sintered conductive vias to form a plurality of sintered conductive lines. Each of the first and second sintered conductive vias are formed with a liquid phase sintering (LPS) solder paste.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: December 24, 2019
    Assignee: Intel Corporation
    Inventors: Mihir A. Oka, Ken P. Hackenberg, Vijay Krishnan (Vijay) Subramanian, Neha M. Patel, Nachiket R. Raravikar
  • Patent number: 10510591
    Abstract: A package-on-package (PoP) structure includes a first package and a second package stacked on the first package. The first package includes a die, a plurality of conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The die includes an amorphous layer located on the rear surface. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The redistribution structure is on the active surface of the die and is electrically connected to the conductive structures and the die.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Hui Cheng, Chin-Fu Kao, Chih-Yuan Chien, Szu-Wei Lu
  • Patent number: 10497659
    Abstract: The present disclosure relates to a package substrate. The package substrate includes a patterned conductive layer and conductive pillars. Each of the conductive pillars includes a first portion and a second portion, where the first portion contacts the patterned conductive layer at one end of the first portion, and the second portion is adjacent to another end of the first portion. A thickness of the first portion is greater than a thickness of the second portion. Side surfaces of the first portion are substantially coplanar to side surfaces of the second portion.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: December 3, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Li-Chuan Tsai, Chih-Cheng Lee
  • Patent number: 10483191
    Abstract: A MEMS pressure sensor packaged with a molding compound. The MEMS pressure sensor features a lead frame, a MEMS semiconductor die, a second semiconductor die, multiple pluralities of bonding wires, and a molding compound. The MEMS semiconductor die has an internal chamber, a sensing component, and apertures. The MEMS semiconductor die and the apertures are exposed to an ambient atmosphere. A method is desired to form a MEMS pressure sensor package that reduces defects caused by mold flashing and die cracking. Fabrication of the MEMS pressure sensor package comprises placing a lead frame on a lead frame tape; placing a MEMS semiconductor die adjacent to the lead frame and on the lead frame tape with the apertures facing the tape and being sealed thereby; attaching a second semiconductor die to the MEMS semiconductor die; attaching pluralities of bonding wires to form electrical connections between the MEMS semiconductor die, the second semiconductor die, and the lead frame; and forming a molding compound.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: November 19, 2019
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Aaron Cadag, Frederick Arellano, Ernesto Antilano, Jr.
  • Patent number: 10475719
    Abstract: A semiconductor structure includes a substrate comprising a die pad disposed over the substrate, and a passivation disposed over the substrate and surrounding the die pad, a redistribution layer (RDL) comprising a dielectric layer disposed over the passivation and an interconnect structure disposed within the dielectric layer and electrically connecting with the die pad, a conductive bump disposed over and electrically connected with the interconnect structure; and an isolation layer surrounding the substrate and the RDL.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: November 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Pei-Haw Tsao, Chien-Jung Wang
  • Patent number: 10476494
    Abstract: An intelligent power module includes a power switch, a freewheeling device, and a controller circuit incorporating a gate drive circuit and one or more power switch protection circuits. In one embodiment, the power switch is an insulated gate bipolar transistor (IGBT) device, the freewheeling device is a PN junction diode, and the controller circuit is implemented as a semiconductor integrated circuit (IC). The power module implements protection functions for the power switching device where the protection circuits are formed on the controller circuit IC and co-packaged with the power switch. In some embodiments, the control circuit in the power module includes an active soft-start circuit which is activated to realize soft-start of the power switch. In other embodiments, the control circuit in the power module includes an active turn-on pulse control circuit to detect for abnormal system input signal pulse events and block system undesired input pulses.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: November 12, 2019
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Bum-Seok Suh, Wonjin Cho, Son Tran
  • Patent number: 10465056
    Abstract: The method for producing a transparent conductive substrate includes forming metal meshes on a flexible non-conductive substrate with high transmittance. It's unnecessary to use palladium as a catalyst in this method. The metal meshes are in the form of nano/micro wires and the conductive substrate has high transmittance of 80%-90% at visible light wavelengths of 390-750 nm.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: November 5, 2019
    Assignee: NATIONAL CHUNG HSING UNIVERSITY
    Inventors: Wei-Ping Dow, Po-Ting Chen, Liang-Jie Lin, Hung-Ming Chang, Ting-Yun Lin, Fang-Yu Lin
  • Patent number: 10435290
    Abstract: A MEMS device having a wafer-level package, is provided with: a stack of a first die and a second die, defining at least a first internal surface internal to the package and carrying at least an electrical contact pad, and at least a first external surface external to the package and defining a first outer face of the package; and a mold compound, at least in part coating the stack of the first and second dies and having a front surface defining at least part of a second outer face of the package, opposite to the first outer face. The MEMS device is further provided with: at least a vertical connection structure extending from the contact pad at the first internal surface towards the front surface of the mold compound; and at least an external connection element, electrically coupled to the vertical connection structure and exposed to the outside of the package, at the second outer face thereof.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: October 8, 2019
    Assignee: STMicroelectronics (Malta) Ltd
    Inventors: Conrad Cachia, David Oscar Vella, Damian Agius, Maria Spiteri
  • Patent number: 10438877
    Abstract: In a general aspect, a multi-chip semiconductor device package assembly can include a leadframe having a first die pad and a second die pad. The assembly can further include a first semiconductor die coupled to the first die pad and a second semiconductor die coupled to the second die pad. The assembly can also include a blank having a first portion coupled to the first die pad and a second portion coupled to the second die pad, such that the blank forms a bridge between the first die pad and the second die pad.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: October 8, 2019
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Jose Felixminia Palagud, Soon Wei Wang
  • Patent number: 10438908
    Abstract: A lead, for a packaged transistor device, having a signal portion and a bias line portion, with the signal portion and the bias line portion each having a proximal end and a distal end. The signal portion and the bias line portions of the lead are integrally formed together as a single conductive component, with the proximal end of the bias line portion integrated into the signal portion of the lead and with the distal ends of the signal portion and the bias line portion physically separate from each other.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: October 8, 2019
    Assignee: NXP USA, Inc.
    Inventors: Arturo Roiz, Justin Nelson Annes, Terry L. Thomas
  • Patent number: 10438928
    Abstract: Apparatuses and methods for semiconductor die heat dissipation are described. For example, an apparatus for semiconductor die heat dissipation may include a substrate and a heat spreader. The substrate may include a thermal interface layer disposed on a surface of the substrate, such as disposed between the substrate and the heat spreader. The heat spreader may include a plurality of substrate-facing protrusions in contact with the thermal interface layer, wherein the plurality of substrate-facing protrusions are disposed at least partially through the thermal interface layer.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: October 8, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Sameer S. Vadhavkar, Xiao Li, Anilkumar Chandolu
  • Patent number: 10424533
    Abstract: A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: September 24, 2019
    Assignee: ADVANCED INTERCONNECT SYSTEMS LIMITED
    Inventors: Haruki Ito, Nobuaki Hashimoto
  • Patent number: 10403605
    Abstract: A semiconductor device comprising a plurality of semiconductor chips and a plurality of electric wirings. The plurality of semiconductor chips are stacked in a first direction, each semiconductor chip of the plurality of semiconductor chips including a plurality of conductive pads that are aligned in an aligning direction, orthogonal to the first direction. The plurality of semiconductor chips are stacked such that each semiconductor chip is shifted from an adjacent semiconductor chip of the plurality of semiconductor chips by a first predetermined interval in the aligning direction and shifted from the adjacent semiconductor chip by a second predetermined interval in a second direction orthogonal to both the first direction and the aligning direction. The plurality of electric wirings electrically connect the plurality of conductive pads of every other semiconductor chip of the plurality of semiconductor chips, respectively.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: September 3, 2019
    Assignee: BUFFALO INC.
    Inventors: Yu Nakase, Takayuki Okinaga, Shuichiro Azuma, Kazuki Makuni, Takeshi Kotegawa, Noriaki Sugahara
  • Patent number: 10396746
    Abstract: A method of forming an integrated resonator apparatus includes depositing alternating dielectric layers of lower and higher acoustic impedance materials over a substrate. First and second resonator electrodes are formed over the alternating dielectric layers, with a piezoelectric layer located between the first and second resonator electrodes. A mass bias is formed over the first and second resonator electrodes. The mass bias, first and second electrodes, piezoelectric layer, and alternating dielectric layers may be encapsulated with a plastic mold fill.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: August 27, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Byron Neville Burgess, William Robert Krenik, Stuart M. Jacobsen
  • Patent number: 10396057
    Abstract: A half-bridge power semiconductor module has an insulating wiring substrate including a single insulating plate, and a positive electrode wiring conductor, a bridge wiring conductor, and a negative electrode wiring conductor disposed on or above the insulating plate while being electrically isolated from one another, at least one high side power semiconductor device having a rear surface electrode bonded onto the positive electrode wiring conductor, at least one low side power semiconductor device having a rear surface electrode bonded onto the bridge wiring conductor, a stand-up bridge terminal connected to the bridge wiring conductor, a stand-up high side terminal disposed between the high side power semiconductor device and the bridge terminal, and connected to the positive electrode wiring conductor, and a stand-up low side terminal disposed between the bridge terminal and the low side power semiconductor device, and connected to the negative electrode wiring conductor.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: August 27, 2019
    Assignee: NISSAN ARC, LTD.
    Inventor: Satoshi Tanimoto
  • Patent number: 10388582
    Abstract: A semiconductor package and a manufacturing method thereof, which can reduce the size of the semiconductor package and improve product reliability. In a non-limiting example embodiment, the method may comprise forming an interposer on a wafer, forming at least one reinforcement member on the interposer, coupling and electrically connecting at least one semiconductor die to the interposer to the interposer, filling a region between the semiconductor die and the interposer with an underfill, and encapsulating the reinforcement member, the semiconductor die and the underfill on the interposer using an encapsulant.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: August 20, 2019
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Young Rae Kim, Won Chul Do, Ji Hun Lee, Min Hwa Chang, Dong Hyun Kim, Wang Gu Lee, Jin Ryang Hwang, Mi Kyeong Choi
  • Patent number: 10388634
    Abstract: A micro-LED transfer method, manufacturing method and display device are disclosed. The method comprises: coating conductive photoresist on a receiving substrate, wherein the conductive photoresist is positive-tone photoresist; bonding a carrier substrate with the receiving substrate via the conductive photoresist, wherein metal electrodes of micro-LEDs on the carrier substrate are aligned with electrodes on the receiving substrate and are bonded with the electrodes on the receiving substrate via the conductive photoresist, and the carrier substrate is a transparent substrate; selectively lifting-off micro-LEDs from the carrier substrate through laser lifting-off using a first laser; and separating the carrier substrate from the receiving substrate.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: August 20, 2019
    Assignee: Goertek, Inc.
    Inventor: Quanbo Zou
  • Patent number: 10388597
    Abstract: A die bonding process for assembling a semiconductor device includes the steps of applying a sintered-silver-use paste to each of a plurality of first regions on an upper surface of a chip mounting part, drying the sintered-silver-use paste and applying a silver paste to a second region located between/among the respective first regions. Further, the process includes the step of mounting a semiconductor chip onto the chip mounting part in such a manner that a rear surface of the semiconductor chip faces an upper surface of the chip mounting part with the sintered-silver-use paste and the silver paste being interposed. After mounting the chip, part of each of first, second, third and fourth corners of a principal surface of the semiconductor chip is located in each of the first regions.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: August 20, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masatoshi Sugiura, Hiroi Oka
  • Patent number: 10388594
    Abstract: According to principles of the disclosure as explained herein, selected leads are electrically connected through metal strips to the lead frame until the end of the manufacturing process. The lead frame is grounded through the manufacturing process to prevent any ESD event from causing damage to the protected leads. In the final singulation step, the leads are electrically isolated from each other and from the lead frame, thus maintaining protection from a potential ESD event up until the final package singulation step.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: August 20, 2019
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Frederick Ray Gomez, Tito Mangaoang, Jr., Jefferson Talledo
  • Patent number: 10366943
    Abstract: An electronic package includes a substrate having a conductive element. The conductive element includes a stepped portion disposed at an end of the conductive element. In one embodiment, the conductive element is a lead. In another embodiment, the conductive element is a die pad. The stepped portion includes a first groove extending inward from a lower surface of the first conductive element, and a second groove extending further inward from the first groove towards an upper surface of the conductive element. An electronic component is connected to the conductive element. In one embodiment, a clip is used to electrically connect the electronic component to the conductive element. An encapsulant encapsulates the electronic component and a portion of the substrate such that the stepped portion is exposed outside an exterior side surface of the encapsulant. The stepped portion is configured to improve the bonding strength of the electronic package when attached to a next level of assembly.
    Type: Grant
    Filed: September 16, 2017
    Date of Patent: July 30, 2019
    Assignee: Amkor Technology, Inc.
    Inventors: Byong Jin Kim, Jia Yunn Ting, Hyeong Il Jeon
  • Patent number: 10367102
    Abstract: An electronic component includes a support member in which a recess part having a bottom face and a side face is provided, and a device unit that includes a substrate and is fixed to the support member so that a primary face of the substrate faces the recess part. An opening width of the recess part is, on the side of the bottom of the recess part with respect to the primary face, narrower than the width of the device unit and, on the opposite side of the bottom of the recess part with respect to the primary face, wider than the width of the device unit. An end face of the substrate overlaps with the side face of the recess part in a direction perpendicular to the primary face of the substrate. A photoelectric conversion element is arranged on the primary face of the substrate.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: July 30, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Hidemasa Oshige
  • Patent number: 10361144
    Abstract: A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: July 23, 2019
    Assignee: ADVANCED INTERCONNECT SYSTEMS LIMITED
    Inventors: Haruki Ito, Nobuaki Hashimoto