NON-VOLATILE MEMORIES, CARDS, AND SYSTEMS INCLUDING SHALLOW TRENCH ISOLATION STRUCTURES WITH BURIED BIT LINES

Abstract

A non-volatile memory device can include a buried bit line in a substrate of a non-volatile memory device and a self-aligned shallow trench isolation region in the substrate that is self-aligned to the buried bit line.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Divisional of U.S. application Ser. No. 12/109,761, filed Apr. 25, 2008 in the United States Patent and Trademark Office, and claims priority from Korean Patent Application No. 10-2007-0041430, filed on Apr. 27, 2007, in the Korean Intellectual Property Office, the entire contents of all of which are hereby incorporated by reference.

FIELD OF THE INVENTION

The present invention relates to the field of electronics, and more particularly, to methods of forming non-volatile memories and the devices so formed.

BACKGROUND

Non-volatile memory devices are widely used in various kinds of electronic products such as mobile telephones, etc. One type of non-volatile memory that has become popular is what is commonly referred to as NOR type flash memory. It is recognized that in conventional NOR flash memory, the metal contact employed in source/drain regions may use a significant area of the integrated circuit. Accordingly, one approach, sometimes referred to as buried bit line, has been used to avoid the formation of contacts in NOR type flash memory.

Non-volatile memories are also discussed in, for example, U.S. Patent Publication No. 2004/0169238 A1 to Lee et al., U.S. Patent Publication No. 2006/0180851 A1 to Lee et al., U.S. Pat. No. 5,526,307 to Yiu et al., U.S. Pat. No. 6,858,906 B2 to Lee et al, and U.S. Pat. No. 7,072,214 B2 to Jeong et al.

SUMMARY

Embodiments according to the invention can provide non-volatile memory devices, systems, and cards that include shallow trench isolation structures with buried bit lines. Pursuant to these embodiments, a non-volatile memory device can include a buried bit line in a substrate of a non-volatile memory device and a self-aligned shallow trench isolation region in the substrate that is self-aligned to the buried bit line.

In some embodiments according to the inventive concept, an electronic system can include a processor that is configured to coordinate operations of an electronic system and a volatile memory, that is electrically coupled to the processor, and that is configured to store and retrieve data responsive processor operations. A system interface, can be electrically coupled to the processor, and can be configured to provide communications between the processor and external systems and a non-volatile memory, can be electrically coupled to the processor, and can include at least one non-volatile memory device that includes a buried bit line in a substrate of a non-volatile memory device and a self-aligned shallow trench isolation region in the substrate that is self-aligned to the buried bit line.

In some embodiments according to the inventive concept, a memory card can include a non-volatile memory controller that is configured to coordinate operations of the memory card and a non-volatile memory, that can be electrically coupled to the non-volatile memory controller, and can include a non-volatile memory, which can include a buried bit line in a substrate of a non-volatile memory and a self-aligned shallow trench isolation region in the substrate that is self-aligned to the buried bit line.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic illustration of an equivalent circuit representing a NOR type flash memory array in some embodiments according to the invention.

FIG. 2 is a schematic representation of a layout of a highlighted area of the NOR type flash memory array shown in FIG. 1 in some embodiments according to the invention.

FIG. 3 is a perspective view of a NOR type flash memory device including buried bit lines with self aligned shallow trench isolation structures formed therein in some embodiments according to the invention.

FIGS. 4-13 are perspective views that illustrate methods of forming a NOR type flash memory including buried bit lines in self aligned shallow trench isolation structures in some embodiments according to the invention.

FIG. 14 is a perspective view of a NOR type flash memory including buried bit lines and self aligned shallow trench isolation structures and protruding floating gate structures in some embodiments according to the invention.

FIG. 15 is a perspective view of a flash memory including buried bit lines and self aligned shallow trench isolation structures with tunneling insulating patterns in some embodiments according to the invention.

FIGS. 16-23 are cross-sectional views that illustrate methods of forming a NOR type flash memory including buried bit lines and self aligned shallow trench isolation structures with U-shaped floating gates in some embodiments according to the invention.

FIG. 24A is a schematic illustration of an equivalent circuit of a NOR type flash memory array formed according to some embodiments of the present invention.

FIG. 24B is a table that illustrates typical operating parameters associated with NOR type flash memories formed according to embodiments of the present invention.

FIG. 25 is a block diagram illustrating memory cards and/or systems including various components and non-volatile memory with NOR type flash memory devices formed according to some embodiments of the present invention.

DESCRIPTION OF EMBODIMENTS ACCORDING TO THE INVENTION

The present invention is described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown by way of example. The present invention may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Moreover, each embodiment described and illustrated herein includes its complementary conductivity type embodiment as well.

It will be understood that when an element is referred to as being “connected to,” “coupled to” or “responsive to” (and/or variants thereof) another element, it can be directly connected, coupled or responsive to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected to,” “directly coupled to” or “directly responsive to” (and/or variants thereof) another element, there are no intervening elements present. Like numbers refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items and may be abbreviated as “/”.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising” (and/or variants thereof), when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. In contrast, the term “consisting of” (and/or variants thereof) when used in this specification, specifies the stated number of features, integers, steps, operations, elements, and/or components, and precludes additional features, integers, steps, operations, elements, and/or components.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present application, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

As described herein below in greater detail, shallow trench isolation structures can be formed self aligned to, for example, impurity regions that provide the buried bit line structures and NOR type flash memories. In particular, forming the shallow trench isolation structures so that they are self aligned to structures that provide the buried bit line of the non-volatile memory (i.e., the impurity regions) can help to substantially equalize ranks of the associated impurity regions (i.e., the lengths of the bit lines). For example, the formation of the self aligned shallow trench isolation structures can help to remove portions of the impurity regions which may have otherwise been formed misaligned by a conventional photolithographic process. As appreciated by the present inventors, using a photolithographic process to form the shallow trench isolation structures separate from the formation of the impurity regions to provide the buried bit lines can lead to misalignment errors thereby increasing the possibility of forming bit lines with different lengths within the same memory sector.

In further embodiments according to the invention, the impurity regions can be formed before the shallow trench isolation structures. In particular, the impurity regions may be formed in the substrate to provide immediately neighboring buried bit lines for the device. After the formation of the impurity region (i.e., the buried bit lines), a shallow trench isolation region can be formed in the substrate between the immediately neighboring buried bit lines. As appreciated by the present inventors, this approach can substantially equalize what may be otherwise different lengths of the immediately neighboring buried bit lines, which may be generated by conventional approaches. For example, as appreciated by the present inventors, if the shallow trench isolation structure is formed in the substrate using a standard photolithographic process (e.g., before the formation of the impurity regions), the subsequent formation of the impurity regions can be misaligned relative to the shallow trench isolation structures previously formed. Accordingly, this misalignment can lead to impurity regions (ultimately providing the buried bit lines) having different lengths.

FIG. 1 is a schematic illustration of an equivalent circuit including a NOR type flash memory array in some embodiments according to the invention. In particular, FIG. 1 shows immediately neighboring memory cells (MC) each having respective local bit lines (LBL) for the two separate groupings of rows (i.e., 8-16 rows of memory cells) which are combined and provided as a global bit line (GBL). Further, the immediately neighboring memory cells (MC) share a source line (within each of the separated rows), which is provided to a common source line (C/S). Each of the rows of memory cells is coupled to a word line (W/L), which can be used to access selected memory cells.

FIG. 2 illustrates a schematic layout of a pair of immediately neighboring memory cells (MC) shown in FIG. 1 is some embodiments according to the invention. In particular, FIG. 2 shows a pair of immediately neighboring memory cells (MC) where the source line bisects the active regions used by the immediately neighboring memory cells (MC). Further, the floating gates of the immediately neighboring memory cells (MC) are each coupled to a word line (W/L). Bit lines of the immediately neighboring memory cells (MC) are also insulated from one another by self aligned shallow trench isolation structures (STI).

FIG. 3 is a perspective view illustrating a NOR type flash memory including buried bit lines and self-aligned shallow trench isolation structures in some embodiments according to the invention. As shown in FIG. 3, a central region of a substrate 100 includes the immediately neighboring memory cells (MC) shown in FIGS. 1 and 2. In particular, a gate pattern 200 is provided on the active region in the substrate 100 for both of the immediately neighboring memory cells (MC). Immediately neighboring memory cells (MC) share a source line 101 located between the respective gate thereof. Further, buried bit lines 120 associated with each of the immediately neighboring memory cells MC are provided by impurity regions formed within the substrate 100. As further shown in FIG. 3, immediately neighboring buried bit lines 120 located between immediately neighboring memory cells (MC) are separated by a self-aligned shallow trench isolation structure pattern 160.

As further shown in FIG. 3, the gate pattern 200 coupled to each of the immediately neighboring memory cells (MC) includes a number of layers. In particular, each of the gate patterns 200 can include a gate insulating pattern 201, a floating gate pattern 202 formed thereon, an inter-gate dielectric layer formed thereon, a control gate pattern formed thereon, and a hard mask pattern 205. It will be understood that the control gate pattern 204 can provide the word line (W/L) described above in reference to FIGS. 1 and 2.

FIGS. 4-13 are perspective views that illustrate methods of forming a NOR type flash memory with buried bit lines and self aligned shallow trench isolation structures in some embodiments according to the invention. According to FIG. 4, a lower pattern 110 is formed on the substrate 100. The lower pattern 110 can be provided by forming a series of layers on the substrate 100 followed by either separately patterning each of the layers or patterning the complete collection of layers together.

According to FIG. 4, the lower pattern 110 includes a gate insulating pattern 111, a lower conductive pattern 112 formed thereon, and the capping pattern 113 formed on the lower conductive pattern 112. In some embodiments according to the invention, the gate insulating pattern 111 can be SiO2, SiON, and/or a high-K material. In some embodiments according to the invention, the lower conductive pattern 112 can be any conductive material, such as polysilicon. In some embodiments according to the invention, the capping pattern 113 may be silicon nitride.

The layers described above are patterned to provide pluralities of openings 114 to define the lower pattern 110. Accordingly, the openings 114 expose respective portions of the substrate 100. Impurities are implanted into the exposed portions of the substrate 100 via the openings 114 to form impurity regions 120. It will be understood that the impurity regions 120 can provide buried bit lines for the NOR type flash memory in some embodiments according to the invention.

According to FIG. 5, a dielectric material 130 is formed on the substrate 100 including in the openings 114 to cover the impurity regions 120. In some embodiments according to the invention, the deposition of the dielectric material 130 is limited to the openings 114. In other embodiments according to the invention, the dielectric material 130 fills the openings 114 and is deposited on an upper surface of the lower pattern 110 and is subsequently planarized to again expose the upper surface of the lower pattern.

According to FIG. 6, a photo-resist pattern 150 is formed on the lower pattern to have openings 155 therein. In some embodiments according to the invention, the photo-resist pattern 150 having the openings 155 can be formed on a mask pattern 140. As shown in FIG. 6, the openings 155 are formed above the regions of the substrate that lie between selective ones of the impurity regions 120 that have the dielectric layers thereon. For example, the openings 155 are formed above regions of the substrate 100 wherein the self aligned shallow trench isolation structures are to be formed. Accordingly, the openings 155 should be formed between immediately neighboring local bit lines provided by the impurity regions 120. In some embodiments according to the invention, the mask pattern 140 and photo resist pattern 155 are formed using conventional photo lithographic processes.

According to FIG. 7, selected portions of the lower pattern 110 are removed via the openings 155 to expose sidewalls of the dielectric layers 130 to which the shallow trench isolation structures are to be self aligned in the substrate 100. As further shown in FIG. 7, and as appreciated by the present inventors, the respective lengths, L3 and L4, of the different impurity regions 120 can be unequal.

As shown in FIG. 8, portions of the substrate 100 underlying the openings 155 and having respective portions of the lower pattern 110 formed thereon are etched to form self aligned trenches 160 and the substrate 100. The self aligned trenches 160 are self aligned to the side walls of the dielectric layers 130 formed thereon the impurity regions 120 to ultimately provide the buried bit line structures for immediately neighboring pairs of memory cells (MC). Further, because of the self aligned nature of the trench 160, the respective lengths of the immediately adjacent impurity regions 120 can be substantially equalized.

According to FIG. 9, an isolation layer 170 is formed on the upper surface of the lower pattern 110 and in self aligned trenches 160. In some embodiments according to the invention, the isolation layer 170 can be HDP, SOG, MTO, HTO, and/or undoped SiGe. In some embodiments according to the invention, the mask pattern 140 described above in reference to FIGS. 6 and 7 may remain beneath the isolation layer 170 rather than be removed.

According to FIG. 10, the portion of the isolation layer 170 remaining on the upper surface of the lower pattern 110 is removed to once again expose the upper surface of the lower pattern 110. Accordingly, as shown in FIG. 10, the deposition of the isolation layer 170 in the self aligned trench 160 provides for the formation of self aligned shallow trench isolation structures 175.

According to FIG. 11, the capping layer 113 included in the lower pattern 110 is removed to expose upper surface of the lower conductive pattern 112. The dielectric layer 130 is recessed (along with the isolation material 175) to expose side walls of the lower conductive pattern 112 above the impurity regions 120 that provide the buried bit lines. As further shown in FIG. 11, a portion of the dielectric layer 130 remains on the impurity regions 120 to reduce any subsequent coupling between an upper conductive layer and the impurity regions 120.

According to FIG. 12, an upper layer 180 is formed on the lower conductive pattern 112. The upper layer 180 includes an intergate dielectric layer 181 formed on the lower conductive layer 112, an upper conductive layer 182 formed on the intergate dielectric layer 181, and an upper hard mask layer 183 formed on the upper conductive layer 182. In some embodiments according to the invention, the upper conductive layer can be polysilicon, silicide, metal and/or a multi-layered upper conductive layer including any of these materials or combinations thereof. In some embodiments according to the invention, the intergate dielectric layer can be SiOx/SxiNy/SiOx, SiOx, SixNy, Al203, HfAIOx, HfAION, HfSiOx, HfSiON. According to FIG. 13, the upper layer is patterned to provide an upper layer pattern 200 that can provide word lines for the memory cells (MC).

FIG. 14 is a perspective view and illustrates the non-volatile memory device including buried bit lines with self aligned shallow trenched isolation (STI) structures with gate structures 190 protruding into the substrate 100. According to FIG. 14, the substrate 100 can be patterned to define groves therein, into which a gate insulating pattern 201 can be deposited. Subsequently, when the lower conductive pattern 202 is formed, a portion is deposited in the groove to provide a protruding portion of a floating gate structure 190 that extends into the substrate 100. Accordingly, a channel developed by the gate 190 may the reduced short channel effects using such a structure.

According to FIG. 15, the gate pattern 210 is formed on the substrate 100. The gate pattern 210 can include a tunnel insulating pattern 211 formed to a thickness of about 30 to about 100 Å. In some embodiments according to the invention, the tunnel insulating pattern can be SiO2, SiON, SixNy, Al2O3, HfAlON, HfSiOx, and/or HfSiON. In some embodiments according to the invention, the gate pattern 210 includes a charge storage pattern 212 formed on the tunnel insulating pattern 211. The charged storage pattern can be formed to a thickness of about 30 to about 100 Å and can be SixNy, Al2O3, HfAlOx, HfAlON, HfSiOx, and/or HfSiON. The gate pattern 210 can also include a blocking insulating pattern 213 formed on the charge storage pattern 212. The blocking insulating pattern 213 can be formed to a thickness of about 50 to about 200 Å and can be made from SiOx/SixNy/SiOx, SiOx, SixNy, Al2O3, HfAlOx, HfAlON, HfSiOx, and/or HfSiON. Further, the gate pattern 210 can include a control gate pattern 214 formed on the blocking insulating pattern 213. The control gate pattern 214 can be formed of a metal that has a work function of at least four electron volts (eE). In some embodiments according to the invention, the metal used to provide the control gate pattern 214 can be, TaN, W, WN, Ti, TiN, Ta, Hf, Nb, Mo, RuO2, Mo2N, Ir, Pt, Co, Cr, RuO, and/or Ti3Al.

FIGS. 16-23 are cross sectional views that illustrate methods of forming a non-volatile memory including buried bit lines and self aligned shallow trench isolation structures with U shaped floating gate electrodes in some embodiments according to the invention. According to FIG. 16, the lower pattern 110 is formed on the substrate 100 including openings 106 to expose underlying portions of the substrate 100. First impurities are implanted into the substrate 100 via the openings 106 to form lightly doped regions 121.

According to FIG. 17, a side wall spacer pattern 99 is formed on side walls of the lower pattern 110 in the openings 106. Subsequently, second impurities are implanted into the substrate 100 through the openings 106 having the spacer pattern 99 formed therein to form a highly doped region 122 in the substrate 100. Accordingly, the lightly doped region 121 located beneath the side wall spacer pattern 99 is maintained in the substrate 100. In some embodiments according to the invention, the material used to form the spacer pattern 99 can be the same material used to form the lower conductive pattern 112. It will be understood that the lightly doped region 121 and the more highly doped region 122, taken together, can provide the impurity region 120 described above.

According to FIG. 18, a lower interlayer dielectric layer 130 is formed in the openings 106 between the spacer pattern 99. According to FIG. 19, selective structures within the lower patter 110 are removed as described above in reference to, for example, FIGS. 7 and 8, to provide self aligned trenches 160 in the substrate 100 that are self aligned to the side walls of the lower interlayer dielectric 130.

According to FIG. 21, a shallow trench isolation material 175 is formed in the self aligned trench 160 to provide the self aligned shallow trench isolation structures 175 that are self aligned to the side walls of the interlayer dielectric layer 130 exposed by the formation of the self aligned trenches 160 shown in FIG. 20.

According to FIG. 22, the capping pattern 113 is removed and the lower inter layer dielectric 130 is recessed to expose side walls of the lower conductive pattern 112 defined by the side wall spacer pattern 99. Therefore, according to FIG. 22, the side wall spacer pattern 99 and the lower conductive pattern 112 combine to provide a U shaped floating gate electrode for the non volatile memory.

According to FIG. 23, an upper pattern is formed on the U shaped floating gate electrode including an inter gate dielectric layer 203, a control gate pattern 204, and a passivation layer 205, which together provide the upper layer 200.

FIG. 24A shows a schematic illustration of an equivalent circuit including the neighboring memory cells (MC) described above in reference to FIG. 1. Further, FIG. 24B includes a table that illustrates nominal parameters associated with operations of the memory cell (MC) shown in FIG. 24A.

FIG. 25 is a schematic representation of an electronic system 560 including a processor circuit 530 that is configured to coordinate overall operation of the electronic system 560 via a bus 500 that is coupled to a volatile memory system 540, an interface system 510, and a nonvolatile memory system 550. The nonvolatile memory system 550 can include memory devices, such as memory cards and separate non-volatile memory devices as described herein and including self-aligned shallow trench isolation structures in some embodiments according to the invention and as described herein.

As described herein, shallow trench isolation structures can be formed self aligned to, for example, impurity regions that provide the buried bit line structures and NOR type flash memories. In particular, forming the shallow trench isolation structures so that they are self aligned to structures that provide the buried bit line of the non-volatile memory (i.e., the impurity regions) can help to substantially equalize ranks of the associated impurity regions (i.e., the lengths of the bit lines). For example, the formation of the self aligned shallow trench isolation structures can help to remove portions of the impurity regions which may have otherwise been formed misaligned by a conventional photolithographic process. As appreciated by the present inventors, using a photolithographic process to form the shallow trench isolation structures separate from the formation of the impurity regions to provide the buried bit lines can lead to misalignment errors thereby increasing the possibility of forming bit lines with different lengths within the same memory sector.

In further embodiments according to the invention, the impurity regions can be formed before the shallow trench isolation structures. In particular, the impurity regions may be formed in the substrate to provide immediately neighboring buried bit lines for the device. After the formation of the impurity region (i.e., the buried bit lines), a shallow trench isolation region can be formed in the substrate between the immediately neighboring buried bit lines. As appreciated by the present inventors, this approach can substantially equalize what may be otherwise different lengths of the immediately neighboring buried bit lines, which may be generated by conventional approaches. For example, as appreciated by the present inventors, if the shallow trench isolation structure is formed in the substrate using a standard photolithographic process (e.g., before the formation of the impurity regions), the subsequent formation of the impurity regions can be misaligned relative to the shallow trench isolation structures previously formed. Accordingly, this misalignment can lead to impurity regions (ultimately providing the buried bit lines) having different lengths.

It will be apparent to those skilled in the art that various modifications and variations can be made in the invention. Thus, it is intended that the invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Claims

1. A non-volatile memory device comprising:

a buried bit line in a substrate of a non-volatile memory device; and

a self-aligned shallow trench isolation region in the substrate self-aligned to the buried bit line.

2. The non-volatile memory device according to claim 1 further comprising:

a gate structure having the buried bit line self-aligned thereto, wherein the gate structure includes a protruding portion that extends into the substrate beyond a lower surface of the buried bit line.

3. An electronic system comprising:

a processor configured to coordinate operations of an electronic system;

a volatile memory, electrically coupled to the processor, configured to store and retrieve data responsive processor operations;

a system interface, electrically coupled to the processor, configured to provide communications between the processor and external systems; and

a non-volatile memory, electrically coupled to the processor, including at least one non-volatile memory device comprising: a buried bit line in a substrate of a non-volatile memory device; and a self-aligned shallow trench isolation region in the substrate self-aligned to the buried bit line.

4. The electronic system according to claim 3 further comprising:

a gate structure having the buried bit line self-aligned thereto, wherein the gate structure includes a protruding portion that extends into the substrate beyond a lower surface of the buried bit line.

5. A memory card comprising:

a non-volatile memory controller configured to coordinate operations of the memory card; and

a non-volatile memory, electrically coupled to the non-volatile memory controller, including a non-volatile memory comprising: a buried bit line in a substrate of a non-volatile memory; and a self-aligned shallow trench isolation region in the substrate self-aligned to the buried bit line.

6. The memory card according to claim 5 further comprising:

a gate structure having the buried bit line self-aligned thereto, wherein the gate structure includes a protruding portion that extends into the substrate beyond a lower surface of the buried bit line.

7. The memory card according to claim 6 wherein the gate structure comprises a U-shaped floating gate electrode.