LATERAL DRAIN MOSFET WITH SUBSTRATE DRAIN CONNECTION
In one form a lateral MOSFET includes an active gate positioned laterally between a source region and a drain region, the drain region extending from an upper surface of a monocrystalline semiconductor body to a bottom surface of the monocrystalline semiconductor body, and a non-active gate positioned above the drain region. In another form the lateral MOSFET includes a gate positioned laterally between a source region and a drain region, the drain region extending from an upper surface of a monocrystalline semiconductor body to a bottom surface of the monocrystalline semiconductor body, the source region and the drain region being of a first conductivity type, a heavy body region of a second conductivity type in contact with and below the source region, and the drain region comprising a lightly doped drain (LDD) region proximate an edge of the gate and a sinker extending from the upper surface of the monocrystalline body to the bottom surface of the monocrystalline semiconductor body.
This is a divisional of U.S. patent application Ser. No. 12/339,215 filed Dec. 19, 2008, the entire specification of which is incorporated herein in its entirety by reference. Reference is also made to related U.S. Pat. No. 7,781,835 entitled “Lateral Drain MOSFET With Improved Clamping Voltage Control” which is also incorporated herein in its entirety by reference.
FIELD OF THE INVENTIONThis invention relates to lateral MOSFETs with a substrate drain connection, and more particularly to lateral MOSFETs with a substrate drain connection wherein the drain has a lateral segment and a vertical segment.
BACKGROUND OF THE INVENTIONThere exists a number of U.S. patents directed to lateral MOSFETs with a substrate drain connection including U.S. Pat. No. 6,600,182 issued to Rumennik on Jul. 29, 2003, and U.S. Pat. No. 7,282,765 issued to Xu et al. on Oct. 16, 2007, both of which make reference to additional patents related to lateral MOSFETs with a substrate drain connection. Also, Ng, Jacky C. W., A Novel Planar Power MOSFET With Laterally Uniform Body and Ion-Implanted JFET Region, IEEE Electron Device Letters, Vol. 29, No. 4, April 2008, pp. 375-377, describes a lateral MOSFET with a substrate drain connection. For these devices which are designed for use in high frequency power applications, a number of transistor characteristics, such as gate-to-drain capacitance and Rdson, are important and therefore affect the sales of such devices.
SUMMARY OF THE INVENTIONThe invention comprises, in one form thereof, a lateral MOSFET comprising a heavily doped substrate of a first conductivity type with a first epitaxial layer of the first conductivity type laying over the substrate. The lateral MOSFET includes a diffused tub of a second conductivity type opposite to the first conductivity type formed in the first epitaxial layer, an active gate electrode on a gate dielectric which is on a major surface of the first epitaxial layer, and a source region of the first conductivity type in the first epitaxial layer extending to the major surface of the first epitaxial layer and self aligned with a first edge of the active gate electrode. Also included is a lightly doped drain of the first conductivity type in the first epitaxial layer extending to the major surface of the first epitaxial layer and self aligned with a second edge of the active gate electrode on an opposite side of the active gate electrode from the first edge, and a sinker region of the first conductivity type on the same side of the active gate electrode as the lightly doped drain and spaced apart from the active gate electrode, the sinker region extending from the major surface of the first epitaxial layer to a depth substantially equal to the depth of the first epitaxial layer.
In a further aspect of the present invention the lateral MOSFET comprises a second epitaxial layer of the first conductivity type between the substrate and the first epitaxial layer.
In a still further aspect of the present invention the lateral MOSFET comprises a non-active gate attached to the major surface of the first epitaxial layer, the non-active gate on the same side of the active gate electrode as the lightly dope diffusion and spaced apart from the active gate electrode, and substantially between the lightly doped diffusion and the portion of the sinker in the major surface of the first epitaxial layer.
In yet another aspect of the present invention the diffused tub has a dopant profile of a diffused region such that the dopant profile of the diffused tub decreases from the major surface of the first epitaxial layer downward.
In an additional aspect of the present invention the diffused tub has a dopant profile of a region formed by multiple implants such that the vertical dopant profile of the diffused tub is substantially uniform.
In still another aspect of the present invention the lateral MOSFET includes a heavily doped region of the second conductivity type laying substantially below the source region.
In yet another aspect of the present invention the sinker has a vertical dopant profile which decreases from the major surface of the first epitaxial layer downward.
In an alternative aspect of the present invention the sinker has a vertical dopant profile which is substantially uniform.
In still another alternative aspect of the present invention the sinker has a vertical dopant profile which increases from the major surface of the first epitaxial layer downward.
The invention comprises, in one form thereof, a lateral MOSFET comprising an active gate positioned laterally between a source region and a drain region, the drain region extending from an upper surface of a monocrystalline semiconductor body to a bottom surface of the monocrystalline semiconductor body, and a non-active gate positioned above the drain region.
The invention comprises, in another form thereof, a lateral MOSFET comprising a gate positioned laterally between a source region and a drain region, the drain region extending from an upper surface of a monocrystalline semiconductor body to a bottom surface of the monocrystalline semiconductor body, the source region and the drain region being of a first conductivity type, a heavy body region of a second conductivity type in contact with and below the source region, metallization extending below the upper surface of the monocrystalline body in contact with the source region and the heavy body along a lateral surface and a side surface of each of the source region and the heavy body, and the drain region comprising a lightly doped drain (LDD) region proximate an edge of the gate and a sinker extending from the upper surface of the monocrystalline body to the bottom surface of the monocrystalline semiconductor body.
In yet another form, the invention includes a method for forming a lateral MOSFET with a substrate drain connection. The method comprises the steps of forming a source region and a drain region in an upper surface of a monolithic semiconductor body, and an active gate positioned above the monocrystalline semiconductor body between the source region and the drain region, the drain region extending from an upper surface of the monocrystalline semiconductor body to a bottom surface of the monocrystalline semiconductor body, and forming a non-active gate positioned above the drain region.
In still another form, the invention includes a method for forming a lateral MOSFET with a substrate drain connection. The method comprises the steps of forming a source region and a drain region in an upper surface of a monolithic semiconductor body, and an gate positioned above the monocrystalline semiconductor body between the source region and the drain region, the drain region extending from an upper surface of the monocrystalline semiconductor body to a bottom surface of the monocrystalline semiconductor body, and forming a heavy body region of a second conductivity type in contact with and below the source region, wherein the step of forming the drain region includes the step of forming a lightly doped drain (LDD) region proximate an edge of the gate, and a sinker extending from the upper surface of the monocrystalline body to the bottom surface of the monocrystalline semiconductor body.
The aforementioned and other features, characteristics, advantages, and the invention in general will be better understood from the following more detailed description taken in conjunction with the accompanying drawings, in which:
It will be appreciated that for purposes of clarity and where deemed appropriate, reference numerals have been repeated in the figures to indicate corresponding features. Also, the relative size of various objects in the drawings has in some cases been distorted to more clearly show the invention.
DETAILED DESCRIPTIONTurning now to the drawings,
An active gate electrode 44 is above the second epitaxial layer 28 and is separated from the second epitaxial layer 28 by a gate oxide 46. The gate oxide can be thermally grown, deposited or be of another dielectric material which can have a high dielectric constant (K) or a low dielectric constant, or a combination of dielectrics.
Metallization 48 extends down into, and contacts, the heavy P body 32 and the source region 34 through a silicide layer 50.
A second non-active gate electrode 52 lies over the sinker 38 with a gate oxide 54 lying between the top of the second epitaxial layer 28 and the non-active gate electrode 52. Both the active gate electrode 44 and the non-active gate electrode 52 may be polysilicon with silicide layers 56 on the top surfaces of the two gate electrodes 44, 52. An interlevel dielectric 58 separates the metallization 48 from the gate electrodes 44, 52 and the top surface of the second epitaxial layer 28.
The lateral extent of the sinker 38 with respect to the active gate electrode 44 affects the Rdson and the breakdown voltage of the MOSFET 20. Although a lateral MOSFET according to the present invention does not have to have the non-active gate 52 as shown in
Those skilled in the art will understand that the non-active gate electrode 52, while formed with the same etch mask used to form the active gate electrode 44, only has to be wide enough to compensate for the mask variations in the photoresist mask used to pattern the photoresist shown in
The second epitaxial layer 28 may be a N-type layer with phosphorous doping, preferably with a ρ of about 2 Ω·cm.
Formed in the upper portion of the second epitaxial layer 28 is a P well 30 which may be formed by gaseous diffusion, by a single implant, or by multiple implants. A typical CMOS tub may be created if the P well 30 is formed by gaseous diffusion. A single implantation, as indicated by arrows 64, may be a boron implant at a nominal dose of 7e13 @ 60 KeV. Multiple implants, as indicated by arrows 64 and 66, may include retrograde implants which may be at about 40 KeV and about 120 KeV, respectively.
The single and multiple implantations used to form the P well 30 have the advantage over gaseous diffusion of forming a more uniform vertical doping profile which may provide more consistency in the threshold voltages, Rdsons, and Qgds of multiple wafers of the lateral MOSFETs 20. If such consistency is present, the Rdson likely can be reduced while maintaining an acceptable Qgds compared to a diffused P well 30. The P well 30 is not formed in LOCOS regions or in termination regions of the semiconductor die.
The heavy P body 32 may be implanted with boron at a dose of about 2.5e14@60 KeV. The concentration of the heavy P body 32 is determined by several factors, including the desired unclamped inductive switching (UIS) capability, the impact on the threshold voltage, the breakdown voltage, the Rdson, and the metallization used as Ti will leach boron out of the heavy P body 32. The source region 43 may be implanted with arsenic at a dose of about 5e15@160 KeV. With the photoresist mask 100 the sinker 35 will also receive the boron implant, but the heavier concentration of sinker N type dopants will dominate the boron implanted dopants. Alternatively, the region at the surface of the second epitaxial layer 28 can be masked during the boron implant. After subsequent thermal treatment of the device shown in
Chemical and mechanical polishing (CMP) can be used to provide planarity to improve photolithography capability and to facilitate forming salicides on the gate electrode 44.
In the simulation represented in
The current density is greatest along the top surface of the second epitaxial layer 28 in the source region 34, the channel portion of the P well 30, and the LDD region 36. Since the LDD region 36 is lightly doped compared to the source region 34, the LDD region 36 has a large effect on the Rdson of the lateral MOSFET 20. Also, since the LDD region 36 is the portion of the drain closest to the active gate 44, it has a large effect on the Qgd of the lateral MOSFET 20.
While the invention has been described with reference to particular embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the scope of the invention. For example, the lateral MOSFETs of the present invention can be formed as silicon-on-nothing MOSFETs.
Therefore, it is intended that the invention not be limited to the particular embodiments disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope and spirit of the appended claims.
Claims
1. A lateral MOSFET comprising:
- a) an active gate positioned laterally between a source region and a drain region, said drain region extending from an upper surface of a monocrystalline semiconductor body to a bottom surface of said monocrystalline semiconductor body;
- b) a non-active gate positioned laterally above said drain region;
- c) a heavy body region of a second conductivity type in contact with and below said source region; and
- d) metallization extending below said upper surface of said monocrystalline body in contact with said source region and said heavy body along a lateral surface and a side surface of each of said source region and said heavy body.
2. The lateral MOSFET of claim 1 wherein a channel region of a first conductivity type lies below said active gate in an epitaxial layer of a second conductivity type opposite to said first conductivity type.
3. The lateral MOSFET of claim 1 wherein said monocrystalline semiconductor body comprises a substrate with a first epitaxial layer on said substrate, and a second epitaxial layer on said first epitaxial layer.
4. The lateral MOSFET of claim 3 wherein said substrate, said first epitaxial layer, and said second epitaxial layer are of the same conductivity type.
5. The lateral MOSFET of claim 2 wherein said channel region is part of a larger region of the same conductivity type, and said larger region has a vertical doping gradient which is not substantially uniform.
6. The lateral MOSFET of claim 2 wherein said channel region is part of a larger region of the same conductivity type, and said larger region has a vertical doping gradient which is substantially uniform.
7. The lateral MOSFET of claim 1 wherein said drain region has a substantially uniform vertical dopant concentration.
8. The lateral MOSFET of claim 1 wherein an upper portion of said drain region has a higher dopant concentration than a portion of said drain region lying below said upper portion.
9. The lateral MOSFET of claim 1 wherein an upper portion of said drain region has a lower dopant concentration than a portion of said drain region lying below said upper portion.
10. A method for forming a lateral MOSFET with a substrate drain connection comprising the steps of:
- a) forming a source region and a drain region in an upper surface of a monolithic semiconductor body, and an active gate positioned above said monocrystalline semiconductor body between said source region and said drain region, said drain region extending from an upper surface of said monocrystalline semiconductor body to a bottom surface of said monocrystalline semiconductor body; and
- b) forming a non-active gate positioned above said drain region.
11. The method of claim 10 wherein said monocrystalline semiconductor body comprises an epitaxial layer formed on a substrate, said epitaxial layer and said substrate being of a first conductivity type.
12. The method of claim 10 wherein said monocrystalline semiconductor body comprises a substrate with a first epitaxial layer formed on said substrate, and a second epitaxial layer formed on said first epitaxial layer, said substrate, said first epitaxial layer, and said second epitaxial layer being of a first conductivity type.
13. The method of claim 12 further including the step of forming a counter doped region of a second conductivity type opposite to said first conductivity type in an upper portion of said second epitaxial layer.
14. The method of claim 13 wherein said counter doped region is formed by gaseous diffusion.
15. The method of claim 13 wherein said counter doped region is formed by a single ion implantation.
16. The method of claim 13 wherein said counter doped region is formed by multiple ion implantations.
17. The method of claim 13 further including the step of performing a threshold voltage implant in an upper surface region of said second epitaxial layer.
18. The method of claim 13 wherein said active gate and said non-active gate are formed after said counter doped region is formed.
19. The method of claim 18 further including forming a sinker in said second epitaxial layer by performing an implant that is self aligned with the edged of the non-active gate which is farthest from said active gate.
20. The method of claim 19 wherein said sinker is formed by a single ion implantation.
21. The method of claim 19 wherein said sinker is formed by multiple ion implantations.
22. The method of claim 19 further including the steps of forming a heavy body of said second conductivity type and a source of said first conductivity type, both of which are self aligned with an edge of said active gate farthest from said sinker, said heavy body extending below said source region and having a lower dopant concentration than said source region.
23. The method of claim 22 further including forming a region of said first conductivity type that is self aligned with the edged of the non-active gate which is farthest from said active gate and is formed at the same time that said source region is formed.
24. The method of claim 22 further including forming a metal contact to said heavy body and source region, said metal contact extending below a top surface of said monocrystalline semiconductor body.
25. The method of claim 22 further including forming a metal contact to said heavy body and source region, said metal contact does not extend below a top surface of said monocrystalline semiconductor body.
Type: Application
Filed: Sep 29, 2011
Publication Date: Jan 26, 2012
Inventors: Thomas E. Grebs (Mountain Top, PA), Gary M. Dolny (Mountain Top, PA), Daniel M. Kinzer (El Segundo, CA)
Application Number: 13/248,339
International Classification: H01L 29/78 (20060101); H01L 21/336 (20060101);