With Lightly Doped Portion Of Drain Region Adjacent Channel (e.g., Ldd Structure) Patents (Class 257/336)
  • Patent number: 10727177
    Abstract: A device includes gates and a first conductive segment. A first distance is present between a first gate of the gates and the first conductive segment. A second distance is present between a second gate of the gates and the first conductive segment. The first distance is greater than the second distance.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Te Lin, Ting-Wei Chiang, Hui-Zhong Zhuang, Li-Chun Tien, Pin-Dai Sue
  • Patent number: 10659039
    Abstract: A semiconductor device according to one embodiment comprises a first transistor, a second transistor, a switch, and a first control circuit. The first transistor including, one end of a current path connected to a first node, another end of the current path connected to a second node, and a gate connected to a third node. The second transistor including, one end of a current path connected to the second node, another end of the current path connected to a fourth node, and a gate connected to the third node. The switch configured to connect the second node and the third node. The first control circuit configured to control the switch.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: May 19, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Masatoshi Shinohara
  • Patent number: 10658161
    Abstract: In-situ low pressure chamber cleans and gas nozzle apparatus for plasma processing systems employing in-situ deposited chamber coatings. Certain chamber clean embodiments for conductor etch applications include an NF3-based plasma clean performed at pressures below 30 mT to remove in-situ deposited SiOx coatings from interior surfaces of a gas nozzle hole. Embodiments include a gas nozzle with bottom holes dimensioned sufficiently small to reduce or prevent the in-situ deposited chamber coatings from building up a SiOx deposits on interior surfaces of a nozzle hole.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: May 19, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Xikun Wang, Andrew Nguyen, Changhun Lee, Xiaoming He, Meihua Shen
  • Patent number: 10658228
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, an oxide layer disposed over the substrate, and a first epitaxial layer disposed over the oxide layer. The first epitaxial layer has the first conductivity type. The semiconductor device also includes a second epitaxial layer disposed over the first epitaxial layer and a third epitaxial layer disposed over the second epitaxial layer. The second epitaxial layer has a second conductivity type that is opposite to the first conductivity type. The third epitaxial layer has the first conductivity type.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: May 19, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chih-Hung Lin, Chia-Hao Lee
  • Patent number: 10580875
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and/or drain metallization features; spacers on sidewalls of the gate structures and composed of a first material and a second material; and contacts in electrical contact with the source and/or drain metallization features, and separated from the gate structures by the spacers.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: March 3, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Guowei Xu, Keith Tabakman, Viraj Sardesai
  • Patent number: 10566422
    Abstract: A power semiconductor device includes a drain region and a source region disposed on a substrate, a gate insulating layer and a gate electrode disposed on the substrate and disposed between the drain region and the source region, a protection layer in contact with a top surface of the substrate and a top surface of the gate electrode, a source contact plug connected to the source region, a drain contact plug connected to the drain region, and a field plate plug in contact with the protection layer, wherein a width of the field plate plug is greater than a width of the source contact plug or a width of the drain contact plug.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: February 18, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Tae Hoon Lee, Jun Hee Cho, Jin Seong Chung
  • Patent number: 10559469
    Abstract: A p-type metal oxide semiconductor field effect transistor (PFET) includes a p-type silicon substrate and an n-type well formed in the p-type silicon substrate. The PFET also comprises a p-type source formed in the n-type well, a p-type drain formed in the n-type well, and dual pockets implanted in the n-type well and coupled to the source and drain. The dual pockets comprise a first pocket with first arsenic n-type dopants and a second pocket with second arsenic n-type dopants.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: February 11, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Younsung Choi
  • Patent number: 10546804
    Abstract: A semiconductor package includes a leadframe having an electrically conductive paddle, electrically conductive perimeter package leads, a first electrically conductive clip electrically connected to a first set of the package leads, and a second electrically conductive clip electrically connected to a second set of the package leads. The semiconductor package includes a single semiconductor die. The die includes a front-side active layer having an integrated power structure of two or more transistors. The die includes a backside portion having a backside contact electrically coupled to at least one of the two or more transistors and to the paddle. One or more first front-side contacts of the die are electrically coupled to at least one of the transistors and to the first clip, and one or more second front-side contacts of the die are electrically coupled to at least one of the transistors and to the second clip.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: January 28, 2020
    Assignee: Silanna Asia Pte Ltd
    Inventors: Shanghui Larry Tu, Michael A. Stuber, Befruz Tasbas, Stuart B. Molin, Raymond Jiang
  • Patent number: 10510860
    Abstract: In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Hsiung Lin, Chia-Hao Chang, Chih-Hao Wang, Wai-Yi Lien, Chih-Chao Chou, Pei-Yu Wang
  • Patent number: 10505034
    Abstract: A vertical transistor is described that uses a through silicon via as a gate. In one example, the structure includes a substrate, a via in the substrate, the via being filled with a conductive material and having a dielectric liner, a deep well coupled to the via, a drain area coupled to the deep well having a drain contact, a source area between the drain area and the via having a source contact, and a gate contact over the via.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: December 10, 2019
    Assignee: Intel Corporation
    Inventors: Xiaodong Yang, Jui-Yen Lin, Kinyip Phoa, Nidhi Nidhi, Yi Wei Chen, Kun-Huan Shih, Walid M. Hafez, Curtis Tsai
  • Patent number: 10497787
    Abstract: An integrated circuit which includes a field-plated FET is formed by forming a first opening in a layer of oxide mask, exposing an area for a drift region. Dopants are implanted into the substrate under the first opening. Subsequently, dielectric sidewalls are formed along a lateral boundary of the first opening. A field relief oxide is formed by thermal oxidation in the area of the first opening exposed by the dielectric sidewalls. The implanted dopants are diffused into the substrate to form the drift region, extending laterally past the layer of field relief oxide. The dielectric sidewalls and layer of oxide mask are removed after the layer of field relief oxide is formed. A gate is formed over a body of the field-plated FET and over the adjacent drift region. A field plate is formed immediately over the field relief oxide adjacent to the gate.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: December 3, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Henry Litzmann Edwards, Binghua Hu, James Robert Todd
  • Patent number: 10468411
    Abstract: A semiconductor device includes a substrate having an active pattern thereon, a gate electrode intersecting the active pattern, and a spacer on a sidewall of the gate electrode. The gate electrode includes a first metal pattern adjacent to the active pattern. The first metal pattern has a first portion parallel to the sidewall and a second portion parallel to the substrate. A top surface of the first portion has a descent in a direction from the spacer towards the second portion.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: November 5, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wonkeun Chung, Gigwan Park, Huyong Lee, TaekSoo Jeon, Sangjin Hyun
  • Patent number: 10453755
    Abstract: A CMOS transistor manufacturing method includes: forming a gate insulating film on a semiconductor substrate; forming a first gate electrode pattern on the gate insulating film in an NMOS transistor area; forming a second gate electrode pattern on the gate insulating film in a PMOS transistor area; forming a first photoresist pattern covering the NMOS transistor area to expose the second gate electrode pattern; performing a first ion injection process into the PMOS transistor area to form an n-type well region and a p-type LDD region; removing the first photoresist pattern; forming a second photoresist pattern covering the PMOS transistor area to expose the first gate electrode pattern; performing a second ion injection process into the NMOS transistor area to form a p-type well region and an n-type LDD region; removing the second photoresist pattern; and forming sidewall spacers at sidewalls of the first and second gate electrode patterns.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: October 22, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Min Kuck Cho, Myeong Seok Kim, In Chul Jung
  • Patent number: 10446684
    Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor structure having a semiconductor substrate and a gate structure on the semiconductor substrate. The gate structure includes a gate dielectric layer on the semiconductor substrate, a gate on the gate dielectric layer, and a spacer layer on opposite sides of the gate. The method also includes etching the semiconductor substrate to form first and second recesses, etching a portion of the spacer layer to expose a surface portion of the semiconductor substrate, and forming a source filling the first recess and a drain filling the second recess. The source (drain) includes a first source (drain) portion in the first (second) recess and a second source (drain) portion on the first source (drain) portion. The second source portion or the second drain portion covers the exposed surface portion of the semiconductor substrate.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: October 15, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Meng Zhao
  • Patent number: 10418461
    Abstract: Semiconductor structures and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming a dummy gate structure over the base substrate; forming source/drain regions having source/drain doping ions in the base substrate at both sides of the dummy gate structure; forming a dielectric layer on the source/drain regions and covering the side surfaces of the dummy gate structure; removing the dummy gate structure to form an opening in the dielectric layer; performing one or more of a first ion implantation process, for implanting first barrier ions in the base substrate toward the source region to form a first barrier layer under the opening, and a second ion implantation process, for implanting second barrier ions in the base substrate toward the source region to form a second barrier layer under the opening; and forming a gate structure in the opening.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: September 17, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Meng Zhao
  • Patent number: 10418899
    Abstract: A switch circuit includes a first MOS transistor and a second MOS transistor of a same conductivity type connected in parallel between a first terminal and a second terminal. The first and second MOS transistors have respective gate terminals coupled to the control terminal to receive a control signal to turn the switch circuit on or off where the control signal transitions from a first voltage level to a second voltage level at a slow rate of change. The first MOS transistor has a first threshold voltage and the second MOS transistor has a second threshold voltage where the first threshold voltage is less than the second threshold voltage.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: September 17, 2019
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Sik K. Lui, Daniel S. Ng, Xiaobin Wang
  • Patent number: 10386718
    Abstract: A computer-implemented method includes modeling, using the computer, a photoresist profile in accordance with a magnitude of a gradient of an inhibitor concentration disposed in the photoresist. The photoresist is used during a process to form an integrated circuit. In one embodiment, the computer-implemented method further includes applying the modeled photoresist profile to reduce a distortion in a printed photoresist pattern caused by a response of the photoresist to an electromagnetic wave and/or particle beam during the process.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: August 20, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Cheng En Wu, Haiqing Wei, Qiaolin Zhang, Hua Song
  • Patent number: 10388794
    Abstract: A display device according to an exemplary embodiment of the present invention includes: a substrate; a plurality of transistors formed on the substrate; and a light-emitting device connected to the plurality of transistors, wherein the transistor includes a gate electrode, the plurality of transistors include a first transistor and a second transistor of which lateral wall slope angles of the gate electrode are different from each other, and the first transistor further includes a doping control member formed on a lateral wall of the gate electrode.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: August 20, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jong Chan Lee, Woong Hee Jeong, Dae Ho Kim, Young Ki Shin, Yoon Ho Khang, Myoung Geun Cha
  • Patent number: 10374056
    Abstract: Disclosed is a method for producing a transistor device and a transistor device. The method includes: forming a source region of a first doping type in a body region of a second doping type in a semiconductor body; and forming a low-resistance region of the second doping type adjoining the source region in the body region. Forming the source region includes implanting dopant particles of the first doping type using an implantation mask via a first surface of the semiconductor body into the body region. Implanting the doping particles of the first doping type includes a tilted implantation.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: August 6, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Katarzyna Kowalik-Seidl, Bjoern Fischer, Winfried Kaindl, Markus Schmitt, Matthias Wegscheider
  • Patent number: 10373872
    Abstract: A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region in a plane view. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping with the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping with the gate region.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: August 6, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Shih-Yin Hsiao, Ching-Chung Yang, Kuan-Liang Liu
  • Patent number: 10373944
    Abstract: Disclosed examples include integrated circuits, fabrication methods and ESD protection circuits to selectively conduct current between a protected node and a reference node during an ESD event, including a protection transistor, a first diode and a resistor formed in a first region of a semiconductor structure, and a second diode formed in a second region isolated from the first region by a polysilicon filled deep trench, where the first and second diodes include cathodes formed by deep N wells alongside the deep trench in the respective first and second regions to use integrated deep trench diode rings to set the ESD protection trigger voltage and prevent a parasitic deep N well/P buried layer junction from breakdown at lower than the rated voltage of the host circuitry.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: August 6, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Akram A. Salman, Muhammad Yusuf Ali
  • Patent number: 10366893
    Abstract: The present invention provides a process for producing a semiconductor device having a breakdown voltage heightened by improving the step coverage properties of the interlayer dielectric for covering polysilicon electrodes. The process includes a step in which a gate insulating film is formed on a silicon carbide substrate, a step in which a polysilicon film is formed on the gate insulating film, a step in which one or more dopants of N, P, As, Sb, B, Al, and Ar are ion implanted into the polysilicon film, and a step in which a mask is selectively formed on the polysilicon film. The exposed portions of the polysilicon film are removed by isotropic dry etching. Thus, polysilicon electrodes can be formed so that in each polysilicon electrode, the hem part sandwiched between the bottom surface and the lateral surface of the polysilicon electrode has an inclination angle of 60° or less.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: July 30, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Setsuko Wakimoto
  • Patent number: 10361279
    Abstract: Methods for forming semiconductor structures are provided. The method includes forming a fin structure over a substrate and forming a gate structure across the fin structure. The method further includes forming a fin spacer on a sidewall of the fin structure and partially removing the fin spacer. The method further includes recessing the fin structure to form a recess and implanting dopants from the recess to form a doped region. The method further includes diffusing the dopants in the doped region to form an expanded doped region and forming a source/drain structure over the expanded doped region.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: July 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Chun-Hsiung Tsai, Cheng-Yi Peng, Shih-Chieh Chang, Kuo-Feng Yu
  • Patent number: 10355135
    Abstract: A semiconductor structure and a method of fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate; a metal gate structure on the substrate; and a spacer next to the metal gate structure having a skirting part extending into the metal gate structure and contacting the substrate. The metal gate structure includes a high-k dielectric layer and a metal gate electrode on the high-k dielectric layer.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Tung-Wen Cheng, Chang-Yin Chen, Mu-Tsang Lin
  • Patent number: 10348081
    Abstract: A current breaker includes a semiconductor substrate in which a switching element is provided, a first electrode provided on a surface of the semiconductor substrate, a second electrode provided on the surface and separated from the first electrode, a resistive film provided on the surface and connecting the first electrode and the second electrode, a terminal, a bonding wire connecting the first electrode and the terminal, and a control element configured to turn on the switching element when a voltage between both ends of a current path including the resistive film exceeds a threshold value. The switching element is connected to at least one of the first electrode and the second electrode.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: July 9, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Yukio Onishi
  • Patent number: 10319836
    Abstract: A vertical transistor structure is provided that includes a bottom source/drain structure that includes a doped semiconductor buffer layer that contains a first dopant species having a first diffusion rate, and an epitaxial doped semiconductor layer that contains a second dopant species that has a second diffusion rate that is less than the first diffusion rate. During a junction anneal, the first dopant species readily diffuses from the doped semiconductor buffer layer into a pillar portion of a base semiconductor substrate to provide the bottom source/drain extension and bottom source/drain junction. No diffusion overrun is observed. During the junction anneal, the second dopant species remains in the epitaxial doped semiconductor layer providing a low resistance contact. The second dopant species does not interfere with the bottom source/drain extension and bottom source/drain junction due to limited diffusion of the second dopant species.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Shogo Mochizuki
  • Patent number: 10319815
    Abstract: Embodiments of laterally diffused metal oxide semiconductor (LDMOS) transistors are provided. An LDMOS transistor includes a substrate having a source region, channel region, and a drain region. A first implant is formed to a first depth in the substrate. A gate electrode is formed over the channel region in the substrate between the source region and the drain region. A second implant is formed in the source region of the substrate; the second implant is laterally diffused under the gate electrode a predetermined distance. A third implant is formed to a second depth in the drain region of the substrate; the second depth is less than the first depth.
    Type: Grant
    Filed: May 26, 2014
    Date of Patent: June 11, 2019
    Assignee: NXP USA, Inc.
    Inventors: Xiaowei Ren, Robert P. Davidson, Mark A. DeTar
  • Patent number: 10297589
    Abstract: Field effect diode structures utilize a junction structure that has an L-shape in cross-section (a fin extending from a planar portion). An anode is positioned at the top surface of the fin, and a cathode is positioned at the end surface of the planar portion. The perpendicularity of the fin and the planar portion cause the anode and cathode to be perpendicular to one another. A first gate insulator contacts the fin between the top surface and the planar portion. A first gate conductor contacts the first gate insulator, and the first gate insulator is between the first gate conductor and the surface of the fin. Additionally, a second gate insulator contacts the planar portion between the end surface and the fin. A second gate conductor contacts the second gate insulator, and the second gate insulator is between the second gate conductor and the surface of the planar portion.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: May 21, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Robert J. Gauthier, Jr., Tom C. Lee, You Li, Rahul Mishra, Souvick Mitra, Andreas Scholze
  • Patent number: 10297676
    Abstract: Embodiments of a device are provided, including a semiconductor substrate including an active device area; a body region disposed in the semiconductor substrate within the active device area, wherein a channel is formed within the body region during operation; a doped isolation layer disposed in the semiconductor substrate underneath the active device area, the doped isolation layer including an opening positioned under the active device area; and a lightly-doped isolation layer disposed in the semiconductor substrate underneath the active device area, the lightly-doped isolation layer positioned at least within the opening and in electrical contact with the doped isolation layer, wherein the doped isolation layer and the lightly-doped isolation layer form a doped isolation barrier that extends across an entire lateral extent of the active device area.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: May 21, 2019
    Assignee: NXP USA, Inc.
    Inventors: Hongning Yang, Xin Lin, Ronghua Zhu
  • Patent number: 10297675
    Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region in a semiconductor fin. The semiconductor fin is etched with a first etching process to form a first cavity extending into the semiconductor fin adjacent to the channel region. The semiconductor fin is etched with a second etching process to form a second cavity that is volumetrically smaller than the first cavity and that adjoins the first cavity.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: May 21, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Alina Vinslava, Hsien-Ching Lo, Yongjun Shi, Jianwei Peng, Jianghu Yan, Yi Qi
  • Patent number: 10242996
    Abstract: A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: March 26, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Chun Chen, James Pak, Unsoon Kim, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
  • Patent number: 10224342
    Abstract: A semiconductor device includes an SOI substrate having a base substrate material, an active semiconductor layer positioned above the base substrate material and a buried insulating material layer positioned between the base substrate material and the active semiconductor layer. A gate structure is positioned above the active semiconductor layer and a back gate region is positioned in the base substrate material below the gate structure and below the buried insulating material layer. An isolation region electrically insulates the back gate region from the surrounding base substrate material, wherein the isolation region includes a plurality of implanted well regions that laterally contact and laterally enclose the back gate region and an implanted isolation layer that is formed below the back gate region.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: March 5, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Juergen Faul
  • Patent number: 10217639
    Abstract: A device including both drain extended metal-on-semiconductor (DE_MOS) and low-voltage metal-on-semiconductor (LV_MOS) transistors and methods of manufacturing the same are provided. In one embodiment, the method includes implanting ions of a first-type at a first energy level in a drain portion of a first DE_MOS transistor in a DE_MOS region of a substrate to form the first DE_MOS transistor, and implanting ions of the first-type at a second energy level in a LV_MOS region of the substrate adjust a voltage threshold of a first LV_MOS transistor, while concurrently implanting ions of the first-type at the second energy level in the drain portion of the first DE_MOS transistor to form a drain extension of the first DE_MOS transistor. Other embodiments are also provided.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: February 26, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sungkwon Lee, Igor G. Kouznetsov, Gyu-Chul Kim
  • Patent number: 10217668
    Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: February 26, 2019
    Assignee: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Scott E. Thompson, Damodar R. Thummalapally
  • Patent number: 10205024
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed over the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a field plate formed over the substrate between the gate structure and the drain region; wherein the field plate is coupled to the source region or a bulk electrode of the substrate. An associated method for fabricating the semiconductor structure is also disclosed.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: February 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Chang Cheng, Fu-Yu Chu, Ruey-Hsin Liu, Kuang-Hsin Chen, Chih-Hsin Ko, Shih-Fen Huang
  • Patent number: 10170353
    Abstract: Devices and methods of fabricating integrated circuit devices for dynamically applying bias to back plates and/or p-well regions are provided. One method includes, for instance: obtaining a wafer with a silicon substrate, at least one first oxide layer, at least one silicon layer, and at least one second oxide layer; forming at least one recess in the wafer; depositing at least one third oxide layer over the wafer and filling the at least one recess; depositing a silicon nitride layer over the wafer; and forming at least one opening having sidewalls and a bottom surface within the filled at least one recess. An intermediate semiconductor device is also disclosed.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: January 1, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Min-hwa Chi
  • Patent number: 10170589
    Abstract: A device includes a semiconductor region in a semiconductor chip, a gate dielectric layer over the semiconductor region, and a gate electrode over the gate dielectric. A drain region is disposed at a top surface of the semiconductor region and adjacent to the gate electrode. A gate spacer is on a sidewall of the gate electrode. A dielectric layer is disposed over the gate electrode and the gate spacer. A conductive field plate is over the dielectric layer, wherein the conductive field plate has a portion on a drain side of the gate electrode. A conductive via is disposed in the semiconductor region. A source electrode is underlying the semiconductor region, wherein the source electrode is electrically shorted to the conductive field plate through the conductive via.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chih Su, Hsueh-Liang Chou, Ruey-Hsin Liu, Chun-Wai Ng
  • Patent number: 10164006
    Abstract: Field-effect transistor structures for a laterally-diffused metal-oxide-semiconductor (LDMOS) device and methods of forming a LDMOS device. First and second fins are formed that extend vertically from a top surface of a substrate. A first isolation region is arranged between the first fin and the second fin. A body region of a first conductivity type is arranged partially in the substrate and partially in the second fin. A drain region of a second conductivity type is arranged partially in the substrate, partially in the first fin, and partially in the second fin. A source region is arranged within the body region in the first fin. A gate structure is arranged to overlap with a portion of the first fin. A second isolation region is arranged within the first fin, and is spaced along the first fin from the first isolation region.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: December 25, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jerome Ciavatti, Jagar Singh, Hui Zang
  • Patent number: 10096693
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a fin structure formed over a substrate and a gate structure formed across the fin structure. The semiconductor structure further includes a bottom spacer formed on a lower part of a sidewall of the gate structure and an upper spacer formed on an upper part of the sidewall of the gate structure. In addition, the upper spacer includes an air gap formed in a dielectric material.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: October 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Chih-Hao Wang, Ying-Keung Leung
  • Patent number: 10050119
    Abstract: Methods for selectively thinning a silicon channel area under a gate electrode and resulting devices are disclosed. Embodiments include providing a SOI substrate including a Si-layer; providing a first dummy-gate electrode over a first gate-oxide between first spacers over a first channel area of the Si-layer and a second dummy-gate electrode over a second gate-oxide between second spacers over a second channel area of the Si-layer; forming a S/D region adjacent each spacer; forming an oxide over the S/D regions and the spacers; removing the dummy-gate electrodes creating first and second cavities between respective first and second spacers; forming a mask with an opening over the first cavity; removing the first gate-oxide; thinning the Si-layer under the first cavity, forming a recess in the Si-layer; forming a third gate-oxide on recess side and bottom surfaces; and filling the recess and the cavities with metal, forming first and second RMG electrodes.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: August 14, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: George Robert Mulfinger, Dina H. Triyoso, Ryan Sporer
  • Patent number: 9991123
    Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate including a first doped region and a second doped region and a gate stack on the semiconductor substrate. The semiconductor device also includes a main spacer layer on a sidewall of the gate stack and a protection layer between the main spacer layer and the semiconductor substrate. The protection layer is doped with a quadrivalent element. The semiconductor device further includes an insulating layer formed over the semiconductor substrate and the gate stack and a contact formed in the insulating layer. The contact includes a first portion contacting the first doped region, and the contact includes a second portion contacting the second doped region. The first portion extends deeper into the semiconductor substrate than the second portion.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: June 5, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFATURING CO., LTD.
    Inventors: Mei-Chun Chen, Ching-Chen Hao, Wen-Hsin Chan, Chao-Jui Wang
  • Patent number: 9991356
    Abstract: Integrated circuit devices with counter-doped conductive gates. The devices have a semiconductor substrate that has a substrate surface. The devices also have a first well of a first conductivity type, a source of a second conductivity type, and a drain of the second conductivity type. A channel extends between the source and the drain. A conductive gate extends across the channel. The conductive gate includes a first gate region and a second gate region of the second conductivity type and a third gate region of the first conductivity type. The third gate region extends between the first and second gate regions. The devices further include a gate dielectric that extends between the conductive gate and the substrate and also include a silicide region in electrical communication with the first, second, and third gate regions. The methods include methods of manufacturing the devices.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: June 5, 2018
    Assignee: NXP USA, Inc.
    Inventors: Weize Chen, Richard J. de Souza, Md M. Hoque, Patrice M. Parris
  • Patent number: 9978864
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a first conductive type well region; a gate structure; a lightly-doped drain region and a lightly-doped source region disposed at two opposite sides of the gate structure; a second conductive type first doped region disposed in the lightly-doped drain region, wherein the doping concentration of the second conductive type first doped region is less than the doping concentration of the lightly-doped drain region; a heavily-doped source region disposed in the lightly-doped source region; and a heavily-doped drain region disposed in the second conductive type first doped region. The present disclosure also provides a method for manufacturing the semiconductor device.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: May 22, 2018
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Tse-Hsiao Liu, Sing-Lin Wu, Chung-Hsuan Wang, Yung-Lung Chou, Chia-Hao Lee, Chih-Cherng Liao
  • Patent number: 9941271
    Abstract: A fin-shaped field-effect transistor device is provided. The fin-shaped field effect transistor device may include a semiconductor substrate having a top and a bottom surface. The fin-shaped field effect transistor device may also include a fin structure disposed on the top surface of the semiconductor substrate, where the fin structure includes a first sidewall and a second sidewall opposite of the first sidewall. The first sidewall is adjacent to a first region of the top surface of the semiconductor substrate and the second sidewall is adjacent to a second region of the top surface of the semiconductor substrate. The fin-shaped field effect transistor device may also include an insulation layer disposed above the fin structure and the first and second regions of the top surface. The fin-shaped field effect transistor device may also include a conductor structure disposed above and adjacent to the insulation layer.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: April 10, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Shom Surendran Ponoth, Changyok Park, Akira Ito
  • Patent number: 9923092
    Abstract: In one embodiment, a method of forming a semiconductor device may include forming a buried region within a semiconductor region, including forming an opening in the buried region. The method may also include forming a drift region of a second conductivity type in the semiconductor region with at least a portion of the drift region overlying a first portion of the buried region. Another portion of the method may include forming a first drain region of the second conductivity type in the drift region wherein the first drain region does not overlie the buried region.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: March 20, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Thierry Coffi Herve Yao, Moshe Agam
  • Patent number: 9911815
    Abstract: Planar and non-planar field effect transistors with extended-drain structures, and techniques to fabricate such structures. In an embodiment, a field plate electrode is disposed over an extended-drain, with a field plate dielectric there between. The field plate is disposed farther from the transistor drain than the transistor gate. In a further embodiment, an extended-drain transistor has source and drain contact metal at approximately twice a pitch, of the field plate and the source and/or drain contact metal. In a further embodiment, an isolation dielectric distinct from the gate dielectric is disposed between the extended-drain and the field plate. In a further embodiment, the field plate may be directly coupled to one or more of the transistor gate electrode or a dummy gate electrode without requiring upper level interconnection.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: March 6, 2018
    Assignee: Intel Corporation
    Inventors: Nidhi Nidhi, Chia-Hong Jan, Walid M. Hafez
  • Patent number: 9911824
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a fin structure formed over a substrate and a gate structure formed across the fin structure. The semiconductor structure further includes a bottom spacer formed on a lower part of a sidewall of the gate structure and an upper spacer formed on an upper part of the sidewall of the gate structure. In addition, the upper spacer includes an air gap formed in a dielectric material.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: March 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Chih-Hao Wang, Ying-Keung Leung
  • Patent number: 9899417
    Abstract: A semiconductor structure includes a semiconductor substrate, a layer of electrically insulating material above the semiconductor substrate, and a layer of semiconductor material above the layer of electrically insulating material. A first transistor includes a first source region, a first drain region, and a first channel region formed in the semiconductor substrate, a first gate insulation layer positioned above the first channel region, and an electrically conductive first gate electrode, wherein the first gate insulation layer includes a first portion of the electrically insulating material. A second transistor includes a second source region, a second drain region, and a second channel region formed in the layer of semiconductor material, a second gate insulation layer positioned above the second channel region, and an electrically conductive second gate electrode, wherein a second portion of the layer of electrically insulating material is positioned below the second channel region.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: February 20, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Ralf Illgen
  • Patent number: 9859271
    Abstract: An ESD protection semiconductor device includes a substrate, a buried layer buried in the substrate, a first well formed in the substrate, a first doped region formed in the first well, a second doped region formed in the first well and adjacent to the first doped region, a second well formed in the first well, and a third doped region formed in the second well. The buried layer, the first well, the first doped region, and the third doped region include a first conductivity type while the second doped region and the second well include a second conductivity type complementary to the first conductivity type. The second well is spaced apart from the first doped region and the second doped region by the first well.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: January 2, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wei Lee, Li-Cih Wang, Tien-Hao Tang
  • Patent number: 9852993
    Abstract: A high voltage integrated device includes a source region and a drain region disposed in a semiconductor layer and spaced apart from each other, a drift region disposed in the semiconductor layer and surrounding the drain region, a channel region defined in the semiconductor layer and between the source region and the drift region, a trench insulation field plate disposed in the drift region, a recessed region provided in the trench isolation field plate, a metal field plate disposed over the trench insulation field plate, and filling the recessed region, a gate insulation layer provided over the channel region and extending over the drift region and over the trench insulation field plate, and a gate electrode disposed over the gate insulation layer.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: December 26, 2017
    Assignee: SK HYNIX SYSTEM IC INC.
    Inventor: Sung Kun Park