With Lightly Doped Portion Of Drain Region Adjacent Channel (e.g., Ldd Structure) Patents (Class 257/336)
  • Patent number: 10388794
    Abstract: A display device according to an exemplary embodiment of the present invention includes: a substrate; a plurality of transistors formed on the substrate; and a light-emitting device connected to the plurality of transistors, wherein the transistor includes a gate electrode, the plurality of transistors include a first transistor and a second transistor of which lateral wall slope angles of the gate electrode are different from each other, and the first transistor further includes a doping control member formed on a lateral wall of the gate electrode.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: August 20, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jong Chan Lee, Woong Hee Jeong, Dae Ho Kim, Young Ki Shin, Yoon Ho Khang, Myoung Geun Cha
  • Patent number: 10386718
    Abstract: A computer-implemented method includes modeling, using the computer, a photoresist profile in accordance with a magnitude of a gradient of an inhibitor concentration disposed in the photoresist. The photoresist is used during a process to form an integrated circuit. In one embodiment, the computer-implemented method further includes applying the modeled photoresist profile to reduce a distortion in a printed photoresist pattern caused by a response of the photoresist to an electromagnetic wave and/or particle beam during the process.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: August 20, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Cheng En Wu, Haiqing Wei, Qiaolin Zhang, Hua Song
  • Patent number: 10373872
    Abstract: A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region in a plane view. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping with the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping with the gate region.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: August 6, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Shih-Yin Hsiao, Ching-Chung Yang, Kuan-Liang Liu
  • Patent number: 10373944
    Abstract: Disclosed examples include integrated circuits, fabrication methods and ESD protection circuits to selectively conduct current between a protected node and a reference node during an ESD event, including a protection transistor, a first diode and a resistor formed in a first region of a semiconductor structure, and a second diode formed in a second region isolated from the first region by a polysilicon filled deep trench, where the first and second diodes include cathodes formed by deep N wells alongside the deep trench in the respective first and second regions to use integrated deep trench diode rings to set the ESD protection trigger voltage and prevent a parasitic deep N well/P buried layer junction from breakdown at lower than the rated voltage of the host circuitry.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: August 6, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Akram A. Salman, Muhammad Yusuf Ali
  • Patent number: 10374056
    Abstract: Disclosed is a method for producing a transistor device and a transistor device. The method includes: forming a source region of a first doping type in a body region of a second doping type in a semiconductor body; and forming a low-resistance region of the second doping type adjoining the source region in the body region. Forming the source region includes implanting dopant particles of the first doping type using an implantation mask via a first surface of the semiconductor body into the body region. Implanting the doping particles of the first doping type includes a tilted implantation.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: August 6, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Katarzyna Kowalik-Seidl, Bjoern Fischer, Winfried Kaindl, Markus Schmitt, Matthias Wegscheider
  • Patent number: 10366893
    Abstract: The present invention provides a process for producing a semiconductor device having a breakdown voltage heightened by improving the step coverage properties of the interlayer dielectric for covering polysilicon electrodes. The process includes a step in which a gate insulating film is formed on a silicon carbide substrate, a step in which a polysilicon film is formed on the gate insulating film, a step in which one or more dopants of N, P, As, Sb, B, Al, and Ar are ion implanted into the polysilicon film, and a step in which a mask is selectively formed on the polysilicon film. The exposed portions of the polysilicon film are removed by isotropic dry etching. Thus, polysilicon electrodes can be formed so that in each polysilicon electrode, the hem part sandwiched between the bottom surface and the lateral surface of the polysilicon electrode has an inclination angle of 60° or less.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: July 30, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Setsuko Wakimoto
  • Patent number: 10361279
    Abstract: Methods for forming semiconductor structures are provided. The method includes forming a fin structure over a substrate and forming a gate structure across the fin structure. The method further includes forming a fin spacer on a sidewall of the fin structure and partially removing the fin spacer. The method further includes recessing the fin structure to form a recess and implanting dopants from the recess to form a doped region. The method further includes diffusing the dopants in the doped region to form an expanded doped region and forming a source/drain structure over the expanded doped region.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: July 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Chun-Hsiung Tsai, Cheng-Yi Peng, Shih-Chieh Chang, Kuo-Feng Yu
  • Patent number: 10355135
    Abstract: A semiconductor structure and a method of fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate; a metal gate structure on the substrate; and a spacer next to the metal gate structure having a skirting part extending into the metal gate structure and contacting the substrate. The metal gate structure includes a high-k dielectric layer and a metal gate electrode on the high-k dielectric layer.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Tung-Wen Cheng, Chang-Yin Chen, Mu-Tsang Lin
  • Patent number: 10348081
    Abstract: A current breaker includes a semiconductor substrate in which a switching element is provided, a first electrode provided on a surface of the semiconductor substrate, a second electrode provided on the surface and separated from the first electrode, a resistive film provided on the surface and connecting the first electrode and the second electrode, a terminal, a bonding wire connecting the first electrode and the terminal, and a control element configured to turn on the switching element when a voltage between both ends of a current path including the resistive film exceeds a threshold value. The switching element is connected to at least one of the first electrode and the second electrode.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: July 9, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Yukio Onishi
  • Patent number: 10319815
    Abstract: Embodiments of laterally diffused metal oxide semiconductor (LDMOS) transistors are provided. An LDMOS transistor includes a substrate having a source region, channel region, and a drain region. A first implant is formed to a first depth in the substrate. A gate electrode is formed over the channel region in the substrate between the source region and the drain region. A second implant is formed in the source region of the substrate; the second implant is laterally diffused under the gate electrode a predetermined distance. A third implant is formed to a second depth in the drain region of the substrate; the second depth is less than the first depth.
    Type: Grant
    Filed: May 26, 2014
    Date of Patent: June 11, 2019
    Assignee: NXP USA, Inc.
    Inventors: Xiaowei Ren, Robert P. Davidson, Mark A. DeTar
  • Patent number: 10319836
    Abstract: A vertical transistor structure is provided that includes a bottom source/drain structure that includes a doped semiconductor buffer layer that contains a first dopant species having a first diffusion rate, and an epitaxial doped semiconductor layer that contains a second dopant species that has a second diffusion rate that is less than the first diffusion rate. During a junction anneal, the first dopant species readily diffuses from the doped semiconductor buffer layer into a pillar portion of a base semiconductor substrate to provide the bottom source/drain extension and bottom source/drain junction. No diffusion overrun is observed. During the junction anneal, the second dopant species remains in the epitaxial doped semiconductor layer providing a low resistance contact. The second dopant species does not interfere with the bottom source/drain extension and bottom source/drain junction due to limited diffusion of the second dopant species.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Shogo Mochizuki
  • Patent number: 10297676
    Abstract: Embodiments of a device are provided, including a semiconductor substrate including an active device area; a body region disposed in the semiconductor substrate within the active device area, wherein a channel is formed within the body region during operation; a doped isolation layer disposed in the semiconductor substrate underneath the active device area, the doped isolation layer including an opening positioned under the active device area; and a lightly-doped isolation layer disposed in the semiconductor substrate underneath the active device area, the lightly-doped isolation layer positioned at least within the opening and in electrical contact with the doped isolation layer, wherein the doped isolation layer and the lightly-doped isolation layer form a doped isolation barrier that extends across an entire lateral extent of the active device area.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: May 21, 2019
    Assignee: NXP USA, Inc.
    Inventors: Hongning Yang, Xin Lin, Ronghua Zhu
  • Patent number: 10297675
    Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region in a semiconductor fin. The semiconductor fin is etched with a first etching process to form a first cavity extending into the semiconductor fin adjacent to the channel region. The semiconductor fin is etched with a second etching process to form a second cavity that is volumetrically smaller than the first cavity and that adjoins the first cavity.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: May 21, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Alina Vinslava, Hsien-Ching Lo, Yongjun Shi, Jianwei Peng, Jianghu Yan, Yi Qi
  • Patent number: 10297589
    Abstract: Field effect diode structures utilize a junction structure that has an L-shape in cross-section (a fin extending from a planar portion). An anode is positioned at the top surface of the fin, and a cathode is positioned at the end surface of the planar portion. The perpendicularity of the fin and the planar portion cause the anode and cathode to be perpendicular to one another. A first gate insulator contacts the fin between the top surface and the planar portion. A first gate conductor contacts the first gate insulator, and the first gate insulator is between the first gate conductor and the surface of the fin. Additionally, a second gate insulator contacts the planar portion between the end surface and the fin. A second gate conductor contacts the second gate insulator, and the second gate insulator is between the second gate conductor and the surface of the planar portion.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: May 21, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Robert J. Gauthier, Jr., Tom C. Lee, You Li, Rahul Mishra, Souvick Mitra, Andreas Scholze
  • Patent number: 10242996
    Abstract: A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: March 26, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Chun Chen, James Pak, Unsoon Kim, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
  • Patent number: 10224342
    Abstract: A semiconductor device includes an SOI substrate having a base substrate material, an active semiconductor layer positioned above the base substrate material and a buried insulating material layer positioned between the base substrate material and the active semiconductor layer. A gate structure is positioned above the active semiconductor layer and a back gate region is positioned in the base substrate material below the gate structure and below the buried insulating material layer. An isolation region electrically insulates the back gate region from the surrounding base substrate material, wherein the isolation region includes a plurality of implanted well regions that laterally contact and laterally enclose the back gate region and an implanted isolation layer that is formed below the back gate region.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: March 5, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Juergen Faul
  • Patent number: 10217639
    Abstract: A device including both drain extended metal-on-semiconductor (DE_MOS) and low-voltage metal-on-semiconductor (LV_MOS) transistors and methods of manufacturing the same are provided. In one embodiment, the method includes implanting ions of a first-type at a first energy level in a drain portion of a first DE_MOS transistor in a DE_MOS region of a substrate to form the first DE_MOS transistor, and implanting ions of the first-type at a second energy level in a LV_MOS region of the substrate adjust a voltage threshold of a first LV_MOS transistor, while concurrently implanting ions of the first-type at the second energy level in the drain portion of the first DE_MOS transistor to form a drain extension of the first DE_MOS transistor. Other embodiments are also provided.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: February 26, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sungkwon Lee, Igor G. Kouznetsov, Gyu-Chul Kim
  • Patent number: 10217668
    Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: February 26, 2019
    Assignee: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Scott E. Thompson, Damodar R. Thummalapally
  • Patent number: 10205024
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed over the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a field plate formed over the substrate between the gate structure and the drain region; wherein the field plate is coupled to the source region or a bulk electrode of the substrate. An associated method for fabricating the semiconductor structure is also disclosed.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: February 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Chang Cheng, Fu-Yu Chu, Ruey-Hsin Liu, Kuang-Hsin Chen, Chih-Hsin Ko, Shih-Fen Huang
  • Patent number: 10170353
    Abstract: Devices and methods of fabricating integrated circuit devices for dynamically applying bias to back plates and/or p-well regions are provided. One method includes, for instance: obtaining a wafer with a silicon substrate, at least one first oxide layer, at least one silicon layer, and at least one second oxide layer; forming at least one recess in the wafer; depositing at least one third oxide layer over the wafer and filling the at least one recess; depositing a silicon nitride layer over the wafer; and forming at least one opening having sidewalls and a bottom surface within the filled at least one recess. An intermediate semiconductor device is also disclosed.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: January 1, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Min-hwa Chi
  • Patent number: 10170589
    Abstract: A device includes a semiconductor region in a semiconductor chip, a gate dielectric layer over the semiconductor region, and a gate electrode over the gate dielectric. A drain region is disposed at a top surface of the semiconductor region and adjacent to the gate electrode. A gate spacer is on a sidewall of the gate electrode. A dielectric layer is disposed over the gate electrode and the gate spacer. A conductive field plate is over the dielectric layer, wherein the conductive field plate has a portion on a drain side of the gate electrode. A conductive via is disposed in the semiconductor region. A source electrode is underlying the semiconductor region, wherein the source electrode is electrically shorted to the conductive field plate through the conductive via.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chih Su, Hsueh-Liang Chou, Ruey-Hsin Liu, Chun-Wai Ng
  • Patent number: 10164006
    Abstract: Field-effect transistor structures for a laterally-diffused metal-oxide-semiconductor (LDMOS) device and methods of forming a LDMOS device. First and second fins are formed that extend vertically from a top surface of a substrate. A first isolation region is arranged between the first fin and the second fin. A body region of a first conductivity type is arranged partially in the substrate and partially in the second fin. A drain region of a second conductivity type is arranged partially in the substrate, partially in the first fin, and partially in the second fin. A source region is arranged within the body region in the first fin. A gate structure is arranged to overlap with a portion of the first fin. A second isolation region is arranged within the first fin, and is spaced along the first fin from the first isolation region.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: December 25, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jerome Ciavatti, Jagar Singh, Hui Zang
  • Patent number: 10096693
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a fin structure formed over a substrate and a gate structure formed across the fin structure. The semiconductor structure further includes a bottom spacer formed on a lower part of a sidewall of the gate structure and an upper spacer formed on an upper part of the sidewall of the gate structure. In addition, the upper spacer includes an air gap formed in a dielectric material.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: October 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Chih-Hao Wang, Ying-Keung Leung
  • Patent number: 10050119
    Abstract: Methods for selectively thinning a silicon channel area under a gate electrode and resulting devices are disclosed. Embodiments include providing a SOI substrate including a Si-layer; providing a first dummy-gate electrode over a first gate-oxide between first spacers over a first channel area of the Si-layer and a second dummy-gate electrode over a second gate-oxide between second spacers over a second channel area of the Si-layer; forming a S/D region adjacent each spacer; forming an oxide over the S/D regions and the spacers; removing the dummy-gate electrodes creating first and second cavities between respective first and second spacers; forming a mask with an opening over the first cavity; removing the first gate-oxide; thinning the Si-layer under the first cavity, forming a recess in the Si-layer; forming a third gate-oxide on recess side and bottom surfaces; and filling the recess and the cavities with metal, forming first and second RMG electrodes.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: August 14, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: George Robert Mulfinger, Dina H. Triyoso, Ryan Sporer
  • Patent number: 9991356
    Abstract: Integrated circuit devices with counter-doped conductive gates. The devices have a semiconductor substrate that has a substrate surface. The devices also have a first well of a first conductivity type, a source of a second conductivity type, and a drain of the second conductivity type. A channel extends between the source and the drain. A conductive gate extends across the channel. The conductive gate includes a first gate region and a second gate region of the second conductivity type and a third gate region of the first conductivity type. The third gate region extends between the first and second gate regions. The devices further include a gate dielectric that extends between the conductive gate and the substrate and also include a silicide region in electrical communication with the first, second, and third gate regions. The methods include methods of manufacturing the devices.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: June 5, 2018
    Assignee: NXP USA, Inc.
    Inventors: Weize Chen, Richard J. de Souza, Md M. Hoque, Patrice M. Parris
  • Patent number: 9991123
    Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate including a first doped region and a second doped region and a gate stack on the semiconductor substrate. The semiconductor device also includes a main spacer layer on a sidewall of the gate stack and a protection layer between the main spacer layer and the semiconductor substrate. The protection layer is doped with a quadrivalent element. The semiconductor device further includes an insulating layer formed over the semiconductor substrate and the gate stack and a contact formed in the insulating layer. The contact includes a first portion contacting the first doped region, and the contact includes a second portion contacting the second doped region. The first portion extends deeper into the semiconductor substrate than the second portion.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: June 5, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFATURING CO., LTD.
    Inventors: Mei-Chun Chen, Ching-Chen Hao, Wen-Hsin Chan, Chao-Jui Wang
  • Patent number: 9978864
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a first conductive type well region; a gate structure; a lightly-doped drain region and a lightly-doped source region disposed at two opposite sides of the gate structure; a second conductive type first doped region disposed in the lightly-doped drain region, wherein the doping concentration of the second conductive type first doped region is less than the doping concentration of the lightly-doped drain region; a heavily-doped source region disposed in the lightly-doped source region; and a heavily-doped drain region disposed in the second conductive type first doped region. The present disclosure also provides a method for manufacturing the semiconductor device.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: May 22, 2018
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Tse-Hsiao Liu, Sing-Lin Wu, Chung-Hsuan Wang, Yung-Lung Chou, Chia-Hao Lee, Chih-Cherng Liao
  • Patent number: 9941271
    Abstract: A fin-shaped field-effect transistor device is provided. The fin-shaped field effect transistor device may include a semiconductor substrate having a top and a bottom surface. The fin-shaped field effect transistor device may also include a fin structure disposed on the top surface of the semiconductor substrate, where the fin structure includes a first sidewall and a second sidewall opposite of the first sidewall. The first sidewall is adjacent to a first region of the top surface of the semiconductor substrate and the second sidewall is adjacent to a second region of the top surface of the semiconductor substrate. The fin-shaped field effect transistor device may also include an insulation layer disposed above the fin structure and the first and second regions of the top surface. The fin-shaped field effect transistor device may also include a conductor structure disposed above and adjacent to the insulation layer.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: April 10, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Shom Surendran Ponoth, Changyok Park, Akira Ito
  • Patent number: 9923092
    Abstract: In one embodiment, a method of forming a semiconductor device may include forming a buried region within a semiconductor region, including forming an opening in the buried region. The method may also include forming a drift region of a second conductivity type in the semiconductor region with at least a portion of the drift region overlying a first portion of the buried region. Another portion of the method may include forming a first drain region of the second conductivity type in the drift region wherein the first drain region does not overlie the buried region.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: March 20, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Thierry Coffi Herve Yao, Moshe Agam
  • Patent number: 9911815
    Abstract: Planar and non-planar field effect transistors with extended-drain structures, and techniques to fabricate such structures. In an embodiment, a field plate electrode is disposed over an extended-drain, with a field plate dielectric there between. The field plate is disposed farther from the transistor drain than the transistor gate. In a further embodiment, an extended-drain transistor has source and drain contact metal at approximately twice a pitch, of the field plate and the source and/or drain contact metal. In a further embodiment, an isolation dielectric distinct from the gate dielectric is disposed between the extended-drain and the field plate. In a further embodiment, the field plate may be directly coupled to one or more of the transistor gate electrode or a dummy gate electrode without requiring upper level interconnection.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: March 6, 2018
    Assignee: Intel Corporation
    Inventors: Nidhi Nidhi, Chia-Hong Jan, Walid M. Hafez
  • Patent number: 9911824
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a fin structure formed over a substrate and a gate structure formed across the fin structure. The semiconductor structure further includes a bottom spacer formed on a lower part of a sidewall of the gate structure and an upper spacer formed on an upper part of the sidewall of the gate structure. In addition, the upper spacer includes an air gap formed in a dielectric material.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: March 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Chih-Hao Wang, Ying-Keung Leung
  • Patent number: 9899417
    Abstract: A semiconductor structure includes a semiconductor substrate, a layer of electrically insulating material above the semiconductor substrate, and a layer of semiconductor material above the layer of electrically insulating material. A first transistor includes a first source region, a first drain region, and a first channel region formed in the semiconductor substrate, a first gate insulation layer positioned above the first channel region, and an electrically conductive first gate electrode, wherein the first gate insulation layer includes a first portion of the electrically insulating material. A second transistor includes a second source region, a second drain region, and a second channel region formed in the layer of semiconductor material, a second gate insulation layer positioned above the second channel region, and an electrically conductive second gate electrode, wherein a second portion of the layer of electrically insulating material is positioned below the second channel region.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: February 20, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Ralf Illgen
  • Patent number: 9859271
    Abstract: An ESD protection semiconductor device includes a substrate, a buried layer buried in the substrate, a first well formed in the substrate, a first doped region formed in the first well, a second doped region formed in the first well and adjacent to the first doped region, a second well formed in the first well, and a third doped region formed in the second well. The buried layer, the first well, the first doped region, and the third doped region include a first conductivity type while the second doped region and the second well include a second conductivity type complementary to the first conductivity type. The second well is spaced apart from the first doped region and the second doped region by the first well.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: January 2, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wei Lee, Li-Cih Wang, Tien-Hao Tang
  • Patent number: 9852993
    Abstract: A high voltage integrated device includes a source region and a drain region disposed in a semiconductor layer and spaced apart from each other, a drift region disposed in the semiconductor layer and surrounding the drain region, a channel region defined in the semiconductor layer and between the source region and the drift region, a trench insulation field plate disposed in the drift region, a recessed region provided in the trench isolation field plate, a metal field plate disposed over the trench insulation field plate, and filling the recessed region, a gate insulation layer provided over the channel region and extending over the drift region and over the trench insulation field plate, and a gate electrode disposed over the gate insulation layer.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: December 26, 2017
    Assignee: SK HYNIX SYSTEM IC INC.
    Inventor: Sung Kun Park
  • Patent number: 9837323
    Abstract: The present disclosure provides a method for forming a semiconductor structure. The method includes providing a semiconductor substrate; forming a first active region, a second active region, a third active region, and a fourth active region in the semiconductor substrate; and forming a middle-voltage P well region (MVPW) in each of the first active region and the second region simultaneously and forming a middle-voltage N well (MVNW) region in each of the third active region and the fourth active region simultaneously.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: December 5, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Chih Chun Tai, Lei Fang, Dae Sub Jung, Gangning Wang, Guangli Yang, Jiao Wang, Hong Sun, Yunpeng Peng
  • Patent number: 9825155
    Abstract: The magnetoresistive element includes a semiconductor channel layer, a pinned layer disposed on the semiconductor channel layer via a first tunnel layer, a free layer disposed on the semiconductor channel layer via a second tunnel layer, wherein the semiconductor channel layer includes a first region containing an interface with the first tunnel layer, a second region containing an interface with the second tunnel layer, and a third region, impurity concentrations in the first and second regions are higher than 1×1019 cm?3, an impurity concentration in the third region is 1×1019 cm?3 or less, the first and second regions are separated by the third region, and the impurity concentrations in the first and second regions decrease in the thickness direction of the semiconductor channel layer from the interface between the semiconductor channel layer and the first tunnel layer and the interface between the semiconductor channel layer and the second tunnel layer.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: November 21, 2017
    Assignee: TDK CORPORATION
    Inventors: Tomoyuki Sasaki, Tohru Oikawa
  • Patent number: 9825168
    Abstract: A semiconductor device includes a semiconductor substrate and a first well region formed in the semiconductor substrate. An insulator is formed in and over a portion of the first well region and a second well region is formed in the first well region at a first side of the insulator. A first doped region is formed in the second well region, and a second doped region is formed in the first well region at a second side opposite the first side of the insulator. A gate structure is formed over the insulator, the first well region between the second well region and the insulator, and the second well region. An isolation element is formed in the semiconductor substrate, surrounding the first well region and the second well region. The first and second doped regions are formed with asymmetric configurations from a top view.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: November 21, 2017
    Assignee: MEDIATEK INC.
    Inventors: Cheng Hua Lin, Yan-Liang Ji
  • Patent number: 9748383
    Abstract: A Metal Oxide Semiconductor (MOS) transistor comprising: a source; a gate; and a drain, the source, gate and drain being located in or on a well structure of a first doping polarity located in or on a substrate; wherein at least one of the source and the drain comprises a first structure comprising: a first region forming a first drift region, the first region being of a second doping polarity opposite the first doping polarity; a second region of the second doping polarity in or on the first region, the second region being a well region and having a doping concentration which is higher than the doping concentration of the first region; and a third region of the second doping polarity in or on the second region. Due to the presence of the second region the transistor may have a lower ON resistance when compared with a similar transistor which does not have the second region. The breakdown voltage may be influenced only to a small extent.
    Type: Grant
    Filed: February 12, 2009
    Date of Patent: August 29, 2017
    Assignee: X-FAB SEMICONDUCTOR FOUNDRIES AG
    Inventors: Elizabeth Ching Tee Kho, Zheng Chao Liu, Deb Kumar Pal, Michael Mee Gouh Tiong, Jian Liu, Kia Yaw Kee
  • Patent number: 9735270
    Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Robert S. Chau, Tahir Ghani, Kaizad R. Mistry
  • Patent number: 9722094
    Abstract: The present invention proposes a TFT, an array substrate, and a method of forming a TFT. The TFT includes a substrate, a buffer layer, a patterned poly-si layer, an isolation layer, a gate layer, and a source/drain pattern layer. The poly-si layer includes a heavily doped source and a heavily doped drain, and a channel. The gate layer includes a first gate area and a second gate area. The source/drain pattern layer includes a source pattern, a drain pattern and a bridge pattern, with the source pattern electrically connecting the heavily doped source, the drain pattern electrically connecting the heavily doped drain, and one end of the bridge pattern connecting the first gate area and the second gate area. The driving ability of the present inventive TFT is enhanced without affecting the leakage current.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: August 1, 2017
    Assignees: Shenzhen China Star Optoelectronics Technology Co., Ltd, Wuhan China Star Optoelectronics Technology Co., Ltd
    Inventors: Mang Zhao, Gui Chen
  • Patent number: 9698015
    Abstract: Embodiments of the present disclosure provide methods for patterning rectangular features with a sequence of lithography, atomic layer deposition (ALD) and etching. Embodiment of the present disclosure includes forming first line clusters along a first direction and second line clusters over the first line clusters in a direction traversing the first direction. The first and second line clusters both include core lines formed from a core material, spacers formed from first and second materials by ALD and etching. After formation of the first and second line clusters, rectangular openings can be formed by selectively etching one or two of the core material, the first material or the second material.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: July 4, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Srinivas D. Nemani
  • Patent number: 9679818
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first gate stack positioned over the semiconductor substrate. The semiconductor device structure includes a first doped structure and a second doped structure positioned at two opposite sides of the first gate stack and embedded in the semiconductor substrate. The semiconductor device structure includes a second gate stack positioned over the semiconductor substrate and adjacent to the second doped structure. The semiconductor device structure includes a third gate stack positioned over the semiconductor substrate. The semiconductor device structure includes an isolation structure embedded in the semiconductor substrate and between the second gate stack and the third gate stack. The isolation structure is wider and thinner than the second doped structure, and the isolation structure is made of an epitaxial material.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: June 13, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: An-Lun Lo, Wei-Shuo Ho, Tzong-Sheng Chang, Chrong-Jung Lin, Ya-Chin King
  • Patent number: 9653594
    Abstract: A system and method for forming and using a liner is provided. An embodiment comprises forming an opening in an inter-layer dielectric over a substrate and forming the liner along the sidewalls of the opening. A portion of the liner is removed from a bottom of the opening, and a cleaning process may be performed through the liner. By using the liner, damage to the sidewalls of the opening from the cleaning process may be reduced or eliminated. Additionally, the liner may be used to help implantation of ions within the substrate.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: May 16, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Chi Tsai, Chia-Han Lai, Yung-Chung Chen, Mei-Yun Wang, Chii-Ming Wu, Fang-Cheng Chen, Huang-Ming Chen, Ming-Ta Lei
  • Patent number: 9647103
    Abstract: The current invention introduces a modulated field element incorporated into the semiconductor device outside the controlling electrode and active areas. This element changes its conductivity and/or dielectric properties depending on the electrical potentials of the interface or interfaces between the modulated field element and the semiconductor device and/or incident electromagnetic radiation. The element is either connected to only one terminal of the semiconductor device, or not connected to any terminal of a semiconductor device nor to its active area(s). Such an element can be used as modulated field plate, or a part of a field plate, as a passivation layer or its part, as a guard ring or its part, as a smart field or charge control element or its part, as a feedback element or its part, as a sensor element or its part, as an additional electrode or its part, as an electromagnetic signal path or its part, and/or for any other functions optimizing or modernizing device performance.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: May 9, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Alexei Koudymov, Michael Shur, Remigijus Gaska
  • Patent number: 9646965
    Abstract: An integrated semiconductor transistor chip for use in a buck converter includes a high side transistor formed on the chip and comprising a laterally diffused metal oxide semiconductor (LDMOS) transistor and a low side transistor formed on the chip and comprising a source down metal oxide semiconductor field effect transistor (MOSFET). The chip also includes a substrate of the chip for use as a source for the low side transistor and an n-doped well for isolation of the high side transistor from the source of the low side transistor.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: May 9, 2017
    Assignee: Texas Instruments Incorporated
    Inventors: Jun Wang, Frank Baiocchi, Haian Lin
  • Patent number: 9633906
    Abstract: A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: April 25, 2017
    Assignees: International Business Machines Corporation, GlobalFoundries, Inc.
    Inventors: Xiuyu Cai, Kangguo Cheng, Johnathan E. Faltermeier, Ali Khakifirooz, Theodorus E. Standaert, Ruilong Xie
  • Patent number: 9608066
    Abstract: A field effect transistor device includes a gate structure formed over a channel region in a semiconductor material. An inner spacer is formed on sidewalls of the gate structure and over an extension region of the semiconductor material. The inner spacer includes charge or dipoles. A source/drain region is formed adjacent to the gate structure. An inversion layer is formed in the extension region induced by the inner spacer to form a conductive link between the channel region and the source/drain region.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: March 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Pouya Hashemi, Vijay Narayanan, Yanning Sun
  • Patent number: 9601585
    Abstract: A transistor includes an isolation region surrounding an active region. The transistor also includes a gate dielectric layer over a portion of the active region. The transistor further includes a gate electrode over the gate dielectric layer. The portion of the active region under the gate dielectric layer includes a channel region between a drain region and a source region, and at least one wing region adjoining the channel region. The at least one wing region has a base edge adjoining the channel region. The at least one wing region is polygonal or curved.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: March 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Liang Chu, Fei-Yuh Chen, Yi-Sheng Chen, Shih-Kuang Hsiao, Chun Lin Tsai, Kong-Beng Thei
  • Patent number: 9583392
    Abstract: A system and method for manufacturing a carbon layer is provided. An embodiment comprises depositing a first metal layer on a substrate, the substrate comprising carbon. A silicide is epitiaxially grown on the substrate, the epitaxially growing the silicide also forming a layer of carbon over the silicide. In an embodiment the carbon layer is graphene, and may be transferred to a semiconductor substrate for further processing to form a channel within the graphene.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: February 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Mark van Dal
  • Patent number: 9583596
    Abstract: An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: February 28, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Philipp Steinmann, Amitava Chatterjee, Sameer Pendharkar