CHIP PACKAGE STRUCTURE AND MANUFACTURING METHODS THEREOF
A chip package structure includes a chip module, a plurality of pre-patterned structures, a filling material layer, and a redistribution layer. The chip module includes a chip including an upper surface, a side surface, and an active surface. The pre-patterned structures are disposed around the chip. Each of the pre-patterned structures includes a circuit, a first surface, an upper surface opposite the first surface, and a side surface. The filling material layer encapsulates the chip and the pre-patterned structures. The filling material layer includes a second surface, and encapsulates the upper and side surfaces of the chip, and the upper and side surfaces of each of the pre-patterned structures. The active surface, each first surface, and the second surface are substantially co-planar. The redistribution layer is disposed on the active surface, each first surface, and the second surface. The redistribution layer electrically connects the chip and each circuit.
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This application is a continuation of U.S. patent application Ser. No. 12/648,270, filed Dec. 28, 2009, which claims the benefit of Taiwan application Serial No. 98120583, filed Jun. 19, 2009, the subject matter of which is incorporated herein by reference.
FIELD OF THE INVENTIONThe present invention generally relates to electronic device packaging. More particularly, the present invention relates to a chip package structure and manufacturing methods thereof.
BACKGROUND OF THE INVENTIONIn order to increase the density of electrical connections of the package structure, a through molding compound technology is typically applied to the structural material layer 104 first, such as mechanical drilling through the structural material layer 104 to enable electrical connectivity to the metal layer 110. However, at present, the through molding compound technology is costly.
SUMMARY OF THE INVENTIONAccordingly, one aspect of the present invention is directed to a chip package structure and manufacturing methods thereof The chip package structure may be a single-chip or multi-chip package structure.
In one innovative aspect, the invention relates to a chip package structure. In one embodiment, the chip package structure includes a chip module, a plurality of pre-patterned structures, a filling material layer, and a redistribution layer. The chip module includes a chip including an upper surface, a side surface, and an active surface. The plurality of pre-patterned structures are disposed around the chip. Each of the plurality of pre-patterned structures includes a circuit, a first surface, an upper surface opposite the first surface, and a side surface. The filling material layer encapsulates the chip and the plurality of pre-patterned structures. The filling material layer includes a second surface, and encapsulates the upper surface of the chip, the side surface of the chip, the upper surface of each of the plurality of pre-patterned structures, and the side surface of each of the plurality of pre-patterned structures. The active surface, the first surface of each of the plurality of pre-patterned structures, and the second surface are substantially co-planar. The redistribution layer is disposed on the active surface, the first surface of each of the plurality of pre-patterned structures, and the second surface. The redistribution layer electrically connects the chip and the circuit in each of the plurality of pre-patterned structures.
In another innovative aspect, the invention relates to a method of forming a chip package structure. In one embodiment, the method includes providing a plurality of separate pre-patterned structures, where each of the plurality of separate pre-patterned structures includes a circuit, a first surface, an upper surface opposite the first surface, and a side surface. The method further includes providing a chip module including a chip, where the chip includes an upper surface, a side surface, and an active surface opposite the upper surface of the chip. The method further includes providing a carrier. The method further includes disposing the plurality of separate pre-patterned structures and the chip adjacent to the carrier such that the plurality of separate pre-patterned structures are positioned around the chip. The method further includes forming a filling material layer around the chip and the plurality of separate pre-patterned structures so that: (a) the filling material layer substantially covers the upper surface of the chip, the side surface of the chip, the upper surface of each of the plurality of separate pre-patterned structures, and the side surface of each of the plurality of separate pre-patterned structures; and (b) a second surface of the filling material layer is substantially co-planar with the active surface and the first surface of each of the plurality of separate pre-patterned structures. The method further includes disposing a redistribution layer on the active surface, the first surface of each of the plurality of separate pre-patterned structures, and the second surface, wherein the redistribution layer electrically connects the chip and the circuit in each of the plurality of separate pre-patterned structures.
The accompanying drawings are included to provide a further understanding of some embodiments of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of some embodiments of the invention.
Reference will now be made in detail to some embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the descriptions to refer to the same or like parts.
DefinitionsThe following definitions apply to some of the aspects described with respect to some embodiments of the invention. These definitions may likewise be expanded upon herein.
As used herein, the singular terms “a”, “an” and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to a protruding metal block can include multiple protruding metal blocks unless the context clearly dictates otherwise.
As used herein, the term “set” refers to a collection of one or more components. Thus, for example, a set of layers can include a single layer or multiple layers. Components of a set also can be referred to as members of the set. Components of a set can be the same or different. In some instances, components of a set can share one or more common characteristics.
As used herein, the term “adjacent” refers to being near or adjoining. Adjacent components can be spaced apart from one another or can be in actual or direct contact with one another. In some instances, adjacent components can be connected to one another or can be formed integrally with one another.
As used herein, terms such as “inner,” “top,” “upper,” “bottom,” “above,” “below,” “upwardly,” “downwardly,” “side,” and “lateral” refer to a relative orientation of a set of components, such as in accordance with the drawings, but do not require a particular orientation of those components during manufacturing or use.
As used herein, the terms “connect”, “connected” and “connection” refer to an operational coupling or linking. Connected components can be directly coupled to one another or can be indirectly coupled to one another, such as via another set of components.
As used herein, the terms “substantially” and “substantial” refer to a considerable degree or extent. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation, such as accounting for typical tolerance levels of the manufacturing operations described herein.
As used herein, the terms “conductive” refers to an ability to transport an electric current. Electrically conductive materials typically correspond to those materials that exhibit little or no opposition to flow of an electric current. One measure of electrical conductivity is in terms of Siemens per meter (“S·m-1”). Typically, an electrically conductive material is one having a conductivity greater than about 104 S·m-1, such as at least about 105 S·m-1 or at least about 106 S·m-1. Electrical conductivity of a material can sometimes vary with temperature. Unless otherwise specified, electrical conductivity of a material is defined at room temperature.
Aspects of the present invention can be used for fabricating various package structures, such as stacked type packages, multiple-chip packages, or high frequency device packages.
According to embodiments of the chip package structure of the invention, the pre-patterned structure is placed in the structural material around the embedded chip, and at least one surface of the chip, the pre-patterned structure and the filling material layer are substantially co-planar. Embodiments of the invention are applicable to single-chip and multi-chip package structures, as well as to fan-out and fan-in package structures. Embodiments of the package structures of the invention can be conveniently stacked to form a package-on-package (POP) package.
First EmbodimentReferring to
The pre-patterned structure 214 of this embodiment of the invention is placed in the structural material around the embedded chip 200 of the chip package structure 200, and serves as a supporting structure of the package, not only increasing the density of electrical connections in small-sized packages, but also incurring lower cost than conventional through molding compound technology. Furthermore, in this embodiment of the invention, the active surface 220a, each first surface 214a and the second surface 240a are substantially co-planar, not only effectively increasing the process conformity rate of the redistribution layer 260, but also incurring lower manufacturing cost. For example, the co-planar design may enable coatings such as a dielectric layer 262 (shown in
Referring to
As indicated in
Referring to
In
Referring to
Then, the process carrier 250, the filling material layer 240, the chip 220, and the pre-patterned structures 214 encapsulated by the filling material layer 240 are inverted as indicated in
Next, a redistribution layer 260 (illustrated in
Referring to
Compared with the first embodiment, this second embodiment of the invention omits the forming a plurality of second openings 2661 on the second dielectric layer 262 and accommodating the conductive material 2662 in a plurality of second openings 2661 (shown in
Compared with the first embodiment, this third embodiment of the invention omits the forming the hole 2401 on the filling material layer 240 and accommodating the conductive material 2402 (shown in
Compared with the third embodiment, this fourth embodiment of the invention omits forming a plurality of second openings 2661 on the second dielectric layer 262 and accommodating the conductive material 2662 in a plurality of second openings 2661 (shown in
Referring to
The pre-patterned structure 314 of this fifth embodiment of the invention is placed in the structural material around the embedded chip 300 of the chip package structure 300, and serves as a supporting structure of the package, not only increasing the density of electrical connections in small-sized packages, but also incurring lower cost than the conventional through molding compound technology. Furthermore, in this fifth embodiment of the invention, the active surface 220a, each first surface 214a, and the second surface 240a are substantially co-planar, not only effectively increasing the process conformity rate of the redistribution layer 360, but also incurring lower manufacturing cost. For example, the co-planar design may enable coatings such as a dielectric layer 362 (shown in
Referring to
As indicated in
Referring to
In
Referring to
Next, in
Then, the process carrier 350 including an adhesive layer 352, the protection layer 380, the adhesive layer 382, the filling material layer 340, the chip 320, and the pre-patterned structures 314 encapsulated by the filling material 340 are inverted as indicated in
Next, a redistribution layer 360 (illustrated in
Referring to
Compared with the fifth embodiment, another embodiment of the invention omits forming a plurality of second openings 3661 on the second dielectric layer 362 and accommodating the conductive material 3662 in a plurality of second openings 3661 (shown in
Compared with the fifth embodiment, yet another embodiment of the invention includes the processing shown in
Compared with the fifth embodiment, a further embodiment omits forming a plurality of second openings 3661 on the second dielectric layer 362 and accommodating the conductive material 3662 in a plurality of second openings 3661 (shown in
The chip package structure disclosed in the above embodiments is a single-chip package structure, but can be a multi-chip package structure if the chip module includes a plurality of chips. There are a plurality of pre-patterned structures disposed around each chip. Furthermore, the active surface of the chips, the second surface of the filling material layer, and the first surfaces of the pre-patterned structures are substantially co-planar.
Furthermore, the single-chip or the multi-chip package structure disclosed in the above embodiments can be stacked to form a package-on-package (POP) package, which includes a plurality of identical or different packages sequentially stacked. Referring to
The chip package structure disclosed in the above described embodiments of the invention has many advantages as exemplified below.
1. The pre-patterned structure placed in the structural material around the embedded chip serves as a supporting structure of the package, not only increasing the density of electrical connection in small-sized packages, but also incurring lower cost than conventional through molding compound technology.
2. The design that the active surface of the chip, each first surface of each pre-patterned structure, and the second surface of the filling material layer are substantially co-planar effectively increases the process conformity rate of the redistribution layer and reduces the manufacturing cost. For example, the co-planar design may enable coatings such as a dielectric layer 262 (shown in
3. Embodiments of the invention are very flexible, and are applicable to single-chip and multi-chip package structures as well as fan-out and fan-in package structures. Package structures of embodiments of the invention can be conveniently stacked to form a package-on-package (POP) package.
While the invention has been described by way of example and in terms of several embodiments, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
Claims
1. A semiconductor package, comprising:
- a chip having an active surface;
- a pre-patterned structure disposed adjacent to lateral surfaces of the chip, the pre-patterned structure having a contact on a surface oriented in the same direction as the active surface;
- a redistribution layer that electrically connects the active surface of the chip with the contact; and
- a filling material that covers portions of the chip, exposing the active surface and the pre-patterned structure.
2. The semiconductor package of claim 1, wherein the active surface of the chip is substantially co-planar with a surface of the pre-patterned structure.
3. The semiconductor package of claim 2, wherein the redistribution layer is disposed adjacent to the active surface of the chip and the substantially co-planar surface of the pre-patterned structure.
4. The semiconductor package of claim 1, wherein the pre-patterned structure includes interconnected trace layers.
5. The semiconductor package of claim 1, wherein the filling material covers the lateral surfaces of the chip.
6. The semiconductor package of claim 1, wherein the filling material substantially covers a surface of the pre-patterned structure and has an opening to expose a contact on the surface of the pre-patterned structure.
7. The semiconductor package of claim 1, further including a second redistribution layer disposed adjacent to an inactive surface of the chip and electrically connected to the pre-patterned structure.
8. A semiconductor package, comprising:
- a chip having an active surface;
- an interposer disposed adjacent to a lateral surface of the chip, the interposer having a contact on a surface oriented in the same direction as the active surface;
- a redistribution layer that electrically connects the active surface of the chip with the contact; and
- a filling material that covers portions of the chip, exposing the active surface and the pre-patterned structure.
9. The semiconductor package of claim 8, wherein the active surface of the chip is substantially co-planar with a surface of the interposer.
10. The semiconductor package of claim 9, wherein the redistribution layer is disposed adjacent to the active surface of the chip and the substantially co-planar surface of the interposer.
11. The semiconductor package of claim 8, wherein the interposer includes interconnected trace layers.
12. The semiconductor package of claim 8, wherein the filling material covers the lateral surfaces of the chip.
13. The semiconductor package of claim 8, wherein the filling material substantially covers a surface of the interposer and has an opening to expose a contact on the surface of the interposer.
14. The semiconductor package of claim 8, further including a second redistribution layer disposed adjacent to an inactive surface of the chip and electrically connected to the interposer.
15. The semiconductor package of claim 14, wherein the filling material has an opening wherein the second redistribution layer is electrically connected to the interposer through the opening.
16. The semiconductor package of claim 8, further comprising an adhesive layer disposed on a surface of the filling material.
17. The semiconductor package of claim 16, further comprising a protection layer disposed on the adhesive layer, wherein the adhesive layer connects the protection layer to the surface of the filling material.
18. A method of forming a semiconductor package, comprising:
- providing a chip;
- providing a plurality of separate pre-patterned structures, wherein each of the plurality of separate pre-patterned structures includes a circuit;
- providing a carrier;
- disposing the plurality of separate pre-patterned structures and the chip on the carrier such that the plurality of separate pre-patterned structures are positioned adjacent to lateral sides of the chip; and
- disposing a filling material around the chip and the plurality of separate pre-patterned structures, exposing an active surface of the chip.
19. The method of claim 18, wherein each of the plurality of separate pre-patterned structures includes multiple interconnected trace layers.
20. The method of claim 18, further comprising:
- creating a slot on a surface of each of the separate pre-patterned structures to expose the circuit of the pre-patterned structure; and
- forming a redistribution layer disposed adjacent to the active surface of the chip and substantially co-planar surfaces of the plurality of the separate pre-patterned structures, wherein the redistribution layer electrically connects the chip and the circuit in each of the plurality of separate pre-patterned structures through the slots.
Type: Application
Filed: Jan 9, 2012
Publication Date: May 3, 2012
Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC. (Kaohsiung)
Inventors: Chaofu Weng (Tainan City), Yi Ting Wu (Chiayi City)
Application Number: 13/346,567
International Classification: H01L 23/52 (20060101); H01L 21/56 (20060101);