Abstract: A method includes disposing a plurality of active solder pads and at least one mechanical support solder pad on the substrate. The plurality of active solder pads provide areas for mechanical bonding of the substrate to at least one device contact pad disposed on a semiconductor die. The at least one mechanical support solder pad provides an area for mechanical bonding of the substrate to at least one dummy device contact pad disposed on the semiconductor die. The method further includes mechanically bonding the substrate to the semiconductor die by forming solder joints between the plurality of active solder pads and the at least one device contact pad, and between the at least one mechanical support pad and the at least one dummy device contact pad.

Abstract: A semiconductor device including a semiconductor chip, an insulating circuit board having a circuit pattern formed on an insulating plate, a case including a frame part having an opening that is substantially rectangular in a plan view of the semiconductor device, inner wall surfaces of the frame part at the opening forming a storage part to store the insulating circuit board, and a printed circuit board which has a flat plate shape and which protrudes from one of the inner wall surfaces of the frame part toward the storage part. The semiconductor device further includes a sealing material filled in the storage part, to thereby seal the semiconductor chip and the printed circuit board. A front surface of the sealing material forms a sealing surface, and in a thickness direction of the semiconductor chip, the sealing surface is higher around the printed circuit board than around the semiconductor chip.

Abstract: A semiconductor device has a substrate. An electrical component is disposed over a surface of the substrate. An encapsulant is deposited over the electrical component and substrate. A portion of the surface of the substrate remains exposed from the encapsulant. A shielding layer is formed over the encapsulant. A portion of the shielding layer is removed to expose the portion of the surface of the substrate.

Abstract: A package structure including a first die, an encapsulant, a first circuit structure, a second circuit structure, a conductive connector, a second die, and a filler is provided. The encapsulant covers the first die and has a first surface and a second surface opposite to each other. The first circuit structure is disposed on the first surface. The second circuit structure is disposed on the second surface. The conductive connector penetrates the encapsulant. The second die is disposed on the second circuit structure. The second die has an optical signal transmission area. The filler is disposed between the second die and the second circuit structure. An upper surface of the second circuit structure has a groove. The upper surface includes a first area and a second area disposed on opposite sides of the groove. The filler directly contacts the first area. The filler is disposed away from the second area.

Abstract: A printed circuit board includes an insulating layer; and an external connection pad embedded in the insulating layer and having one surface exposed. The external connection pad may include a base pad portion having a first pattern portion in contact with a side surface of the insulating layer and having a first width, and a second pattern portion protruding from the first pattern portion and having a second width smaller than the first width, the second pattern portion having a gap with the side surface of the insulating layer, and a surface treatment layer disposed in the gap between the second pattern portion and the insulating layer and extending on an upper surface of the second pattern portion.

Abstract: Example embodiments of systems and methods for creating a chip fraud prevention system with a fraud prevention fluid are provided. A chip fraud prevention system includes a device including a chip. The chip may be at least partially encompassed in a chip pocket which contains a fraud prevention fluid. The fraud prevention fluid may be contained in a capsule or implemented as an adhesive. One or more connections may be communicatively coupled to at least one surface of the chip. The one or more connections may be placed in close proximity and/or in contact to the fraud prevention fluid.

Abstract: A mounting board includes an electrode pad and an insulating protective film on an insulating resin layer. In a plan view, the electrode pad includes first and second sides running parallel in a first direction. The insulating protective film includes an opening including first and second regions adjoining each other in the first direction. The first region lies over the electrode pad to expose part of the electrode pad. The second region exposes part of the insulating resin layer. The first region is defined by third and fourth sides that are between the first and second sides in a second direction perpendicular to the first direction and run parallel in the first direction. The maximum dimension of the second region in the second direction is greater than the distance between respective ends of the third and fourth sides at which the first region adjoins the second region.

Abstract: Devices and methods for encapsulating a portion of a wound dressing with biocompatible coating are disclosed. In some embodiments, a method includes coating a first side of a flexible wound contact layer of the wound dressing with a hydrophobic coating. The first side of the wound contact layer can support a plurality of electronic components. The method can further include coating a second side of the wound contact layer opposite the first side with the hydrophobic coating. The wound contact layer can be formed at least partially from hydrophilic material.

Abstract: A display device for an interior of a motor vehicle has an opaque decorative layer with a display side and a rear side. The opaque decorative layer has at least one opening which extends through the opaque decorative layer from the rear side as far as the display side and which is filled with a light-guiding filling material. At least one illumination source is arranged in the region of the rear side of the opaque decorative layer in such a way that the illumination source emits light through the opening with the light-guiding filling material from the display side of the opaque decorative layer into the interior.

Abstract: A curable epoxy composition suitable for surface application, comprising one or more epoxy resin (s); 2, 4, 6-tribromophenyl end-capped tetrabromobisphenol A epoxy-based flame retardant; and phosphorus-containing compound selected from the group consisting of one or more of: ammonium polyphosphate; resorcinol bis (diphenyl phosphate); and liquid alkylated triphenyl phosphate ester. The composition is substantially Sb2O3-free.

Abstract: A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.

Abstract: A method for packaging semiconductor dies by overmolding is disclosed. The dies are embedded in a substrate of a mold material, and cavities are produced in the mold substrate by producing 3D structures of a sacrificial material prior to the overmolding step. Afterwards, the sacrificial material is removed to thereby create cavities in the mold substrate. A conformal layer is produced on the 3D structures prior to overmolding, and the mold substrate is thinned to expose an upper surface of the 3D structures. The conformal layer is not removed when the sacrificial structures are removed. In this way, the conformal layer remains on the surfaces of the mold substrate inside the cavity. In one aspect, the conformal layer may have a protective function, useful in the production of packages including dies which come into contact with fluid substances.

Abstract: Improvements to gratings for use in waveguides and methods of producing them are described herein. Deep surface relief gratings (SRGs) may offer many advantages over conventional SRGs and Bragg gratings, an important one being a higher S-diffraction efficiency. In one embodiment, deep SRGs can be implemented as polymer surface relief gratings or evacuated Bragg gratings (EBGs). EBGs can be formed by first recording a holographic polymer dispersed liquid crystal (HPDLC) grating. Removing the liquid crystal from the cured grating provides a polymer surface relief grating. Polymer surface relief gratings have many applications including for use in waveguide-based displays.

Abstract: We disclose herein a flow sensor assembly comprising a first substrate, a flow sensor located over the first substrate, a lid located over the flow sensor, a flow inlet channel, and a flow outlet channel. A surface of the flow sensor and a surface of the lid cooperate to form a flow sensing channel between the flow inlet channel and the flow outlet channel, and a surface of the flow sensing channel is substantially flat throughout the length of the flow sensing channel.

Abstract: Embodiments relate to sensor and sensing devices, systems and methods. In an embodiment, a micro-electromechanical system (MEMS) device comprises at least one sensor element; a framing element disposed around the at least one sensor element; at least one port defined by the framing element, the at least one port configured to expose at least a portion of the at least one sensor element to an ambient environment; and a thin layer disposed in the at least one port.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor wafer, a plurality of semiconductor chips, and a plurality of first protection dams. The semiconductor wafer has a plurality of functional regions separated by a plurality of vertical streets and a plurality of horizontal streets. The semiconductor chips are mounted on the functional regions, respectively. The first protection dams are disposed on the vertical streets and the horizontal streets and spaced from the semiconductor chips. A height of the first protection dam is not less than a height of the semiconductor chip.

Abstract: The present disclosure discloses a method of packaging a chip and a chip package structure. The method of packaging the chip includes: forming a protective layer on a front surface of a chip to be packaged; mounting the chip to be packaged formed with the protective layer on the front surface on a first carrier, the back surface of the chip to be packaged facing upwards and a front surface thereof facing towards the first carrier; forming a first encapsulation layer, the first encapsulation layer being formed on the back surface of the chip to be packaged and the exposed first carrier; and detaching the first carrier to exposed the protective layer.

Abstract: Embodiments of the present disclosure generally relate to a method of cleaning a substrate. More specifically, embodiments of the present disclosure relate to a method of cleaning a substrate in a manner that reduces or eliminates the negative effects of line stiction between semiconductor device features. In an embodiment, a method of cleaning a substrate includes exposing a substrate having high aspect ratio features formed thereon to a first solvent to remove an amount of a residual cleaning solution disposed on a surface of the substrate, exposing the surface of the substrate to a second solvent to remove the first solvent disposed on the surface of the substrate, exposing the surface of the substrate to a supercritical fluid to remove the second solvent disposed on the surface of the substrate, and exposing the surface of the substrate to electromagnetic energy.

Abstract: A method of providing a sensor IC package can include applying a film to a leadframe having first and second surfaces, mounting at least one component to the film, and applying a pre-mold material to cover at least a portion of the leadframe and the passive component while leaving a first side of the leadframe exposed. The film can be removed and a die attached to the first side of the leadframe. At least one electrical connection can be formed between the die and the leadframe. The assembly of the die, the leadframe, and the pre-mold material can be encapsulated with a final mold material to provide a low profile IC package.

Abstract: An electronic circuit module includes a circuit board, electronic components, a burying layer, and a conductive film. The circuit board includes a first principal surface on which first electrodes are provided, a second principal surface on which second electrodes including grounding electrodes are provided, and a side surface connecting the first principal surface and the second principal surface. The electronic components are connected to the first electrodes. The burying layer is provided on the first principal surface of the circuit board with the electronic components buried therein. The conductive film is connected to the grounding electrodes. The outer surface of the burying layer includes markings with protruding shapes with respect to the outer surface of the burying layer. The conductive film covers the outer surface of the burying layer.

Abstract: A semiconductor sensor device includes a substrate including a first main face and a second main face opposite the first main face, a semiconductor element including a sensing region, the semiconductor element on the first main face of the substrate and being electrically coupled to the substrate, a lid on the first main face of the substrate and forming a cavity, wherein the semiconductor element is in the cavity, and a vapor deposited dielectric coating covering the semiconductor element and the first main face of the substrate, the vapor deposited dielectric coating having an opening over the sensing region, wherein the second main face of the substrate is at least partially free of the vapor deposited dielectric layer.

Abstract: A method of fabricating a package structure including at least the following steps is provided. A carrier is provided. A first package is formed on the carrier. The first package is formed by at least the following steps. A first redistribution layer is formed on the carrier, wherein the first redistribution layer has a first surface and a second surface opposite to the first surface. A semiconductor die is bonded on the first surface of the first redistribution layer. The semiconductor die is electrically connected to the first redistribution layer through a plurality of conductive wires. An insulating material is formed to encapsulate the semiconductor die and the plurality of conductive wires.

Abstract: Representative implementations provide techniques for processing integrated circuit (IC) dies and related devices, in preparation for stacking and bonding the devices. The disclosed techniques provide removal of processing residue from the device surfaces while protecting the underlying layers. One or more sacrificial layers may be applied to a surface of the device during processing to protect the underlying layers. Processing residue is attached to the sacrificial layers instead of the device, and can be removed with the sacrificial layers.

Abstract: A thin film transistor (TFT) array substrate includes: a substrate; a display region formed on the substrate; a flexible printed circuit disposed on the substrate and located at one side of the display region; a control chip disposed between the display region and the flexible printed circuit, and two sides of the flexible printed circuit going beyond two corresponding sides of the control chip, respectively; a first reinforcement member disposed at a first side of the control chip, and the first side being adjacent to one side of the control chip that faces the display region; a second reinforcement member disposed at a second side of the control chip opposite to the first side; and a third reinforcement member covering the control chip, the first reinforcement member and the second reinforcement member.

Abstract: A method produces or machines a roller which is suitable to be used in a machine for producing or processing a fibrous web. The roller contains a roller core and at least one functional layer. The method is characterized in that the method includes the application of a functional layer. The application of the functional layer is performed by applying a coating substrate to the surface of a roller core. The application takes place simultaneously over at least half the roller width, preferably over 75% of the roller width, particularly preferably over the entire roller width. The entire applied coating substrate or parts thereof are hardened, forming a solidified structure.

Abstract: A system is disclosed for use in additively manufacturing a composite structure. The system may include a head having a nozzle configured to discharge a composite material including a matrix and a reinforcement, and a cure enhancer configured to direct energy to the composite material to enhance curing of the matrix. The system may also include an optic adjustably positioned between the cure enhancer and the nozzle of the head.

Abstract: Provided herein are products and methods for making structures having a body defined by a carbon nanotube (CNT) pulp network having a long-range connectivity exceeding a percolation threshold of the structure to permit electron transport throughout the structure, an active material dispersed within the body, and a binder material binding the active material to the CNT pulp network within the body.

Abstract: A system and method for connecting semiconductor dies is provided. An embodiment comprises connecting a first semiconductor die with a first width to a second semiconductor die with a larger second width and that is still connected to a semiconductor wafer. The first semiconductor die is encapsulated after it is connected, and the encapsulant and first semiconductor die are thinned to expose a through substrate via within the first semiconductor die. The second semiconductor die is singulated from the semiconductor wafer, and the combined first semiconductor die and second semiconductor die are then connected to another substrate.

Abstract: A method for fabricating a semiconductor chip is disclosed. In an embodiment, the method includes providing a plurality of semiconductor chips, wherein each semiconductor chip comprises a first main face, a second main face opposite to the first main face and side faces connecting the first and second main faces, placing the semiconductor chips on a carrier with the second main faces facing the carrier and applying an encapsulation material by transfer molding thereby forming the semiconductor chip panel, wherein the encapsulation material is applied so that the side faces of the semiconductor chips are covered with the encapsulation material while the first main faces are not.

Abstract: A method for producing a printed circuit board (10) having at least one embedded sensor chip (3), in which at least one sensor face (5) and terminals (4) are arranged on a face of the chip, said method comprising the following steps: a) providing an adhesive film (1), b) printing a conductor structure (2) formed from a conductive paste onto a surface of the adhesive film, c) placing the at least one sensor chip (3) with the face comprising the at least one sensor face (5) and the terminals (4) onto the conductor structure (2) formed from a conductive paste, in an indexed manner, d) curing the conductive paste, e) applying an insulation layer (6) having a conductor layer (7) arranged thereabove to the surface of the structure, created in the previous steps, comprising the chip (3), f) laminating the structure created in the previous steps, g) structuring the conductor layer (7) and forming vias (9) from the conductor layer to conductive tracks (7b, 7c) of the conductor structure on the surface of the adhesi

Abstract: Techniques for constructing a multi-chip module semiconductor device are provided herein. The techniques include placing electronic modules on a first surface and a second surface, with electrical connections for the electronic modules being proximate to respectively mounted surfaces, disposing a mold material on one of the mounting surfaces to substantially surround corresponding electronic modules, orienting the mounting surface without the mold material disposed thereon, relative to the mounting surface with the mold material disposed thereon to cause the mold material to substantially surround each electronic module while maintaining a minimum distance between the electronic modules mounted on each mounting surface. The techniques further include removing the mounting surfaces from the mold compound to yield a multi-chip semiconductor device.

Abstract: A semiconductor package including a package base substrate; at least one semiconductor chip on the package base substrate; a heat sink attached on the at least one semiconductor chip, the heat sink including a base and a plurality of protrusion patterns on a top of the base; and a molding covering a top of the package base substrate, a side surface of the at least one semiconductor chip, and a side surface of the heat sink without covering a top of the heat sink.

Abstract: An electronics module assembly is described herein that packages dies using a universal cavity wafer that is independent of electronics module design. In one embodiment, the electronics module assembly can include a cavity wafer having a single frontside cavity that extends over a majority of a frontside surface area of the cavity wafer and a plurality of fillports. The assembly can also include at least one group of dies placed in the frontside cavity and encapsulant that secures the position of the at least one group of dies relative to the cavity wafer. Further, a layer of the encapsulant can cover a backside of the cavity wafer.

Abstract: A method for forming a substrate structure for an electrical component includes placing an electrically insulating laminate on a substrate and applying hot pressure to the electrically insulating laminate by a heatable plate. An average temperature of a surface temperature distribution within a center area of the heatable plate is higher than 80° C. during applying the hot pressure. Further, an edge area of the heatable plate laterally surrounds the center area and a temperature of the heatable plate within the edge area decreases from the center area towards an edge of the heatable plate during applying the hot pressure. A temperature at a location located vertically above an edge of the substrate during applying the hot pressure is at least 5° C. lower than the average temperature of the surface temperature distribution within the center area.

Abstract: A LED device is disclosed. The device has a LED area, a boundary element surrounding the LED area, a plurality of chip scale package LEDs in the LED area, a plurality of flip chip LEDs in the LED area, an encapsulate, a first conductive path, and a second conductive. The encapsulate covers the plurality of chip scale package LEDs and the plurality of flip chip LEDs in the LED area. The encapsulate has phosphor. The first conductive path connects the plurality of chip scale package LEDs. The second conductive path connects the plurality of flip chip LEDs. The plurality of chip scale package LEDs and the plurality of flip chip LEDs in the LED area are arranged in rows. Each row comprises alternating chip scale package LEDs and flip chip LEDs.

Abstract: Electronic modules having complex contact structures may be formed by encapsulating panels containing pluralities of electronic modules delineated by cut lines and having conductive interconnects buried within the panel along the cut lines. Holes defining contact regions along the electronic module sidewall may be cut into the panel along the cut lines to expose the buried interconnects. The panel may be metallized, e.g. by a series or processes including plating, on selected surfaces including in the holes to form the contacts and other metal structures followed by cutting the panel along the cut lines to singulate the individual electronic models. The contacts may be located in a conductive grove providing a castellated module.

Abstract: In an example, a process for reversibly bonding a conformal coating to a dry film solder mask (DFSM) material is disclosed. The process includes applying a first conformal coating material to a DFSM material. The first conformal coating material includes a first functional group, and the DFSM material includes a second functional group that is different from the first functional group. The process also includes reversibly bonding the first conformal coating material to the DFSM material via a chemical reaction of the first functional group and the second functional group.

Abstract: Ground shielding is achieved by a conductor shield having conductive surfaces that immediately surround individual chips within a multichip module or device, such as a multichip module or device with flip-chip (FC) bumps. Intra-module shielding between individual chips within the multichip module or device is achieved by electromagnetic or radio-signal (RF) isolation provided by the surfaces of the conductor shield immediately surrounding each of the chips. The conductor shield is directly connected to one or more grounded conductor portions of a substrate or interposer to ensure reliable grounding.

Abstract: A semiconductor package includes a semiconductor die having a first main side and a second main side opposite the first main side, the first main side having an inner region surrounded by a periphery region. The semiconductor package further includes a film covering the semiconductor die and adhered to the periphery region of the first main side of the semiconductor die. The film has a curved surface so that the inner region of the first main side of the semiconductor die is spaced apart from the film by an air gap. Electrical conductors are attached at a first end to pads at the periphery region of the first main side of the semiconductor die. A corresponding method of manufacture is also provided.

Abstract: During a process to encapsulate electronic components and attachment interfaces thereof on a first side of a substrate of a hybrid assembly, a fluid is supplied to a trench of an encapsulation system in which the hybrid assembly is loaded, and a balancing pressure is delivered by the fluid within the trench, during the encapsulation process, to support the hybrid assembly from an opposing second side of the substrate. A regulator of a fluid supply of the system may maintain the balancing pressure, for example, being controlled by a controller of the system that is configured to estimate a pressure within a molding cavity of the system.

Abstract: A semiconductor package includes upper and lower semiconductor chip packages, and a redistribution wiring layer pattern interposed between the packages. The lower package includes a molding layer in which at least one chip is embedded, and has a top surface and an inclined sidewall surface along which the redistribution wiring layer pattern is formed. The upper and lower packages are electrically connected to through the redistribution wiring layer pattern. A first package may be formed by a wafer level packaging technique and may include a redistribution wiring layer as a substrate, a semiconductor chip disposed on the redistribution wiring layer, and a molding layer on which the lower package, redistribution wiring layer pattern and upper package are disposed.

Abstract: A method for remapping an extracted die is provided. The method includes one or more of removing an extracted die from a previous integrated circuit package, the extracted die including a plurality of original bond pads having locations that do not correspond to desired pin assignments of a new package base and bonding an interposer to the extracted die. The interposer includes first bond pads configured to receive new bond wires from the plurality of original bond pads and second bond pads corresponding to desired pin assignments of the new package base, each individually electrically coupled to one of the first bond pads and configured to receive new bond wires from package leads or downbonds of the new package base.

Abstract: Provided is a manufacturing process for electronic circuit components such as bare dies, and packaged integrated chips, among other configurations, to form electronic assemblies. The surface of the electronic circuit component carries electronic elements such as conductive traces and/or other configurations including contact pads. A method for forming an electronic assembly includes providing a tacky layer. Then an electronic circuit component is provided having a first side and a second side, where the first side carries the electronic elements. The first side of the electronic circuit component is positioned into contact with the tacky layer. A bonding material is then deposited to a portion of the adhesive layer that is not covered by the first side of the electronic circuit component, to a depth which is sufficient to cover at least a portion of the electronic circuit component. The bonding material is then fixed or cured into a fixed or cured bonding material, and the tacky layer is removed.

Abstract: Some implementations provide a semiconductor device that includes a substrate, several metal and dielectric layers coupled to the substrate, and a pad coupled to one of the several metal layers. The semiconductor device also includes a first metal layer coupled to the pad and an under bump metallization layer coupled to the first metal redistribution layer. The semiconductor device further includes a mold layer covering a first surface of the semiconductor device and at least a side portion of the semiconductor device. In some implementations, the mold layer is an epoxy layer. In some implementations, the first surface of the semiconductor device is the top side of the semiconductor device. In some implementations, the mold layer covers the at least side portion of the semiconductor device such that a side portion of at least one of the several metal layers and dielectric layers is covered with the mold layer.

Abstract: A semiconductor package formed utilizing a removable backside protective layer includes a leadframe, a die pad, leads and a molding compound around them. The first surface of the die pad and leads are exposed to an external environment by the plurality of recesses. The recesses are formed by coupling a removable backside protective layer to the leadframe before applying the molding compound. After the molding compound is applied and cured, the backside protective layer is removed to expose the first surface of the die pad and the first surfaces of the leads so the semiconductor package may be mounted within an electronic device. The removable backside protective layer protects the die pad and the leads from mold flashing and residue when forming the semiconductor package during the fabrication process.

Abstract: A packaged includes a flip-chip assembly. The flip-chip assembly includes a first semiconductor substrate having at least one integrated semiconductor device, and a second substrate connected to the first substrate. A main surface of the first semiconductor substrate faces and is spaced apart from the second substrate. The packaged semiconductor device further includes a parylene coating covering outer surfaces of the first semiconductor substrate and the second substrate. A first section of the main surface is exposed from the parylene coating.

Abstract: A semiconductor device includes a semiconductor chip having a first main surface, a second main surface opposite to the first main surface, and a side wall surface. An electrical contact area is exposed at the side wall surface of the semiconductor chip. An electrically conducting layer covers at least partially the second main surface and the electrical contact area.

Abstract: A package includes a device die, a molding material molding the device die therein, and a plurality of redistribution lines overlying the device die and the molding material. A laser mark pad is coplanar with one of the plurality of redistribution lines, wherein the laser mark pad and the one of the plurality of redistribution layers are formed of the same conductive material. A polymer layer is over the laser mark pad and the plurality of redistribution lines. A tape is attached over the polymer layer. A laser mark penetrates through the tape and the polymer layer. The laser mark extends to a top surface of the laser mark pad.

Abstract: A coating for protecting a wafer from moisture and debris due to dicing, singulating, or handling the wafer is provided. A semiconductor sensor device comprises a wafer having a surface and at least one trench feature and the protective coating covering the trench feature. The trench feature comprises a plurality of walls and the walls are covered with the protective coating, wherein the walls of the trench feature are formed as a portion of the semiconductor sensor device. The semiconductor sensor device further comprises a patterned mask formed on the wafer before the trench feature is formed, wherein the protective coating is formed directly to the trench feature and the patterned mask.

Abstract: A method is for making a semiconductor device. The method may include providing a lead frame having a recess, forming a sacrificial material in the recess of the lead frame, and mounting an IC on the lead frame. The method may include encapsulating the IC and the lead frame, removing portions of the lead frame to define lead frame contacts for the IC, and removing the sacrificial material to define for each lead frame contact a solder anchoring tab extending outwardly at a lower region and defining a sidewall recess between opposing portions of the solder anchoring tab and the encapsulation material.