Encapsulation, E.g., Encapsulation Layer, Coating (epo) Patents (Class 257/E21.502)
  • Patent number: 10756065
    Abstract: A method of fabricating a package structure including at least the following steps is provided. A carrier is provided. A first package is formed on the carrier. The first package is formed by at least the following steps. A first redistribution layer is formed on the carrier, wherein the first redistribution layer has a first surface and a second surface opposite to the first surface. A semiconductor die is bonded on the first surface of the first redistribution layer. The semiconductor die is electrically connected to the first redistribution layer through a plurality of conductive wires. An insulating material is formed to encapsulate the semiconductor die and the plurality of conductive wires.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: August 25, 2020
    Assignee: Powertech Technology Inc.
    Inventors: Shang-Yu Chang Chien, Hung-Hsin Hsu, Nan-Chun Lin
  • Patent number: 10707087
    Abstract: Representative implementations provide techniques for processing integrated circuit (IC) dies and related devices, in preparation for stacking and bonding the devices. The disclosed techniques provide removal of processing residue from the device surfaces while protecting the underlying layers. One or more sacrificial layers may be applied to a surface of the device during processing to protect the underlying layers. Processing residue is attached to the sacrificial layers instead of the device, and can be removed with the sacrificial layers.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: July 7, 2020
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Cyprian Emeka Uzoh, Guilian Gao
  • Patent number: 10663782
    Abstract: A thin film transistor (TFT) array substrate includes: a substrate; a display region formed on the substrate; a flexible printed circuit disposed on the substrate and located at one side of the display region; a control chip disposed between the display region and the flexible printed circuit, and two sides of the flexible printed circuit going beyond two corresponding sides of the control chip, respectively; a first reinforcement member disposed at a first side of the control chip, and the first side being adjacent to one side of the control chip that faces the display region; a second reinforcement member disposed at a second side of the control chip opposite to the first side; and a third reinforcement member covering the control chip, the first reinforcement member and the second reinforcement member.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: May 26, 2020
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd
    Inventors: Xin Qiu, Yao-li Huang
  • Patent number: 10655276
    Abstract: A method produces or machines a roller which is suitable to be used in a machine for producing or processing a fibrous web. The roller contains a roller core and at least one functional layer. The method is characterized in that the method includes the application of a functional layer. The application of the functional layer is performed by applying a coating substrate to the surface of a roller core. The application takes place simultaneously over at least half the roller width, preferably over 75% of the roller width, particularly preferably over the entire roller width. The entire applied coating substrate or parts thereof are hardened, forming a solidified structure.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: May 19, 2020
    Assignee: Voith Patent GmbH
    Inventors: Wesley Brooks, Robert Eberhardt, Siegfried Graser, Franz Grohmann, Ting Liu, Ralf Moser, Stefan Probst-Schendzielorz, Matthias Schmitt, Michael Wokurek
  • Patent number: 10625467
    Abstract: A system is disclosed for use in additively manufacturing a composite structure. The system may include a head having a nozzle configured to discharge a composite material including a matrix and a reinforcement, and a cure enhancer configured to direct energy to the composite material to enhance curing of the matrix. The system may also include an optic adjustably positioned between the cure enhancer and the nozzle of the head.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: April 21, 2020
    Assignee: Continuous Composites Inc.
    Inventor: Kenneth Lyle Tyler
  • Patent number: 10581082
    Abstract: Provided herein are products and methods for making structures having a body defined by a carbon nanotube (CNT) pulp network having a long-range connectivity exceeding a percolation threshold of the structure to permit electron transport throughout the structure, an active material dispersed within the body, and a binder material binding the active material to the CNT pulp network within the body.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: March 3, 2020
    Assignee: Nanocomp Technologies, Inc.
    Inventors: Mark W. Schauer, Eitan Zeira, David Gailus, Brian White
  • Patent number: 10510701
    Abstract: A system and method for connecting semiconductor dies is provided. An embodiment comprises connecting a first semiconductor die with a first width to a second semiconductor die with a larger second width and that is still connected to a semiconductor wafer. The first semiconductor die is encapsulated after it is connected, and the encapsulant and first semiconductor die are thinned to expose a through substrate via within the first semiconductor die. The second semiconductor die is singulated from the semiconductor wafer, and the combined first semiconductor die and second semiconductor die are then connected to another substrate.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Chen-Hua Yu, Sen-Bor Jan
  • Patent number: 10483133
    Abstract: A method for fabricating a semiconductor chip is disclosed. In an embodiment, the method includes providing a plurality of semiconductor chips, wherein each semiconductor chip comprises a first main face, a second main face opposite to the first main face and side faces connecting the first and second main faces, placing the semiconductor chips on a carrier with the second main faces facing the carrier and applying an encapsulation material by transfer molding thereby forming the semiconductor chip panel, wherein the encapsulation material is applied so that the side faces of the semiconductor chips are covered with the encapsulation material while the first main faces are not.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: November 19, 2019
    Assignee: Infineon Technologies AG
    Inventors: Daniel Porwol, Edward Fuergut
  • Patent number: 10453706
    Abstract: Techniques for constructing a multi-chip module semiconductor device are provided herein. The techniques include placing electronic modules on a first surface and a second surface, with electrical connections for the electronic modules being proximate to respectively mounted surfaces, disposing a mold material on one of the mounting surfaces to substantially surround corresponding electronic modules, orienting the mounting surface without the mold material disposed thereon, relative to the mounting surface with the mold material disposed thereon to cause the mold material to substantially surround each electronic module while maintaining a minimum distance between the electronic modules mounted on each mounting surface. The techniques further include removing the mounting surfaces from the mold compound to yield a multi-chip semiconductor device.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: October 22, 2019
    Assignee: THE CHARLES STARK DRAPER LABORATORY, INC.
    Inventors: Keith N. Kunard, Justin C. Borski
  • Patent number: 10455703
    Abstract: A method for producing a printed circuit board (10) having at least one embedded sensor chip (3), in which at least one sensor face (5) and terminals (4) are arranged on a face of the chip, said method comprising the following steps: a) providing an adhesive film (1), b) printing a conductor structure (2) formed from a conductive paste onto a surface of the adhesive film, c) placing the at least one sensor chip (3) with the face comprising the at least one sensor face (5) and the terminals (4) onto the conductor structure (2) formed from a conductive paste, in an indexed manner, d) curing the conductive paste, e) applying an insulation layer (6) having a conductor layer (7) arranged thereabove to the surface of the structure, created in the previous steps, comprising the chip (3), f) laminating the structure created in the previous steps, g) structuring the conductor layer (7) and forming vias (9) from the conductor layer to conductive tracks (7b, 7c) of the conductor structure on the surface of the adhesi
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: October 22, 2019
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventor: Gerald Weidinger
  • Patent number: 10453822
    Abstract: A semiconductor package including a package base substrate; at least one semiconductor chip on the package base substrate; a heat sink attached on the at least one semiconductor chip, the heat sink including a base and a plurality of protrusion patterns on a top of the base; and a molding covering a top of the package base substrate, a side surface of the at least one semiconductor chip, and a side surface of the heat sink without covering a top of the heat sink.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: October 22, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-sung Kim, Cheol-woo Lee
  • Patent number: 10418249
    Abstract: An electronics module assembly is described herein that packages dies using a universal cavity wafer that is independent of electronics module design. In one embodiment, the electronics module assembly can include a cavity wafer having a single frontside cavity that extends over a majority of a frontside surface area of the cavity wafer and a plurality of fillports. The assembly can also include at least one group of dies placed in the frontside cavity and encapsulant that secures the position of the at least one group of dies relative to the cavity wafer. Further, a layer of the encapsulant can cover a backside of the cavity wafer.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: September 17, 2019
    Assignee: The Charles Stark Draper Laboratory, Inc.
    Inventors: Maurice Karpman, Michael Rickley, Andrew Mueller, Nicole Mueller, Jeffrey Thompson, Charles Baab
  • Patent number: 10384431
    Abstract: A method for forming a substrate structure for an electrical component includes placing an electrically insulating laminate on a substrate and applying hot pressure to the electrically insulating laminate by a heatable plate. An average temperature of a surface temperature distribution within a center area of the heatable plate is higher than 80° C. during applying the hot pressure. Further, an edge area of the heatable plate laterally surrounds the center area and a temperature of the heatable plate within the edge area decreases from the center area towards an edge of the heatable plate during applying the hot pressure. A temperature at a location located vertically above an edge of the substrate during applying the hot pressure is at least 5° C. lower than the average temperature of the surface temperature distribution within the center area.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: August 20, 2019
    Assignee: Intel Corporation
    Inventors: Ji Yong Park, Sri Chaitra J. Chavali, Siddharth K. Alur, Kyu Oh Lee
  • Patent number: 10297584
    Abstract: A LED device is disclosed. The device has a LED area, a boundary element surrounding the LED area, a plurality of chip scale package LEDs in the LED area, a plurality of flip chip LEDs in the LED area, an encapsulate, a first conductive path, and a second conductive. The encapsulate covers the plurality of chip scale package LEDs and the plurality of flip chip LEDs in the LED area. The encapsulate has phosphor. The first conductive path connects the plurality of chip scale package LEDs. The second conductive path connects the plurality of flip chip LEDs. The plurality of chip scale package LEDs and the plurality of flip chip LEDs in the LED area are arranged in rows. Each row comprises alternating chip scale package LEDs and flip chip LEDs.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: May 21, 2019
    Assignee: Light To Form, LLC
    Inventors: Shoubert Makanoeich, Nelson Caldani, Eric Bretschneider
  • Patent number: 10264664
    Abstract: Electronic modules having complex contact structures may be formed by encapsulating panels containing pluralities of electronic modules delineated by cut lines and having conductive interconnects buried within the panel along the cut lines. Holes defining contact regions along the electronic module sidewall may be cut into the panel along the cut lines to expose the buried interconnects. The panel may be metallized, e.g. by a series or processes including plating, on selected surfaces including in the holes to form the contacts and other metal structures followed by cutting the panel along the cut lines to singulate the individual electronic models. The contacts may be located in a conductive grove providing a castellated module.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: April 16, 2019
    Assignee: VLT, Inc.
    Inventors: Patrizio Vinciarelli, Patrick R. Lavery, Rudolph F. Mutter, Jeffery J. Kirk, Andrew T. D'Amico
  • Patent number: 10257940
    Abstract: In an example, a process for reversibly bonding a conformal coating to a dry film solder mask (DFSM) material is disclosed. The process includes applying a first conformal coating material to a DFSM material. The first conformal coating material includes a first functional group, and the DFSM material includes a second functional group that is different from the first functional group. The process also includes reversibly bonding the first conformal coating material to the DFSM material via a chemical reaction of the first functional group and the second functional group.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sarah K. Czaplewski, Joseph Kuczynski, Jason T. Wertz, Jing Zhang
  • Patent number: 10242957
    Abstract: Ground shielding is achieved by a conductor shield having conductive surfaces that immediately surround individual chips within a multichip module or device, such as a multichip module or device with flip-chip (FC) bumps. Intra-module shielding between individual chips within the multichip module or device is achieved by electromagnetic or radio-signal (RF) isolation provided by the surfaces of the conductor shield immediately surrounding each of the chips. The conductor shield is directly connected to one or more grounded conductor portions of a substrate or interposer to ensure reliable grounding.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: March 26, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Daeik Daniel Kim, Changhan Hobie Yun, Mario Francisco Velez, David Francis Berdy, Chengjie Zuo, Jonghae Kim, Matthew Michael Nowak
  • Patent number: 10224260
    Abstract: A semiconductor package includes a semiconductor die having a first main side and a second main side opposite the first main side, the first main side having an inner region surrounded by a periphery region. The semiconductor package further includes a film covering the semiconductor die and adhered to the periphery region of the first main side of the semiconductor die. The film has a curved surface so that the inner region of the first main side of the semiconductor die is spaced apart from the film by an air gap. Electrical conductors are attached at a first end to pads at the periphery region of the first main side of the semiconductor die. A corresponding method of manufacture is also provided.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: March 5, 2019
    Assignee: Infineon Technologies AG
    Inventor: Chee Yang Ng
  • Patent number: 10201094
    Abstract: During a process to encapsulate electronic components and attachment interfaces thereof on a first side of a substrate of a hybrid assembly, a fluid is supplied to a trench of an encapsulation system in which the hybrid assembly is loaded, and a balancing pressure is delivered by the fluid within the trench, during the encapsulation process, to support the hybrid assembly from an opposing second side of the substrate. A regulator of a fluid supply of the system may maintain the balancing pressure, for example, being controlled by a controller of the system that is configured to estimate a pressure within a molding cavity of the system.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: February 5, 2019
    Assignee: Medtronic, Inc.
    Inventors: Chunho Kim, Songhua Shi, Mark S. Ricotta, Scott B. Sleeper, Yongqian Wang
  • Patent number: 10186500
    Abstract: A semiconductor package includes upper and lower semiconductor chip packages, and a redistribution wiring layer pattern interposed between the packages. The lower package includes a molding layer in which at least one chip is embedded, and has a top surface and an inclined sidewall surface along which the redistribution wiring layer pattern is formed. The upper and lower packages are electrically connected to through the redistribution wiring layer pattern. A first package may be formed by a wafer level packaging technique and may include a redistribution wiring layer as a substrate, a semiconductor chip disposed on the redistribution wiring layer, and a molding layer on which the lower package, redistribution wiring layer pattern and upper package are disposed.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: January 22, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Kwan Ryu, Yonghwan Kwon, Yun Seok Choi, Chajea Jo, Taeje Cho
  • Patent number: 10177054
    Abstract: A method for remapping an extracted die is provided. The method includes one or more of removing an extracted die from a previous integrated circuit package, the extracted die including a plurality of original bond pads having locations that do not correspond to desired pin assignments of a new package base and bonding an interposer to the extracted die. The interposer includes first bond pads configured to receive new bond wires from the plurality of original bond pads and second bond pads corresponding to desired pin assignments of the new package base, each individually electrically coupled to one of the first bond pads and configured to receive new bond wires from package leads or downbonds of the new package base.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: January 8, 2019
    Assignee: Global Circuit Innovations, Inc.
    Inventor: Erick Merle Spory
  • Patent number: 10165677
    Abstract: Provided is a manufacturing process for electronic circuit components such as bare dies, and packaged integrated chips, among other configurations, to form electronic assemblies. The surface of the electronic circuit component carries electronic elements such as conductive traces and/or other configurations including contact pads. A method for forming an electronic assembly includes providing a tacky layer. Then an electronic circuit component is provided having a first side and a second side, where the first side carries the electronic elements. The first side of the electronic circuit component is positioned into contact with the tacky layer. A bonding material is then deposited to a portion of the adhesive layer that is not covered by the first side of the electronic circuit component, to a depth which is sufficient to cover at least a portion of the electronic circuit component. The bonding material is then fixed or cured into a fixed or cured bonding material, and the tacky layer is removed.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: December 25, 2018
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Ping Mei, Tse Nga Ng, Brent S. Krusor, Gregory L. Whiting, Steven E. Ready, Janos Veres
  • Patent number: 10141202
    Abstract: Some implementations provide a semiconductor device that includes a substrate, several metal and dielectric layers coupled to the substrate, and a pad coupled to one of the several metal layers. The semiconductor device also includes a first metal layer coupled to the pad and an under bump metallization layer coupled to the first metal redistribution layer. The semiconductor device further includes a mold layer covering a first surface of the semiconductor device and at least a side portion of the semiconductor device. In some implementations, the mold layer is an epoxy layer. In some implementations, the first surface of the semiconductor device is the top side of the semiconductor device. In some implementations, the mold layer covers the at least side portion of the semiconductor device such that a side portion of at least one of the several metal layers and dielectric layers is covered with the mold layer.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: November 27, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Reynante Tamunan Alvarado, Lizabeth Ann Keser, Jianwen Xu
  • Patent number: 10128169
    Abstract: A semiconductor package formed utilizing a removable backside protective layer includes a leadframe, a die pad, leads and a molding compound around them. The first surface of the die pad and leads are exposed to an external environment by the plurality of recesses. The recesses are formed by coupling a removable backside protective layer to the leadframe before applying the molding compound. After the molding compound is applied and cured, the backside protective layer is removed to expose the first surface of the die pad and the first surfaces of the leads so the semiconductor package may be mounted within an electronic device. The removable backside protective layer protects the die pad and the leads from mold flashing and residue when forming the semiconductor package during the fabrication process.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: November 13, 2018
    Assignee: STMicroelectronics, Inc.
    Inventors: Aaron Cadag, Ian Harvey Arellano, Ela Mia Cadag
  • Patent number: 10118816
    Abstract: A packaged includes a flip-chip assembly. The flip-chip assembly includes a first semiconductor substrate having at least one integrated semiconductor device, and a second substrate connected to the first substrate. A main surface of the first semiconductor substrate faces and is spaced apart from the second substrate. The packaged semiconductor device further includes a parylene coating covering outer surfaces of the first semiconductor substrate and the second substrate. A first section of the main surface is exposed from the parylene coating.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: November 6, 2018
    Assignee: Infineon Technologies AG
    Inventors: Klaus Elian, Horst Theuss
  • Patent number: 10109592
    Abstract: A semiconductor device includes a semiconductor chip having a first main surface, a second main surface opposite to the first main surface, and a side wall surface. An electrical contact area is exposed at the side wall surface of the semiconductor chip. An electrically conducting layer covers at least partially the second main surface and the electrical contact area.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: October 23, 2018
    Assignee: Infineon Technologies AG
    Inventor: Chee Yang Ng
  • Patent number: 10096553
    Abstract: A package includes a device die, a molding material molding the device die therein, and a plurality of redistribution lines overlying the device die and the molding material. A laser mark pad is coplanar with one of the plurality of redistribution lines, wherein the laser mark pad and the one of the plurality of redistribution layers are formed of the same conductive material. A polymer layer is over the laser mark pad and the plurality of redistribution lines. A tape is attached over the polymer layer. A laser mark penetrates through the tape and the polymer layer. The laser mark extends to a top surface of the laser mark pad.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: October 9, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: An-Jhih Su, Hsien-Wei Chen
  • Patent number: 10017377
    Abstract: A coating for protecting a wafer from moisture and debris due to dicing, singulating, or handling the wafer is provided. A semiconductor sensor device comprises a wafer having a surface and at least one trench feature and the protective coating covering the trench feature. The trench feature comprises a plurality of walls and the walls are covered with the protective coating, wherein the walls of the trench feature are formed as a portion of the semiconductor sensor device. The semiconductor sensor device further comprises a patterned mask formed on the wafer before the trench feature is formed, wherein the protective coating is formed directly to the trench feature and the patterned mask.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: July 10, 2018
    Assignee: Robert Bosch GmbH
    Inventor: Mikko VA Suvanto
  • Patent number: 10008472
    Abstract: A method is for making a semiconductor device. The method may include providing a lead frame having a recess, forming a sacrificial material in the recess of the lead frame, and mounting an IC on the lead frame. The method may include encapsulating the IC and the lead frame, removing portions of the lead frame to define lead frame contacts for the IC, and removing the sacrificial material to define for each lead frame contact a solder anchoring tab extending outwardly at a lower region and defining a sidewall recess between opposing portions of the solder anchoring tab and the encapsulation material.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: June 26, 2018
    Assignee: STMICROELECTRONICS, INC.
    Inventor: Jefferson Talledo
  • Patent number: 10002846
    Abstract: A method is provided. The method includes removing an extracted die including an original ball bond from a previous packaged integrated circuit, bonding the extracted die to an interposer to create a remapped extracted die, 3D printing one or more first bond connections between one or more original bond pads of the extracted die and one or more first bond pads of the interposer, securing the remapped extracted die to a package base, and 3D printing one or more second bond connections between one or more second bond pads of the interposer and one or more package leads or downbonds of the package base. The one or more first and second bond connections conform to the shapes and surfaces of the extracted die, the interposer, and the package base.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: June 19, 2018
    Assignee: Global Circuit Innovations Incorporated
    Inventor: Erick Merle Spory
  • Patent number: 9978733
    Abstract: An optoelectronic semiconductor component includes an optoelectronic semiconductor chip with a first surface and a second surface. The component also includes a protective chip which has a protective diode, a first surface and a second surface. The semiconductor chip and the protective chip are embedded in a molded body. A first electrical contact and a second electrical contact are arranged on the first surface of the semiconductor chip. A third electrical contact and a fourth electrical contact are arranged on the first surface of the protective chip. The first electrical contact is electrically connected to the third electrical contact. In addition, the second electrical contact is electrically connected to the fourth electrical contact.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: May 22, 2018
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Stefan Illek, Matthias Sabathil
  • Patent number: 9966498
    Abstract: A method for manufacturing a light-emitting element, including steps of: providing a wafer-level element including a wafer and a light-emitting stack on the wafer, wherein the wafer including an upper surface and a bottom surface, and light-emitting stack is formed on the upper surface of the wafer; forming a light-emitting stack on the upper surface of the wafer; cutting the wafer from one of the bottom surface or the top surface of the wafer by a water-jet laser having a first beam size; cutting the wafer from the other one of the bottom surface or the upper surface of the wafer by the water-jet laser having a second beam size; and dividing the wafer-level element wafer and the light-emitting stack into a plurality of light-emitting dies.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: May 8, 2018
    Assignee: EPISTAR CORPORATION
    Inventors: Min-Yen Tsai, De-Shan Kuo
  • Patent number: 9961769
    Abstract: The present disclosure relates to microelectronic substrates, such as interposers, motherboards, test platforms, and the like, that are fabricated to have overlapping connection zones, such that different microelectronic devices, such as microprocessors, chipsets, graphics processing devices, wireless devices, memory devices, application specific integrated circuits, and the like, may be alternately attached to the microelectronic substrates to form functional microelectronic packages.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: May 1, 2018
    Assignee: INTEL CORPORATION
    Inventors: Md Altaf Hossain, Cliff C. Lee, David W. Browning, Itai M. Pines, Brian P. Kelly
  • Patent number: 9953846
    Abstract: A method for fabricating a semiconductor chip is disclosed. In an embodiment, the method includes providing a carrier, providing a plurality of semiconductor chips, the semiconductor chips each including a first main face and a second main face opposite to the first main face and side faces connecting the first and second main faces, placing the semiconductor chips on the carrier with the second main faces facing the carrier, and applying an encapsulation material to the side faces of the semiconductor chips.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: April 24, 2018
    Assignee: Infineon Technologies AG
    Inventors: Daniel Porwol, Edward Fuergut
  • Patent number: 9952111
    Abstract: According to an embodiment, a device includes a substrate, a transducer die disposed over the substrate, a cover disposed over the transducer die, and a support structure connecting the cover to the substrate. The support structure includes a port configured to allow transfer of fluidic signals between an ambient environment and the transducer die.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: April 24, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Andreas Froemel
  • Patent number: 9911375
    Abstract: A display device includes a first substrate that is non-rectangular and includes a display area having a plurality of pixels and a non-display area located around the display area, a second substrate that faces the first substrate and overlaps part of the first substrate, an integrated circuit that provides a driving signal to the pixels, and a first pad to which a flexible printed circuit board that delivers an external signal is coupled and which is electrically connected to the integrated circuit. The non-display area of the first substrate includes a first area that extends in a first direction and is exposed from the second substrate and a second area that extends in a second direction different from the first direction and is exposed from the second substrate. The integrated circuit is located in the first area. The first pad is located in the second area.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: March 6, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventor: Youn Bum Lee
  • Patent number: 9901880
    Abstract: Provided is a composition for use in fabricating a carbon molecular sieve membrane, including a fluorine-containing polymer matrix and polysilsesquioxane. The composition shows high selectivity to the gas to be separated and high separation quality by controlling the mixing ratio of the fluorine-containing polymer matrix with polysilsesquioxane as well as the type of fluorine-containing polymer matrix and polysilsesquioxane. Ancillary selective pore formation is enhanced by a so-called “autogenous fluorinated gas induced siloxane etching” (A-FISE) mechanism of fluorine-containing polymer/polysilsesquioxane blend precursors during carbonization. Therefore, it is possible to effectively separate gases having a small difference in particle size, which, otherwise, are difficult to be separated with the conventional polymer membranes.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: February 27, 2018
    Assignee: Korea Institute of Science and Technology
    Inventors: Jong Suk Lee, Seung Sang Hwang, Sunghwan Park, Albert Sung Soo Lee
  • Patent number: 9890036
    Abstract: In described examples, a hermetic package of a microelectromechanical system (MEMS) structure includes a substrate having a surface with a MEMS structure of a first height. The substrate is hermetically sealed to a cap forming a cavity over the MEMS structure. The cap is attached to the substrate surface by a vertical stack of metal layers adhering to the substrate surface and to the cap. The stack has a continuous outline surrounding the MEMS structure while spaced from the MEMS structure by a distance. The stack has: a first bottom metal seed film adhering to the substrate and a second bottom metal seed film adhering to the first bottom metal seed film; and a first top metal seed film adhering to the cap and a second top metal seed film adhering to the first top metal seed film.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: February 13, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: John Charles Ehmke, Virgil Cotoco Ararao
  • Patent number: 9837292
    Abstract: A method includes placing an underfill-shaping cover on a package component of a package, with a device die of the package extending into an opening of the underfill-shaping cover. An underfill is dispensed into the opening of the underfill-shaping cover. The underfill fills a gap between the device die and the package component through capillary. The method further includes, with the underfill-shaping cover on the package component, curing the underfill. After the curing the underfill, the underfill-shaping cover is removed from the package.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: December 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chih Chuang, Jung Wei Cheng, Chun-Hung Lin, Tsung-Ding Wang
  • Patent number: 9824953
    Abstract: A semiconductor module is disclosed. The semiconductor module may include a housing having a sidewall portion, a housing support plate coupled to a bottom surface of the sidewall portion such that the housing support plate and the sidewall portion define an interior space of the housing of the semiconductor module, and a semiconductor device disposed within the interior space and fixedly coupled to the housing. The semiconductor module may further include a cover member fixedly attached to a top surface of the sidewall portion such that the cover member, the housing and the housing support plate form a protective enclosure for the semiconductor device.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: November 21, 2017
    Assignee: Caterpillar Inc.
    Inventors: William Mische, Eric Andris, Basheer Qattum, Daniel Sergison
  • Patent number: 9741617
    Abstract: Encapsulated semiconductor packages and methods of production thereof. As a non-limiting example, a semiconductor package may be produced by partially dicing a wafer, molding the partially diced wafer, and completely dicing the molded and partially diced wafer.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: August 22, 2017
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Bora Baloglu, Curtis Zwenger, Ron Huemoeller
  • Patent number: 9661739
    Abstract: In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a portion of the metallic structure for each component area to be shielded is then exposed through the body by a cutting, drilling, or like operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed portion of the metallic structures.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: May 23, 2017
    Assignee: Qorvo US, Inc.
    Inventors: Donald Joseph Leahy, Brian D. Sawyer, Stephen Parker, Thomas Scott Morris
  • Patent number: 9633773
    Abstract: Disclosed herein are a thin film common mode filter and a method of manufacturing the same. The thin film common mode filter according to the exemplary embodiment of the present invention includes a magnetic substrate made of a magnetic ceramic material; and coil patterns formed on the magnetic substrate, wherein external electrodes connected with the coil patterns are sequentially stacked and insulating layers formed on and beneath the coil pattern are made of a composite of ferrite powder and thermosetting resin.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: April 25, 2017
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jeong Min Cho, Won Chul Sim, Ho Jin Yun, Ju Hwan Yang, Young Seuck Yoo
  • Patent number: 9634180
    Abstract: A method for forming semiconductor device package comprises providing a substrate with via contact pads and via through holes through said substrate, terminal pads on a bottom surface of said substrate and an exposed type through hole through said substrate. A die is provided with bonding pads thereon and an exposed type pad on a bottom surface of said die. A reflective layer is formed on an upper surface of the substrate. The die is adhered on the substrate. A dry film is formed on a top of the die as a slanting structure. A re-distribution layer conductive trace is formed by sputtering and E-plating on an upper surface of the slanting structure.
    Type: Grant
    Filed: December 21, 2014
    Date of Patent: April 25, 2017
    Assignee: KING DRAGON INTERNATIONAL INC.
    Inventor: Wen Kun Yang
  • Patent number: 9627603
    Abstract: A quartz vibrator that includes a substrate, a quartz vibrating element, and a dome-shaped cap. The quartz vibrating element is mounted on the substrate. The cap is bonded to the substrate. The cap defines and forms a sealed space that seals the quartz vibrating element along with the substrate. The cap has a side wall portion, a ceiling portion, and a connecting portion. The side wall portion encloses the quartz vibrating element. The ceiling portion is positioned above the quartz vibrating element. The connecting portion connects the side wall portion and the ceiling portion. The connecting portion is thinner than the side wall portion and the ceiling portion.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: April 18, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hiroaki Kaida, Manabu Ibayashi, Yoshifumi Saito, Yuichiro Nagamine, Katsuma Moroishi, Takuya Kono, Kazuhiro Mimura
  • Patent number: 9620475
    Abstract: In one implementation, a method of fabricating a power semiconductor package is disclosed. The method includes providing a conductive carrier array including a plurality of power modules held together with connecting bars, where each of the plurality of power modules includes a control transistor, a sync transistor, and a driver IC. The method further includes overlying on the conductive carrier array a heat spreader array including a plurality of power electrode heat spreaders such that each of the plurality of power electrode heat spreaders couples a drain of the sync transistor to a source of the control transistor in each power module.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: April 11, 2017
    Assignee: Infineon Technologies Americas Corp
    Inventor: Eung San Cho
  • Patent number: 9595501
    Abstract: A disclosed circuit arrangement includes a flexible substrate. A layer of pressure sensitive adhesive (PSA) is directly adhered to a first major surface of the substrate. One or more metal foil pads and electrically conductive wire are attached directly on a surface of the PSA layer. The wire has a round cross-section and one or more portions directly connected to the one or more metal foil pads with one or more weld joints, respectively. An electronic device is attached directly on the surface of the layer of PSA and is electrically connected to the one or more portions of the round wire by one or more bond wires, respectively.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: March 14, 2017
    Assignee: Automated Assembly Corporation
    Inventor: Robert Neuman
  • Patent number: 9576886
    Abstract: A lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad, terminals, and plastic encapsulation except on a back side of the sheet to provide an exposed thermal die pad, exposed side walls, and exposed back sides of the terminals. A solder wetable metal or metal alloy plating layer is on the back side and on the exposed the walls of the terminals. The exposed thermal pad and the back side of the terminals each include a contact region which lacks the plating layer.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: February 21, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Reynaldo Corpuz Javier, Alok Kumar Lohia, Andy Quang Tran
  • Patent number: 9570872
    Abstract: A method for mounting a rigid electrical connector, including selecting an electrical connector that is compatible with a predetermined portable electronic device; forming an aperture through an interface member, wherein the aperture is larger than the electrical connector; selecting an elastomeric potting material that is compatible with both the electrical connector and the interface member; locating the electrical connector in the aperture with a space between the electrical connector and the interface member; introducing the elastomeric potting material in an uncured state into the space between the electrical connector and the interface member; and while maintaining the space between the electrical connector and the interface member, curing the elastomeric potting material in the space therebetween.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: February 14, 2017
    Inventor: Jeffrey D. Carnevali
  • Patent number: 9548240
    Abstract: A semiconductor device comprises a semiconductor die including a conductive layer. A first insulating layer is formed over the semiconductor die and conductive layer. An encapsulant is disposed over the semiconductor die. A compliant island is formed over the first insulating layer. An interconnect structure is formed over the compliant island. An under bump metalization (UBM) is formed over the compliant island. The compliant island includes a diameter greater than 5 ?m larger than a diameter of the UBM. An opening is formed in the compliant island over the conductive layer. A second insulating layer is formed over the first insulating layer and compliant island. A third insulating layer is formed over an interface between the semiconductor die and the encapsulant. An opening is formed in the third insulating layer over the encapsulant for stress relief.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: January 17, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang, Xia Feng