INTEGRATED CIRCUITS HAVING PLACE-EFFICIENT CAPACITORS AND METHODS FOR FABRICATING THE SAME
Integrated circuits having place-efficient capacitors and methods for fabricating the same are provided. A dielectric layer is formed overlying a conductive feature on a semiconductor substrate. A via opening is formed into the dielectric layer to expose a portion of the conductive feature. A partial opening is etched into the dielectric layer and positioned over the conductive feature. Etch resistant particles are deposited overlying the dielectric layer and in the partial opening. The dielectric layer is further etched using the etch resistant particles as an etch mask to extend the partial opening. A first conductive layer is formed overlying the extended partial opening and electrically contacting the conductive feature. A capacitor insulating layer is formed overlying the first conductive layer. A second conductive layer is formed overlying the insulating layer.
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The present invention generally relates to integrated circuits and methods for fabricating integrated circuits, and more particularly relates to integrated circuits having place-efficient capacitors and methods for fabricating the same.
BACKGROUND OF THE INVENTIONDuring front end-of-the-line processing, a plurality of semiconductor devices (e.g., transistors, resistors, and the like) are formed on a semiconductor wafer. During back end-of-the-line (BEOL) processing, a plurality of semiconductor devices are interconnected to form a plurality of integrated circuits on the wafer, which are subsequently separated into individual die during wafer dicing. Interconnection of the semiconductor devices is accomplished via the formation of a plurality of BEOL layers, which include, in part, a number of metallization layers and a number of interlayer dielectric layers (ILD layers).
Capacitors are used in many electrical and electronic devices to implement a wide variety of functions. Capacitors may be fabricated as part of the back-end-of-the-line (BEOL) process. BEOL begins when a first metallization layer is deposited on the semiconductor wafer. Back end capacitors typically require a large amount of chip area and often compete for available chip area in which transistors can be formed.
There is a continual interest in the integration density of semiconductor devices, such as capacitors, etc. on the integrated circuit. High capacitance is desired for capacitors, including DRAM storage capacitors. “Capacitance” refers to the capacity of the device for storing electric charge. One approach to increase the capacitance is to increase the area of the capacitor electrodes. Capacitance is directly proportional to the surface area of the electrodes. However, this approach results in an increase in the actual area occupied by the capacitor on the integrated circuit or an increase in the size of the chip (the integrated circuit). Neither of these options is desirable as increasing the actual area occupied by the capacitor excludes other semiconductor devices and an increase in the chip size undermines the interest toward integration density.
Accordingly, it is desirable to provide integrated circuits having a capacitor with increased capacitance per unit area (i.e., a “place-efficient capacitor”) and methods for fabricating the same. It is also desired to increase the capacitance of the capacitor without occupying more chip space or increasing the size of the integrated circuit to enable an increase in the number of semiconductor devices integrated on a given area of the integrated circuit. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.
BRIEF SUMMARY OF THE INVENTIONMethods for fabricating integrated circuits having place-efficient capacitors are provided. In accordance with one exemplary embodiment, the method includes forming a dielectric layer overlying a conductive feature on a semiconductor substrate. A via opening is formed into the dielectric layer to expose a portion of the conductive feature. A partial opening is etched into the dielectric layer and positioned over the conductive feature. Etch resistant particles are deposited overlying the dielectric layer and in the partial opening. The dielectric layer is further etched using the etch resistant particles as an etch mask to extend the partial opening. A first conductive layer is formed overlying the extended partial opening and electrically contacting the conductive feature. A capacitor insulating layer is formed overlying the first conductive layer. A second conductive layer is formed overlying the insulating layer.
Methods for fabricating integrated circuits having place-efficient capacitors are provided in accordance with yet another exemplary embodiment of the present invention. The method includes forming a dielectric layer overlying a conductive feature on a semiconductor substrate. A via opening is formed in the dielectric layer to expose a portion of the conductive feature. The via opening is filled with an organic planarization layer (OPL) material. The dielectric layer is etched to form a partial opening positioned over the conductive feature. Etch-resistant particles are deposited over the dielectric layer in the partial opening. The dielectric layer is further etched around the etch-resistant particles to extend the partial opening forming an extended partial opening. The etch-resistant particles and the OPL material within the via opening are removed. A lower capacitor electrode is formed, for example from a metal liner, within the via opening and the extended partial opening. A capacitor insulating layer is formed overlying the metal liner. An upper capacitor electrode is formed filling the via opening and the extended partial opening with a metal fill material.
Integrated circuits having a place-efficient capacitor are provided in accordance with yet another exemplary embodiment of the present invention. The integrated circuit includes a lower capacitor electrode having a surface area that includes an inner surface area of an extended partial opening and a via opening formed in a patterned dielectric layer on a semiconductor substrate. A capacitor insulating layer overlies the lower capacitor electrode. An upper capacitor electrode metal fill material fills the extended partial opening and the via opening and has a surface area that includes the inner surface area of the extended partial opening and via opening.
The present invention will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and
The following detailed description of the invention is merely exemplary in nature and is not intended to limit the invention or the application and uses of the invention. Furthermore, there is no intention to be bound by any theory presented in the preceding background of the invention or the following detailed description of the invention.
Various embodiments are directed to integrated circuits having place-efficient capacitors and methods for fabricating the same. As used herein and noted previously, “place-efficient capacitors” are capacitors with increased capacitance per unit area. Etch-resistant particles are used as patterning agents to introduce porosity to a dielectric layer of the integrated circuit to increase the effective area between capacitor electrodes, thereby increasing the capacitor capacitance, without the capacitor occupying more area on the integrated circuit or increasing the size of the integrated circuit. A place-efficient capacitor frees up available space on the integrated circuit for other semiconductor devices, thereby improving the economics of integrated circuit fabrication.
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After the further etching step is completed, the etch-resistant particles, the residual second photoresist layer, and the OPL layer including within the via opening are removed to leave a patterned dielectric layer 42 that is roughened with increased surface area as illustrated in
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From the foregoing, it is to be appreciated that the integrated circuit having a place-efficient capacitor fabricated in accordance with exemplary embodiments achieves significantly higher capacitance per unit area on the integrated circuit. The effective area between the capacitor electrodes is increased, enabling more efficient use of the chip area, particularly useful for high density DRAM arrays. The effective capacitor area is increased without occupying more chip space by increasing the surface area of the dielectric layer between the capacitor electrodes. A higher number of semiconductor devices may be integrated on a given area of the integrated circuit or higher capacitance can be achieved for a single semiconductor device.
While at least one exemplary embodiment has been presented in the foregoing detailed description of the invention, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the invention in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the invention, it being understood that various changes may be made in the function and arrangement of elements described in an exemplary embodiment without departing from the scope of the invention as set forth in the appended claims and their legal equivalents.
Claims
1. A method for fabricating an integrated circuit having a place-efficient capacitor comprising:
- forming a dielectric layer overlying a conductive feature on a semiconductor substrate;
- forming a via opening into the dielectric layer to expose a portion of the conductive feature;
- etching a partial opening into the dielectric layer and positioned over the conductive feature;
- depositing etch resistant particles overlying the dielectric layer and in the partial opening;
- further etching the dielectric layer using the etch resistant particles as an etch mask to extend the partial opening;
- forming a first conductive layer overlying the extended partial opening and electrically contacting the conductive feature;
- forming a capacitor insulating layer overlying the first conductive layer; and
- forming a second conductive layer overlying the insulating layer.
2. The method of claim 1, wherein forming a via opening into the dielectric layer comprises:
- forming and patterning an opening in a first photoresist layer; and
- etching the via opening.
3. The method of claim 1, further comprising after the forming a via opening and before etching a partial opening:
- forming an organic planarization layer (OPL) overlying the dielectric layer including filling the via opening;
- forming a second photoresist layer on the organic planarization layer (OPL); and forming and patterning a second opening in the second photoresist layer and OPL layer.
4. The method of claim 1, wherein depositing etch resistant particles comprises depositing etch resistant particles from the group selected from porous polymers, organic or inorganic particles, and combinations thereof.
5. The method of claim 1, wherein depositing etch resistant particles comprises depositing etch resistant particles to distribute the etch resistant particles overlying the dielectric layer and in the partial opening.
6. (canceled)
7. The method of claim 1, wherein forming a first conductive layer comprises forming a metal liner.
8. The method of claim 7, wherein forming a first conductive layer comprises forming a lower capacitor electrode having an irregular surface area of the extended partial opening and via opening.
9. The method of claim 1, wherein forming a second conductive layer overlying the insulating layer comprises forming a metal layer overlying the insulating layer including filling the extended partial opening with a metal fill material.
10. A method for fabricating an integrated circuit having a place-efficient capacitor comprising:
- forming a dielectric layer overlying a conductive feature on a semiconductor substrate;
- forming a via opening into the dielectric layer to expose a portion of the conductive feature;
- filling the via opening with an organic planarization layer (OPL) material;
- etching the dielectric layer to form a partial opening positioned over the conductive feature;
- depositing etch-resistant particles over the dielectric layer in the partial opening;
- further etching the dielectric layer around the etch-resistant particles to extend the partial opening forming an extended partial opening;
- removing the etch-resistant particles and the OPL material within the via opening;
- forming a lower capacitor electrode comprising a metal liner within the via opening and the extended partial opening;
- forming a capacitor insulating layer overlying the metal liner; and
- forming an upper capacitor electrode comprising filling the via opening and the extended partial opening with a metal fill material.
11. The method of claim 10, wherein forming a via opening into the dielectric layer comprises:
- forming and patterning an opening in a first photoresist layer; and
- etching the via opening.
12. The method of claim 10, further comprising after filling the via opening and before etching the dielectric layer:
- forming a second photoresist layer on the OPL material; and
- forming and patterning a second opening in the second photoresist layer and OPL material, the partial opening extending the second opening.
13. The method of claim 10, wherein etching the dielectric layer to form a partial opening comprises etching to form a partial opening transverse to the via opening.
14. The method of claim 10, wherein depositing etch resistant particles comprises depositing etch resistant particles from the group selected from porous polymers, organic or inorganic particles, and combinations thereof.
15. The method of claim 14, wherein depositing etch resistant particles comprises depositing etch-resistant inorganic particles selected from the group consisting of platinum, gold, carbon, and combinations thereof.
16. The method of claim 14, wherein depositing etch resistant particles comprises depositing etch resistant particles with an area coverage of about 20% to about 60%.
17. (canceled)
18. The method of claim 10, wherein forming a lower capacitor electrode comprises forming the lower capacitor electrode having an irregular surface area of the extended partial opening and via opening.
19. The method of claim 10, wherein forming an upper capacitor electrode comprises forming a metal layer overlying the capacitor insulating layer including filling the via opening and the extended partial opening with the metal fill material of the metal layer.
20. (canceled)
Type: Application
Filed: Feb 7, 2011
Publication Date: Aug 9, 2012
Applicant: GLOBALFOUNDRIES INC. (Grand Cayman)
Inventor: Dmytro CHUMAKOV (Dresden)
Application Number: 13/022,416
International Classification: H01L 23/522 (20060101); H01L 21/02 (20060101);