Of Capacitor (epo) Patents (Class 257/E21.008)
  • Patent number: 11164938
    Abstract: Methods of forming and processing semiconductor devices are described. Certain embodiments relate to the formation of self-aligned DRAM capacitors. More particularly, certain embodiments relate to the formation of self-aligned DRAM capacitors utilizing the formation of self-aligned growth pillars. The pillars lead to greater capacitor heights, increase critical dimension uniformity, and self-aligned bottom and top contacts.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: November 2, 2021
    Assignee: Micromaterials LLC
    Inventors: Uday Mitra, Regina Freed, Ho-yung David Hwang, Sanjay Natarajan, Lequn Liu
  • Patent number: 11056556
    Abstract: A method of fabricating a metal-insulator-metal (MIM) capacitor structure includes forming a bottom electrode, forming a first oxide layer adjacent the bottom electrode, and depositing a first high-k dielectric layer over the bottom electrode and the first oxide layer. A middle electrode is then formed over the first high-k dielectric layer and a second oxide layer is formed adjacent the middle electrode. A second high-k dielectric layer may be deposited over the middle electrode and the second oxide layer and a top electrode over the second high-k dielectric layer.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: July 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiang-Ku Shen, Ming-Hong Kao, Hui-Chi Chen, Dian-Hau Chen, Yen-Ming Chen
  • Patent number: 11043413
    Abstract: Embodiments described herein relate generally to one or more methods for forming a barrier layer for a conductive feature in semiconductor processing. In some embodiments, an opening is formed through a dielectric layer to a conductive feature. A barrier layer is formed in the opening along a sidewall of the dielectric layer and on a surface of the conductive feature. Forming the barrier layer includes depositing a layer including using a precursor gas. The precursor gas has a first incubation time for deposition on the surface of the conductive feature and has a second incubation time for deposition on the sidewall of the dielectric layer. The first incubation time is greater than the second incubation time. A conductive fill material is formed in the opening and on the barrier layer.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: June 22, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Pang Kuo, Ya-Lien Lee
  • Patent number: 10957588
    Abstract: Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one self-aligned via within at least dielectric material; plugging the at least one self-aligned via with material; forming a protective sacrificial mask over the material which plugs the at least one self-aligned via, after a recessing process; forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the material during the trench formation; removing the protective sacrificial mask and the material within the at least one self-aligned via to form a wiring via; and filling the wiring via and the at least one trench with conductive material.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: March 23, 2021
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Mark L. Lenhardt, Frank W. Mont, Brown C. Peethala, Shariq Siddiqui, Jessica P. Striss, Douglas M. Trickett
  • Patent number: 10879389
    Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, a first well region formed in a portion of the semiconductor substrate, having a second conductivity type that is the opposite of the first conductivity type. A second well region is formed in a portion of the first well region, having the first conductivity type. A first gate structure is formed over a portion of the second well region and a portion of the first well region. A first doped region is formed in a portion of the second well region. A second doped region is formed in a portion of the first well region, having the second conductivity type. A second dielectric layer is formed over a portion of the first gate structure, a portion of the first well region, and a portion of the second doped region.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: December 29, 2020
    Assignee: MEDIATEK INC
    Inventors: Cheng-Hua Lin, Yan-Liang Ji, Chih-Wen Hsiung
  • Patent number: 10879303
    Abstract: Each semiconductor chip of a detector comprises a semiconductor substrate having a plurality of photodetector units, an insulating layer formed on a front face of the semiconductor substrate, a common electrode arranged on the insulating layer, a readout line for electrically connecting a quenching resistance of each photodetector unit and the common electrode to each other, and a through electrode extending from the common electrode to a rear face of the semiconductor substrate through a through hole of the semiconductor substrate.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: December 29, 2020
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Yoshimaro Fujii, Terumasa Nagano, Kazuhisa Yamamura, Kenichi Sato, Ryutaro Tsuchiya
  • Patent number: 10840294
    Abstract: Each semiconductor chip of a detector comprises a semiconductor substrate having a plurality of photodetector units, an insulating layer formed on a front face of the semiconductor substrate, a common electrode arranged on the insulating layer, a readout line for electrically connecting a quenching resistance of each photodetector unit and the common electrode to each other, and a through electrode extending from the common electrode to a rear face of the semiconductor substrate through a through hole of the semiconductor substrate.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: November 17, 2020
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Yoshimaro Fujii, Terumasa Nagano, Kazuhisa Yamamura, Kenichi Sato, Ryutaro Tsuchiya
  • Patent number: 10825505
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for staggering the timing of targeted refresh operations. Memory dies may need to periodically perform refresh operations, which may be auto-refresh operations or targeted refresh operations. Targeted refresh operations may draw less current than auto-refresh operations. When dies are collected into a group (e.g., a memory stack, a memory module) the timing of targeted refresh operations may be staggered between the different dies to help reduce the peak current drawn. The targeted refresh operations may be staggered such that, when a maximum number of the dies are performing a refresh operation, at least one of the dies performs a targeted refresh operation instead of an auto-refresh operation.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventor: James S. Rehmeyer
  • Patent number: 10784393
    Abstract: A photodetection element is a photodetection element having an incidence surface for light on a back surface of a semiconductor layer, and includes a periodic nano-concave/convex structure provided on a front surface of the semiconductor layer and having convex portions and concave portions constituting a longitudinal resonator and a transverse resonator for the light incident from the incidence surface, the periodic nano-concave/convex structure converting the light into surface plasmons, and a metal film provided to cover the periodic nano-concave/convex structure, a height and an arrangement pitch of the convex portions in the periodic nano-concave/convex structure are set such that a resonance wavelength of the longitudinal resonator and a resonance wavelength of the transverse resonator match, and a thickness of the metal film is equal to or greater than 20 nm.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: September 22, 2020
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Hiroyasu Fujiwara, Wei Dong, Kazutoshi Nakajima, Shohei Hayashi
  • Patent number: 10755938
    Abstract: The present disclosure provides a semiconductor structure, including an active region with a first surface; an isolated region having a second surface, surrounding the active region, the first surface being higher than the second surface; and a metal gate having a plurality of metal layers disposed over the first surface and the second surface. A ratio of a thinnest portion and a thickest portion of at least one of the plurality of metal layers is greater than about 40%.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chi-Cheng Hung, Yu-Sheng Wang, Ting-Siang Su, Ching-Hwanq Su
  • Patent number: 10748860
    Abstract: Parallel inductors include a first metal wire (8a or 8b) for connecting a drain terminal (2) and a first metal pattern (7a or 7b), and a second metal wire (10a or 10b) for connecting the first metal pattern (7a or 7b) and a second metal pattern (9a or 9b). The second metal wires (10a and 10b) are each positioned between the corresponding first metal wire (8a or 8b) and a corresponding third metal wire (12a or 12b) for connecting the drain terminal (2) and a third metal pattern (11). The direction of current through the second metal wires (10a and 10b) is opposite to the direction of current through each of the first metal wire (8a or 8b) and the third metal wire (12a or 12b).
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: August 18, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Keigo Nakatani, Yuji Komatsuzaki, Shintaro Shinjo, Koji Yamanaka, Shohei Imai
  • Patent number: 10720357
    Abstract: A method of forming a semiconductor device. The method may include providing a device structure, where the device structure comprises a masked portion and a cut portion. The masked portion may comprise a mask covering at least one semiconductor fin of a fin array, and the cut portion may comprise a trench, where the trench exposes a semiconductor fin region of the fin array. The method may further include providing an exposure of the trench to oxidizing ions, the oxidizing ions to transform a semiconductor material into an oxide.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: July 21, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Min Gyu Sung, Naushad K Variam, Sony Varghese, Johannes Van Meer, Jae Young Lee, Jun Lee
  • Patent number: 10707180
    Abstract: A bond pad structure and method are provided. The structure includes a first conductive layer formed over a substrate. A second conductive layer is formed over a first portion of the first conductive layer, and a first portion of the second conductive layer forms a first capacitor electrode. A third conductive layer is formed over the first conductive layer and second conductive layer, and a first portion of the third conductive layer forms a second capacitor electrode. A second portion of the third conductive layer forms a wire bond region. A dielectric material is disposed between the first capacitor electrode and the second capacitor electrode to form a first capacitor.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: July 7, 2020
    Assignee: NXP USA, INC.
    Inventors: Ricardo Uscola, Michele Lynn Miera, Sai Sunil Mangaonkar, Jitesh Vaswani
  • Patent number: 10699999
    Abstract: A metal-insulator-metal (MIM) capacitor structure is provided. The MIM capacitor structure includes a first conductive layer formed over a substrate, and the first conductive layer includes a first portion and a second portion. The MIM capacitor structure also includes an insulating layer formed over the first portion of the first conductive layer and a second conductive layer formed over the first conductive layer. The second conductive layer includes a first portion and a second portion, the first portion of the second conductive layer is in direct contact with the insulating layer, and the second portion of the second conductive layer is in direct contact with the second portion of the first conductive layer.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Chung Jen, Chia-Lun Hsu
  • Patent number: 10665393
    Abstract: A capacitor includes a support member included in a body, a plurality of pillars disposed in an upper portion of the support member and each having a lower portion wider than an upper portion, and a capacitor layer disposed on a side surface and an upper surface of each pillar and including a dielectric layer and first and second electrodes alternately disposed with the dielectric layer interposed therebetween. Lower end portions of adjacent pillars are in contact with each other.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: May 26, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jeong Hoon Ryou, Dong Sik Yoo, Seung Hun Han, No Il Park, Seung Mo Lim, Hyun Ho Shin
  • Patent number: 10553530
    Abstract: Embodiments of the disclosure relate to a three-dimensional (3D) inductor-capacitor (LC) circuit. The 3D LC circuit includes an inductor formed by a conductive ribbon of a defined height and a conductive sleeve conductively coupled to the conductive ribbon. The conductive sleeve and the conductive ribbon can generate a built-in capacitance(s) for the 3D LC circuit. In examples discussed herein, the conductive ribbon can also help reduce the skin effect of the inductor by distributing an electrical current across the defined height of the conductive ribbon. By generating the built-in capacitance(s) and distributing the electrical current across the defined height of the conductive ribbon, it is possible to reduce current crowding and improve quality factor (Q-factor) of the 3D LC circuit. As a result, it is possible to couple one or more 3D LC circuits to form a high performance radio frequency (RF) filter(s) for the fifth-generation (5G) wireless communication systems.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: February 4, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Dirk Robert Walter Leipold, George Maxim, Danny W. Chang, Baker Scott
  • Patent number: 10516110
    Abstract: Subject matter disclosed herein may relate to fabrication of correlated electron materials used, for example, to perform a switching function. In embodiments, processes are described, which may be useful in avoiding formation of a potentially resistive oxide layer at an interfacial surface between a conductive substrate, for example, and a correlated electron material.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: December 24, 2019
    Assignee: ARM Ltd.
    Inventors: Kimberly Gay Reid, Lucian Shifren
  • Patent number: 10510825
    Abstract: A reliable metal insulator metal (MIM) capacitor is disclosed. The MIM capacitor is disposed over at least an interlevel dielectric (ILD) layer of a plurality of ILD layers with interconnects disposed over a substrate. The MIM capacitor includes a capacitor dielectric disposed between top and bottom metal capacitor electrodes. The edges of the top metal electrode at the interface with the capacitor dielectric are rounded. The rounded edges of the top capacitor electrode at the interface with the capacitor dielectric reduce edge electric field, thereby improves time-dependent dielectric breakdown (TDDB) reliability of the capacitor.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: December 17, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Zhehui Wang, Hai Cong, Ramadas Nambatyathu
  • Patent number: 10491172
    Abstract: A circuit including a radio frequency (RF) amplifier including a transistor configured to receive an RF signal at its control terminal, a capacitor coupled to a first terminal of the transistor, an inductor coupled to a second terminal of the transistor, wherein the capacitor and inductor form a loop from the first terminal to the second terminal, wherein the loop bypasses a parasitic inductance between the second terminal and ground.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: November 26, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Tianzuo Xi, Haichuan Kang, ZhenQi Chen, Zhenying Luo, Xiangdong Zhang, Xinwei Wang, Yanjie Sun, Yan Kit Gary Hau, Jing-Hwa Chen
  • Patent number: 10446535
    Abstract: A three-dimensional integrated structure is formed by a first substrate with first components oriented in a first direction and a second substrate with second components oriented in a second direction. An interconnection level includes electrically conducting tracks that run in a third direction. One of the second direction and third direction forms a non-right and non-zero angle with the first direction. An electrical link formed by at least one of the electrically conducting tracks electrically connected two points of the first or of the second components.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: October 15, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexandre Ayres, Bertrand Borot
  • Patent number: 10424440
    Abstract: A capacitor that includes a lower common electrode having a first region and a second region, a first upper electrode opposing the first region, a first dielectric layer between the first region and the first upper electrode, a second upper electrode located in a layer in which the first upper electrode is located and opposing the second region, a second dielectric layer between the second region and the second upper electrode, a first connection electrode electrically connected to the first upper electrode, a second connection electrode located in a layer in which the first connection electrode is located and electrically connected to the second upper electrode, and auxiliary electrodes located in a layer different from a layer in which the lower common electrode is located and that connect the first region and the second region of the lower common electrode.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: September 24, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Toshiyuki Nakaiso, Takashi Komiyama
  • Patent number: 10386326
    Abstract: Flexible electrical devices are provided that include a coated inner carbon nanotube electrode that has an exterior surface, an outer carbon nanotube electrode disposed on the exterior surface of the coated inner carbon nanotube electrode, and an overlap region in which the coated inner carbon nanotube electrode and the outer carbon nanotube electrode overlap one another, in which the device has a fiber-like geometry and first and second electrode ends. Methods are provided for fabricating an electrical component that includes a flexible electrical component having a fiber-like geometry and includes carbon nanotube electrodes.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: August 20, 2019
    Assignee: The Florida State University Research Foundation, Inc.
    Inventors: Jesse Smithyman, Zhiyong Liang
  • Patent number: 10355131
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure comprises a semiconductor substrate comprising two source/drain regions, a gate stack over the semiconductor substrate and between the source/drain regions, and a spacer over the semiconductor substrate and surrounding the gate stack. The spacer comprises a carbon-containing layer and a carbon-free layer.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: July 16, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Shiang-Bau Wang
  • Patent number: 10319675
    Abstract: The present disclosure provides one embodiment of a semiconductor structure that includes an interconnection structure formed on a semiconductor substrate; and a capacitor disposed in the interconnection structure. The interconnection structure includes a top electrode; a bottom electrode; a dielectric material layer sandwiched between the top and bottom electrodes; and a nanocrystal layer embedded in the dielectric material layer.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: June 11, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Chieh Lai, Meng-Ting Yu, Yung-Hsien Wu, Kuang-Hsin Chen
  • Patent number: 10312084
    Abstract: A method for fabricating the semiconductor device is disclosed. A semiconductor substrate having a main surface is provided. A gate is formed on the main surface of the semiconductor substrate. An offset liner is formed on the sidewall of the gate. An ion implantation process is performed to form lightly doped drain (LDD) region in the semiconductor substrate. A spacer is formed on a sidewall of the gate. A cavity is recessed into the main surface of the semiconductor substrate. The cavity is adjacent to the spacer. An epitaxial layer is grown in the cavity. The spacer is then subjected to a surface treatment to form a dense oxide film on the spacer. A mask layer is deposited on the dense oxide film. The dense oxide film has a thickness that is smaller or equal to 12 angstroms.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: June 4, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuang-Hsiu Chen, Yi-Liang Ye, Chueh-Yang Liu, Yu-Ren Wang
  • Patent number: 10243080
    Abstract: Methods of selectively depositing high-K gate dielectric on a semiconductor structure are disclosed. The method includes providing a semiconductor structure disposed above a semiconductor substrate. The semiconductor structure is disposed beside an isolation sidewall. A sacrificial blocking layer is then selectively deposited on the isolation sidewall and not on the semiconductor structure. Thereafter, a high-K gate dielectric is deposited on the semiconductor structure, but not on the sacrificial blocking layer. Properties of the sacrificial blocking layer prevent deposition of oxide material on its surface. A thermal treatment is then performed to remove the sacrificial blocking layer, thereby forming a high-K gate dielectric only on the semiconductor structure.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: March 26, 2019
    Assignee: Intel Corporation
    Inventors: Grant Kloster, Scott B. Clendenning, Rami Hourani, Szuya S. Liao, Patricio E. Romero, Florian Gstrein
  • Patent number: 10141223
    Abstract: A method of improving micro-loading effect when recess etching a tungsten layer. A substrate having trenches thereon is provided. A tungsten layer is deposited on the substrate and in the trenches. A planarization process is performed to form a planarization layer on the tungsten layer. A first etching process is performed to etch the planarization layer and the tungsten layer with an etch selectivity of planarization layer:tungsten layer=1:1 until the planarization layer is completely removed. A second etching process is performed to etch the remainder of the tungsten layer to recess the tungsten layer within the trenches.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: November 27, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Chiang Chen, Fu-Che Lee, Ming-Feng Kuo
  • Patent number: 10134584
    Abstract: A method of manufacturing a semiconductor device includes forming a seed layer on a substrate by alternately performing supplying a halogen-based first process gas to the substrate and supplying a non-halogen-based second process gas to the substrate, and forming a film on the seed layer by supplying a third process gas to the substrate. A pressure of a space where the substrate exists in the act of supplying the first process gas is set higher than a pressure of the space where the substrate exists in the act of supplying the second process gas.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: November 20, 2018
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Yugo Orihashi, Atsushi Moriya
  • Patent number: 10115719
    Abstract: Integrated circuits having resistor structures formed from a MIM capacitor material and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with a resistor area and a capacitor area. The method includes depositing a capacitor material over the resistor area and the capacitor area of the semiconductor substrate. The method also includes forming a resistor structure from the capacitor material in the resistor area. Further, the method includes forming electrical connections to the resistor structure in the resistor area.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: October 30, 2018
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Jagar Singh, Sanford Chu
  • Patent number: 10115786
    Abstract: A capacitor includes: a bottom electrode; a middle electrode on the bottom electrode; a top electrode on the middle electrode; a first dielectric layer between the bottom electrode and the middle electrode; and a second dielectric layer between the middle electrode and the top electrode. Preferably, the second dielectric layer is disposed on at least a sidewall of the middle electrode to physically contact the first dielectrically, and the middle electrode includes a H-shape.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: October 30, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhibiao Zhou, Shao-Hui Wu, Chi-Fa Ku, Chen-Bin Lin
  • Patent number: 10090245
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure over the substrate. The semiconductor device structure includes a first dielectric layer over the substrate and the first conductive structure. The semiconductor device structure includes a second conductive structure over the first conductive structure and extending into the first dielectric layer. The second conductive structure is electrically connected to the first conductive structure. The semiconductor device structure includes a cover layer between the second conductive structure and the first dielectric layer. The cover layer surrounds the second conductive structure, the second conductive structure passes through the cover layer and is partially between the cover layer and the first conductive structure, and the cover layer includes a metal oxide.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: October 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Fang Cheng, Chi-Lin Teng, Hai-Ching Chen, Hsin-Yen Huang, Tien-I Bao, Jung-Hsun Tsai
  • Patent number: 10083893
    Abstract: According to an embodiment, a semiconductor device is provided. The semiconductor device includes a through-hole, a copper layer, and a metal portion. The through-hole penetrates a semiconductor substrate between front and rear sides. The copper layer is formed inside the through-hole. The metal portion is made of a metal other than copper, formed closer to a hole core side of the through-hole than the copper layer is, and involves a void therein.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: September 25, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Koji Ogiso, Kazuyuki Higashi, Tatsuo Migita
  • Patent number: 10026926
    Abstract: Embodiments relate to a method of forming an organic light emitting diode (OLED) display device. A first inorganic layer, a first organic layer, and a second inorganic layer are formed on pixel regions of an OLED display device. At least part of a first inorganic layer is formed using atomic layer deposition (ALD), such that the first inorganic layer completely covers particles generated on the OLED. Embodiments also relate to an OLED display device with pixel regions, each pixel region including an OLED, a bank layer across a boundary between adjacent pixel regions, and a first inorganic layer on at least a portion of the OLED and the bank layer. The first inorganic layer includes a first inorganic sub-layer and a second inorganic sub-layer.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: July 17, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: Jae-Young Lee, Ji-Min Kim, Gi-Youn Kim, Sang-Hoon Oh
  • Patent number: 9997700
    Abstract: A method for manufacturing an RRAM cell includes providing a metal-insulator-metal stack and exposing a subsection of a MIM stack to particle bombardment and/or radiation. Exposing a subsection of the MIM stack to particle bombardment and/or radiation forms localized defects in the functional layer of the MIM stack, thereby reducing the required forming voltage of the RRAM cell and further providing precise control over the location of a conductive filament created in the MIM stack during forming of the device.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: June 12, 2018
    Assignee: Carnegie Mellon University
    Inventors: Mohamed Abdeltawab Abdelmoula, Marek Skowronski, Abhishek A. Sharma, James A. Bain
  • Patent number: 9991330
    Abstract: The present application provides planar and stacked resistor structures that are embedded within an interconnect dielectric material in which the resistivity of an electrical conducting resistive material or electrical conducting resistive materials of the resistor structure can be tuned to a desired resistivity during the manufacturing of the resistor structure. Notably, a doped metallic insulator layer is formed atop a substrate. A controlled surface treatment process is then performed to an upper portion of the doped metallic insulator layer to convert the upper portion of the doped metallic insulator layer into an electrical conducting resistive material layer. The remaining doped metallic insulator layer and the electrical conducting resistive material layer are then patterned to provide the resistor structure.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: June 5, 2018
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Chih-Chao Yang
  • Patent number: 9985106
    Abstract: Semiconductor devices may include a field insulating layer that is on a substrate, a gate structure that is on the substrate and separated from the field insulating layer, a first spacer structure that is on sidewalls and a lower surface of the gate structure and is separated from the field insulating layer, and a second spacer structure that is on a part of an upper surface of the field insulating layer that is overlapped by the gate structure.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: May 29, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang Jine Park, Yong Sun Ko, In Seak Hwang
  • Patent number: 9978938
    Abstract: A metal-insulator-metal (MIM) capacitor structure of an RRAM device includes a first electrode and a second electrode with an insulating layer interposing the first and second electrodes. The conductive filament providing for a switching function of the RRAM device may be formed within the insulating layer. Further, a nitrogen-rich metal layer interposes the second electrode and the insulating layer. The nitrogen-rich metal layer includes a greater nitrogen concentration than that of the adjacent second electrode.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: May 22, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hai-Dang Trinh, Cheng-Yuan Tsai, Hsing-Lien Lin
  • Patent number: 9941565
    Abstract: An isolator device and a corresponding method of forming the isolator device to include first and second electrodes, a layer of first dielectric material between the first and second electrodes, and at least one region of second dielectric material between the layer of first dielectric material and at least one of the first and second electrodes. The second dielectric material has a higher relative permittivity than the first dielectric material.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: April 10, 2018
    Assignee: Analog Devices Global
    Inventors: Conor John McLoughlin, Michael John Flynn, Laurence B. O'Sullivan, Shane Geary, Stephen O'Brien, Bernard P. Stenson, Baoxing Chen, Sarah Carroll, Michael Morrissey, Patrick M. McGuinness
  • Patent number: 9929086
    Abstract: In a semiconductor device (SD), plate-shaped upper electrodes (UEL) are formed on a lower electrode (LEL) with a dielectric film (DEC) interposed therebetween. The lower electrode (LEL), the dielectric film (DEC), and the upper electrodes (UEL) constitute MIM capacitors (MCA). One of the upper electrodes (UEL) and another upper electrode (UEL) that are adjacent to each other are arranged at an equal distance (D1), without the guard ring being interposed therebetween. The upper electrodes (UEL) positioned on the outermost periphery and the guard ring (GR) positioned outside those upper electrodes UEL are arranged at a distance equal to the distance (D1) from each other.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: March 27, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuo Tomita, Keiichi Yamada
  • Patent number: 9923047
    Abstract: The inventive concepts provide semiconductor devices and methods for manufacturing the same in which the method includes forming a capacitor including a bottom electrode, a dielectric layer and a top electrode sequentially stacked on a substrate, and also where formation of the top electrode includes forming a first metal nitride layer on the dielectric layer, and forming a second metal nitride layer on the first metal nitride layer, in which the first metal nitride layer is disposed between the dielectric layer and the second metal nitride layer, and the first metal nitride layer is formed at a temperature lower than a temperature at which the second metal nitride layer is formed.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: March 20, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Se Hoon Oh, Seongyul Park, Chin Moo Cho, Yunjung Choi, Gyu-Hee Park, Youn-Joung Cho, Younsoo Kim, Jae Hyoung Choi
  • Patent number: 9818603
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes providing a substrate, the substrate includes a first fin, a second fin, and an isolation region disposed between the first fin and the second fin. The second fin includes a different material than a material of the substrate. The method includes forming an oxide over the first fin, the second fin, and a top surface of the isolation region at a temperature of about 400 degrees C. or less, and post-treating the oxide at a temperature of about 600 degrees C. or less.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: November 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chi Lin, Chin-Hsiang Lin, Neng-Kuo Chen, Sey-Ping Sun
  • Patent number: 9806032
    Abstract: The disclosure relates to integrated circuit (IC) structures and fabrication techniques. Methods according to the disclosure can include: providing a precursor structure including: a first inter-metal dielectric (IMD); a barrier dielectric positioned on the first IMD; forming an insulator on the barrier dielectric of the precursor structure, wherein an upper surface of the insulator includes a first trench and a second trench laterally separated from the first trench; forming an alignment marker over the precursor structure by filling the first trench with a first refractory metal film; forming a first metal-insulator-metal (MIM) electrode by filling the second trench with the first refractory metal film; recessing the insulator without exposing an upper surface of the barrier dielectric; forming a MIM dielectric layer on the insulator; and forming a second MIM electrode on the MIM dielectric layer, such that the second MIM electrode overlies a portion of the first MIM electrode.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: October 31, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wei Lin, Nailong He, Upinder Singh
  • Patent number: 9780032
    Abstract: A wiring substrate includes a first insulation layer, a wiring layer formed on an upper surface of the first insulation layer, a barrier film that covers the upper surface of the first insulation layer, an upper surface of the wiring layer, and side surfaces of the wiring layer, and a second insulation layer that covers an upper surface of the barrier film and side surfaces of the barrier film. The barrier film is an alumina film containing carbon atoms, and the alumina film has a carbon atom content rate that is in the range of 0.2 atomic % to 3.6 atomic %.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: October 3, 2017
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Tomoo Yamasaki, Kazuhiro Fujita
  • Patent number: 9777372
    Abstract: A method for fabricating articles for use in optics, electronics, and plasmonics includes large scale lithography or other patterning and conformal deposition such as by atomic layer deposition.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: October 3, 2017
    Assignee: REGENTS OF THE UNIVERSITY OF MINNESOTA
    Inventors: Sang-Hyun Oh, Xiaoshu Chen
  • Patent number: 9773701
    Abstract: A method of forming an integrated circuit includes forming at least one opening through a first surface of a substrate. The method further includes forming at least one conductive structure in the at least one opening. The method further includes removing a portion of the substrate to form a processed substrate having the first surface and a second surface opposite the first surface and to expose a portion of the at least one conductive structure adjacent to the second surface. The at least one conductive structure continuously extending from the first surface through the processed substrate to the second surface of the processed substrate, at least one sidewall of the at least one conductive structure spaced from a sidewall of the at least one opening by an air gap.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: September 26, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Hung Liu, Ku-Feng Yang, Pei-Ching Kuo, Ming-Tsu Chung, Hsin-Yu Chen, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 9773860
    Abstract: A method for fabricating a capacitor is disclosed. First, a substrate is provided, a bottom electrode and a capacitor dielectric layer are formed on the substrate, a conductive layer is formed on the capacitor dielectric layer, a patterned hard mask is formed on the conductive layer, a patterned hard mask is used to remove part of the conductive layer to form a top electrode, the patterned hard mask is removed, and a protective layer is formed on a top surface and sidewalls of top electrode. Preferably, the protective layer includes metal oxides.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: September 26, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Tsung Lai, Ching-Li Yang, Yu-Cheng Tung, Shih-Che Huang, Chih-Sheng Chang
  • Patent number: 9767730
    Abstract: An organic light emitting diode display includes a pixel portion displaying an image and a peripheral portion surrounding the pixel portion, a semiconductor layer including a pixel switching semiconductor layer on the pixel portion on the substrate, a being driving semiconductor layer, and a peripheral switching semiconductor layer on the peripheral portion, a first gate insulating layer on the semiconductor layer, a peripheral switching gate electrode on the first gate insulating layer of the peripheral portion, a second gate insulating layer covering the peripheral switching gate electrode and the first gate insulating layer, a pixel switching gate electrode and a driving gate electrode on the second gate insulating layer of the pixel portion, and a third gate insulating layer covering the pixel switching gate electrode, the driving gate electrode, and the second gate insulating layer.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: September 19, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Deok-Hoi Kim
  • Patent number: 9728812
    Abstract: The present invention discloses an electrostatic energy storage device and a preparation method thereof. The device comprises at least one electrostatic energy storage unit, wherein each electrostatic energy storage unit is provided with a five-layer structure and comprises two metal film electrodes which form a capacitor, composite nano insulating film layers attached to the inner sides of the two metal film electrodes, and a ceramic nano crystalline film arranged between the composite nano insulating film layers. Based on the electrostatic parallel-plate induction capacitor principle, the metal film electrodes with a nano microstructure and the ceramic nano crystalline film sandwiched between the metal film electrodes and having an ultrahigh dielectric constant form an electrostatic induction plate capacitor to store electrostatic energy.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: August 8, 2017
    Inventors: Jin Bai, Gang Feng
  • Patent number: 9715966
    Abstract: A supercapacitor, principally ceramic, with a fast recharging rate and extremely high energy density. Energy densities can exceed 9.5 KW-hr/L (0.27 MW-hr/ft3). High permittivity, high voltage breakdown and nanoporous electrodes achieve these features. High permittivity is reached through a ceramic dielectric consisting of a titanium oxide variant, doped with various combinations of trivalent positive ions. Example: (Al0.5Nb0.5)0.5%Ti99.5%O2. The dielectric permittivity is further increased by adding layers of conductive island matrices placed in the dielectric. Charge capacity is expanded by use of nanoporous electrodes with an effective area over twenty times a flat surface electrode. Example: graphene. The key process involves sintering wafers, adding conductive island matrices' conductors, typically vacuum impregnating wafers with a polymer, then stacking wafers and electrodes, followed by connecting electrodes. Subassemblies are then stacked into unlimitedly larger macro-assemblies.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: July 25, 2017
    Inventor: Richard Down Newberry
  • Patent number: 9711394
    Abstract: A method for fabricating a semiconductor device includes the following steps: providing a substrate having an epitaxial layer, a gate structure and an interlayer dielectric thereon, where the epitaxial structure is disposed at sides of the gate structure and the interlayer dielectric covering the epitaxial structure; forming an opening in the interlayer dielectric so that the surface of the epitaxial layer is exposed from the bottom of the opening; performing a rapid thermal process in an inert environment until non-conductive material is generated on the surface of the epitaxial layer; and removing the non-conductive material.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: July 18, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Hsiang Hung, Ssu-I Fu, Chih-Kai Hsu, Wei-Chi Cheng, Jyh-Shyang Jenq