Including External Interconnections Consisting Of Multilayer Structure Of Conductive And Insulating Layers Inseparably Formed On Semiconductor Body (epo) Patents (Class 257/E23.142)

  • Patent number: 10964473
    Abstract: The coil unit includes a planar coil, a magnetic body and a capacitor module, the capacitor module has a substrate, capacitor elements mounted on the substrate, and a first connecting terminal and a second connecting terminal provided outside an element region on which capacitor elements are mounted, the first connecting terminal is provided inside a winding section as viewed in a plan view, the second connecting terminal is provided outside the winding section as viewed in a plan view, a direction in which the first connecting terminal and the second connecting terminal are connected is perpendicular to a direction in which the conductor extends in the winding section of the planar coil, the coil unit in which the element region is provided in a range overlapping the winding section of the coil as viewed in a plan view is selected.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: March 30, 2021
    Assignee: TDK CORPORATION
    Inventors: Takuya Murashige, Shoma Asai, Masahide Ohnishi
  • Patent number: 10259078
    Abstract: Methods and systems for laser etching substrates to fine tune antennas for wireless communication are provided. A method includes laser etching an antenna element design into a substrate material. The antenna element design is for receiving conductive material to form an antenna structure. The method also includes laser etching a first area of the substrate material to change an intrinsic property of the substrate material in order to control an electrical characteristic of the antenna structure.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: April 16, 2019
    Assignee: MOTOROLA MOBILITY LLC
    Inventors: Istvan J Szini, Aiman Shibli
  • Patent number: 9972827
    Abstract: The method for producing a stack of films provided with at least one 3D-structured pattern including providing a first mold having a textured front face including a first 3D pattern, depositing a first layer of the stack on the textured front face so as to cover the first 3D pattern by a continuous layer, the first layer having a first face in contact with the front face of the mold, removing the first mold so as to release the first face of the first layer having a second 3D pattern complementary to the first 3D pattern and depositing a second layer of the stack on the first face of the first layer so as to cover the second 3D pattern by a continuous layer.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: May 15, 2018
    Assignees: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Hélène Porthault, Frédéric Le Cras, Sylvain Franger
  • Patent number: 9613903
    Abstract: A hard mask is disposed over a base material, and an I-shaped first opening is disposed in the hard mask. The first opening includes two parallel portions and a connecting portion interconnecting the two parallel portions. Spacers are formed on sidewalls of the first opening. The spacers fill an entirety of the connecting portion, wherein a center portion of each of the two parallel portions is unfilled by the spacers. The hard mask is etched to remove a portion of the hard mask and to form a second opening, wherein the second opening is between the two parallel portions of the first opening. The second opening is spaced apart from the two parallel portions of the first opening by the spacers. The first opening and the second opening are then extended down into the base material.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: April 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • Patent number: 9041187
    Abstract: A semiconductor package that includes a substrate having a metallic back plate, an insulation body and a plurality of conductive pads on the insulation body, and a semiconductor die coupled to said conductive pads, the conductive pads including regions readied for direct connection to pads external to the package using a conductive adhesive.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: May 26, 2015
    Assignee: International Rectifier Corporation
    Inventor: Martin Standing
  • Patent number: 9035372
    Abstract: A nonvolatile memory device includes (i) a semiconductor substrate, (ii) a channel formed over the substrate and extending in a first direction, (iii) a first NAND string arranged over a lower portion of a sidewall of the channel, (iv) a second NAND string arranged over an upper portion of the sidewall of the channel, and (v) an erasing conductive layer provided between the first and the second NAND strings and coupled to the sidewall of the channel.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: May 19, 2015
    Assignees: SK HYNIX INC., INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY
    Inventor: Yun Hevb Song
  • Patent number: 9018750
    Abstract: Disclosed is a package that includes a wafer substrate and a metal stack seed layer. The metal stack seed layer includes a titanium thin film outer layer. A resist layer is provided in contact with the titanium thin film outer layer of the metal stack seed layer, the resist layer forming circuitry. A method for manufacturing a package is further disclosed. A metal stack seed layer having a titanium thin film outer layer is formed. A resist layer is formed so as to be in contact with the titanium thin film outer layer of the metal stack seed layer, and circuitry is formed from the resist layer.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: April 28, 2015
    Assignee: Flipchip International, LLC
    Inventors: Robert Forcier, Douglas Scott
  • Patent number: 9006098
    Abstract: A method of improving electrical interconnections between two electrical elements is made available by providing a meta-material overlay in conjunction with the electrical interconnection. The meta-material overlay is designed to make the electrical signal propagating via the electrical interconnection to act as though the permittivity and permeability of the dielectric medium within which the electrical interconnection is formed are different than the real component permittivity and permeability of the dielectric medium surrounding the electrical interconnection. In some instances the permittivity and permeability resulting from the meta-material cause the signal to propagate as if the permittivity and permeability have negative values. Accordingly the method provides for electrical interconnections possessing enhanced control and stability of impedance, reduced noise, and reduced loss.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Christopher Wyland
  • Patent number: 9006804
    Abstract: A method for fabricating a semiconductor device is provided herein and includes the following steps. First, a first interlayer dielectric is formed on a substrate. Then, a gate electrode is formed on the substrate, wherein a periphery of the gate electrode is surrounded by the first interlayer dielectric. Afterwards, a patterned mask layer is formed on the gate electrode, wherein a bottom surface of the patterned mask layer is leveled with a top surface of the first interlayer dielectric. A second interlayer dielectric is then formed to cover a top surface and each side surface of the patterned mask layer. Finally, a self-aligned contact structure is formed in the first interlayer dielectric and the second interlayer dielectric.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: April 14, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Po-Chao Tsao, Shih-Fang Tzou
  • Patent number: 9000601
    Abstract: The respective main electrodes of the semiconductor switching elements such as IGBTs, which are respectively mounted on the plurality of insulating boards, are electrically connected to each other via the conductor member. This configuration makes it possible to suppress the occurrence of the resonant voltage due to the junction capacity and the parasitic inductance of each semiconductor switching element.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: April 7, 2015
    Assignee: Hitachi Power Semiconductor Device, Ltd.
    Inventors: Katsunori Azuma, Kentaro Yasuda, Takahiro Fujita, Katsuaki Saito, Yoshihiko Koike, Michiaki Hiyoshi
  • Patent number: 8999842
    Abstract: A method of manufacturing a semiconductor device with a cap layer for a copper interconnect structure formed in a dielectric layer is provided. In an embodiment, a conductive material is embedded within a dielectric layer, the conductive material comprising a first material and having either a recess, a convex surface, or is planar. The conductive material is silicided to form an alloy layer. The alloy layer comprises the first material and a second material of germanium, arsenic, tungsten, or gallium.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang
  • Patent number: 8994188
    Abstract: A device for use with integrated circuits is provided. The device includes a substrate having a through-substrate via formed therethrough. Dielectric layers are formed over at least one side of the substrate and metallization layers are formed within the dielectric layers. A first metallization layer closest to the through-substrate via is larger than one or more overlying metallization layers. In an embodiment, a top metallization layer is larger than one or more underlying metallization layers. Integrated circuit dies may be attached to the substrate on either or both sides of the substrate, and either side of the substrate may be attached to another substrate, such as a printed circuit board, a high-density interconnect, a packaging substrate, an organic substrate, a laminate substrate, or the like.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Shin-Puu Jeng, Tsang-Jiuh Wu
  • Patent number: 8952521
    Abstract: In one embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A chip is disposed in the substrate. The chip includes a plurality of contact pads at the first major surface. A first antenna structure is disposed at the first major surface. A reflector is disposed at the second major surface.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: February 10, 2015
    Assignee: Infineon Technologies AG
    Inventors: Maciej Wojnowski, Walter Hartner, Ottmar Geitner, Gottfried Beer, Klaus Pressel, Mehran Pour Mousavi
  • Patent number: 8941237
    Abstract: A device includes a substrate, a semiconductor chip, first and second pads, and a first wiring layer. The substrate includes first and second surfaces. The semiconductor chip includes third and fourth surfaces. The third surface faces toward the first surface. The first and second pads are provided on the third surface. The first and second pads are connected to each other. The first wiring layer is provided on the second surface of the substrate. The first wiring layer is connected to the first pad.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: January 27, 2015
    Assignee: PS4 Luxco S.A.R.L.
    Inventors: Yu Hasegawa, Mitsuaki Katagiri
  • Patent number: 8928152
    Abstract: A semiconductor device includes a substrate having a conductive area, a first pattern formed on the substrate and having a contact hole through which the conductive area is exposed, and a contact plug in the contact hole. The contact plug includes first and second silicon layers. The first silicon layer, formed from a first compound including at least two silicon atoms, is formed in the contact hole to contact a top surface of the conductive area and a side wall of the first pattern. The second silicon layer, formed from a second compound including a number of silicon atoms less than the number of the silicon atoms of the first compound, is formed on the first silicon layer and fills a remaining space of the contact hole, the second silicon layer being spaced apart from the first pattern at an entrance of the contact hole.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: January 6, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Taek-soo Jeon, Bong-hyun Kim, Won-seok Yoo, Jae-hong Seo, Ho-kyun An, Dae-hyun Kim
  • Patent number: 8907446
    Abstract: An integrated circuit structure with a metal-to-metal capacitor and a metallic device such as a resistor, effuse, or local interconnect where the bottom plate of the capacitor and the metallic device are formed with the same material layers. A process for forming a metallic device along with a metal-to-metal capacitor with no additional manufacturing steps.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: December 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Scott R. Summerfelt, Byron L. Williams, Scott K. Montgomery, James Klawinsky, Asad M. Haider
  • Patent number: 8884417
    Abstract: Methods and apparatus are disclosed for wirelessly communicating among integrated circuits and/or functional modules within the integrated circuits. A semiconductor device fabrication operation uses a predetermined sequence of photographic and/or chemical processing steps to form one or more functional modules onto a semiconductor substrate. The functional modules are coupled to an integrated waveguide that is formed onto the semiconductor substrate and/or attached thereto to form an integrated circuit. The functional modules communicate with each other as well as to other integrated circuits using a multiple access transmission scheme via the integrated waveguide. One or more integrated circuits may be coupled to an integrated circuit carrier to form Multichip Module. The Multichip Module may be coupled to a semiconductor package to form a packaged integrated circuit.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: November 11, 2014
    Assignee: Broadcom Corporation
    Inventors: Jesus Alfonso Castaneda, Arya Reza Behzad, Ahmadreza Rofougaran, Sam Ziqun Zhao, Michael Boers
  • Patent number: 8872352
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: October 28, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kenichi Watanabe
  • Patent number: 8872353
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: October 28, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kenichi Watanabe
  • Patent number: 8872347
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: October 28, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kenichi Watanabe
  • Patent number: 8860224
    Abstract: A device includes a top metal layer; a UTM line over the top metal layer and having a first thickness; and a passivation layer over the UTM line and having a second thickness. A ratio of the second thickness to the first thickness is less than about 0.33.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: October 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wen Chen, Chuang-Han Hsieh, Kun-Yu Lin, Kuan-Chi Tsai
  • Patent number: 8853861
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: October 7, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kenichi Watanabe
  • Patent number: 8853855
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a conductive post on the substrate, the conductive post includes a vertical side; attaching an integrated circuit to the substrate; and forming an encapsulant including a molded cavity, the vertical side circumscribed by and exposed within the molded cavity from the encapsulant.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: October 7, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: KyungHoon Lee, DaeSik Choi, Sooyoung Lee
  • Patent number: 8847403
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: September 30, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kenichi Watanabe
  • Patent number: 8841187
    Abstract: Disclosed is a semiconductor device and a method for fabricating the semiconductor device. The method for fabricating the semiconductor device comprises steps of: forming a side cliff in a substrate in accordance with a gate mask pattern, the side cliff being substantially vertical to a substrate surface; forming a dielectric layer on the substrate that comprises the side cliff; etching the dielectric layer to have the dielectric layer left only on the side cliff, as a dielectric wall; and burying the side cliff by a substrate growth, the burying is performed up to a level higher than the upper end of the dielectric wall.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: September 23, 2014
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Meng Zhao
  • Patent number: 8841775
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 23, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kenichi Watanabe
  • Patent number: 8829681
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: September 9, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kenichi Watanabe
  • Patent number: 8816329
    Abstract: A radiation-emitting device for emitting electromagnetic radiation which is a mixture of at least three different partial radiations of a first, a second and a third wavelength range.
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: August 26, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Ralf Krause, Günter Schmid, Stefan Seidel
  • Patent number: 8816500
    Abstract: A semiconductor device includes a semiconductor chip including a first main face and a second main face wherein the second main face is the backside of the semiconductor chip. Further, the semiconductor device includes an electrically conductive layer, in particular an electrically conductive layer, arranged on a first region of the second main face of the semiconductor chip. Further, the semiconductor device includes a polymer structure arranged on a second region of the second main face of the semiconductor chip, wherein the second region is a peripheral region of the second main face of the semiconductor chip and the first region is adjacent to the second region.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: August 26, 2014
    Assignee: Infineon Technologies AG
    Inventors: Manfred Schneegans, Ivan Nikitin
  • Patent number: 8810025
    Abstract: The present disclosure provides a carrier substrate, a device including the carrier substrate, and a method of bonding the carrier substrate to a chip. An exemplary device includes a carrier substrate having a chip region and a periphery region, and a chip bonded to the chip region of the carrier substrate. The carrier substrate includes a reinforcement structure embedded within the periphery region.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: August 19, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wen Liu, Ching-Jung Yang, Hsien-Wei Chen, Hsin-Yu Pan, Chao-Wen Shih
  • Patent number: 8796686
    Abstract: An integrated circuit includes a seal ring structure disposed around a circuit that is disposed over a substrate. A first pad is electrically coupled with the seal ring structure. A leakage current test structure is disposed adjacent to the seal ring structure. A second pad electrically coupled with the leakage current test structure, wherein the leakage current test structure is configured to provide a leakage current test between the seal ring structure and the leakage current test structure.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: August 5, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ying Yang, Hsien-Wei Chen
  • Patent number: 8791576
    Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: July 29, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kenichi Watanabe
  • Patent number: 8786072
    Abstract: A semiconductor package that includes a substrate having a metallic back plate, an insulation body and a plurality of conductive pads on the insulation body, and a semiconductor die coupled to said conductive pads, the conductive pads including regions readied for direct connection to pads external to the package using a conductive adhesive.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: July 22, 2014
    Assignee: International Rectifier Corporation
    Inventor: Martin Standing
  • Patent number: 8779599
    Abstract: A device includes a bottom chip and an active top die bonded to the bottom chip. A dummy die is attached to the bottom chip. The dummy die is electrically insulated from the bottom chip.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: July 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Cheng-Lin Huang, Szu Wei Lu, Jui-Pin Hung, Shin-Puu Jeng, Chen-Hua Yu
  • Patent number: 8766441
    Abstract: Solder on slot connections in package on package structures. An apparatus includes a substrate having a front side surface and a back side surface; a first passivation layer disposed over at least one of the front side and back side surfaces; at least one via opening formed in the first passivation layer; a conductor layer disposed over the first passivation layer, coupled to the at least one via and forming a conductive trace on the surface of the first passivation layer; a second passivation layer formed over the conductor layer; and at least one slot opening formed in the second passivation layer and exposing a portion of the conductive trace for receiving a solder connector. In additional embodiments the substrate may be a semiconductor wafer. Methods for forming the structures are disclosed.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: July 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei Sen Chang, Ching-Wen Hsiao, Chen-Shien Chen
  • Patent number: 8759156
    Abstract: A method of producing a laminate insert package includes providing a first metal layer, printing a first dielectric layer on the first metal layer, providing a second metal layer, printing a second dielectric layer on the second metal layer, and printing a dielectric spacer layer on the first dielectric layer. At least one semiconductor chip is attached to either the first or the second metal layer. A first layer assembly comprising the first metal layer, the first dielectric layer, the dielectric spacer layer and a second layer assembly comprising the second metal layer and the second dielectric layer are brought together. The first and second layer assemblies are laminated to form a laminate insert package, whereby the at least one semiconductor chip is embedded within the laminate insert package.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: June 24, 2014
    Assignee: Infineon Technologies AG
    Inventor: Martin Standing
  • Patent number: 8735956
    Abstract: A semiconductor device and a method for manufacturing the same are disclosed. An additional spacer is formed at a lateral surface of an upper part of the bit line so that the distance of insulation films between a storage node and a neighboring storage node contact plug is increased. Accordingly, the distance between the storage node and the neighboring storage node contact is guaranteed and a bridge failure is prevented.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: May 27, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Un Hee Lee
  • Publication number: 20140124913
    Abstract: A packaging substrate, a packaged semiconductor device, a computing device and methods for forming the same are provided. In one embodiment, a packaging substrate is provided that includes a packaging structure having a chip mounting surface and a bottom surface. The packaging structure has at a plurality of conductive paths formed between the chip mounting surface and the bottom surface. The conductive paths are configured to provide electrical connection between an integrated circuit chip disposed on the chip mounting surface and the bottom surface of the packaging structure. The packaging structure has an opening formed in the chip mounting surface proximate a perimeter of the packaging structure. A stiffening microstructure is disposed in the opening and is coupled to the packaging structure.
    Type: Application
    Filed: November 2, 2012
    Publication date: May 8, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Leilei Zhang, Ron Boja, Abraham Yee, Zuhair Bokharey
  • Patent number: 8716852
    Abstract: A device includes a capping substrate bonded with a substrate structure. The substrate structure includes an integrated circuit structure. The integrated circuit structure includes a top metallic layer disposed on an outgasing prevention structure. At least one micro-electro mechanical system (MEMS) device is disposed over the top metallic layer and the outgasing prevention structure.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: May 6, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Pao Shu, Chia-Ming Hung, Wen-Chuan Tai, Hung-Sen Wang, Hsiang-Fu Chen, Alex Kalnitsky
  • Patent number: 8716871
    Abstract: A semiconductor device that includes a first metal layer component formed over a substrate. The semiconductor device includes a via formed over the first metal layer component. The via has a recessed shape. The semiconductor device includes a second metal layer component formed over the via. The semiconductor device includes a first dielectric layer component formed over the substrate. The first dielectric layer component is located adjacent to, and partially over, the first metal layer component. The first dielectric layer component contains fluorine. The semiconductor device includes a second dielectric layer component formed over the first dielectric layer component. The first dielectric layer component and the second dielectric layer component are each located adjacent to the via. The second dielectric layer component is free of fluorine.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: May 6, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Uway Tseng, Shu-Hui Su
  • Patent number: 8710661
    Abstract: Methods for planarizing layers of a material, such as a dielectric, and interconnect structures formed by the planarization methods. The method includes depositing a first dielectric layer on a top surface of multiple conductive features and on a top surface of a substrate between the conductive features. A portion of the first dielectric layer is selectively removed from the top surface of at least one of the conductive features without removing a portion the first dielectric layer that is between the conductive features. A second dielectric layer is formed on the top surface of the at least one of the conductive features and on a top surface of the first dielectric layer, and a top surface of the second dielectric layer is planarized. A layer operating as an etch stop is located between the top surface of at least one of the conductive features and the second dielectric layer.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: April 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Zhong-Xiang He, Anthony K. Stamper, Eric J. White
  • Patent number: 8698293
    Abstract: A multi-chip package comprises a first chip accommodated in a first housing and a second chip accommodated in a second housing. The first housing and the second housing are arranged in a laterally spaced-apart relationship defining a gap between the first housing and the second housing. An interconnecting structure is configured to span the gap and to electrically couple the first chip and the second chip.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: April 15, 2014
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Josef Hoeglauer, Juergen Schredl
  • Patent number: 8698296
    Abstract: The reliability of a semiconductor device is to be improved. A microcomputer chip (semiconductor chip) having a plurality of pads formed on a main surface thereof is mounted over an upper surface of a wiring substrate in an opposed state of the chip main surface to the substrate upper surface. Pads coupled to a plurality of terminals (bonding leads) formed over the substrate upper surface comprise a plurality of first pads in which a unique electric current different from the electric current flowing through other pads flows and a plurality of second pads in which an electric current common to the pads flows or does not flow. Another first pad of the first pads or one of the second pads are arranged next to the first pad. The first pads are electrically coupled to a plurality of bonding leads respectively via a plurality of bumps (first conductive members), while the second pads are bonded to the terminals via a plurality of bumps (second conductive members).
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: April 15, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Naoto Taoka, Atsushi Nakamura, Naozumi Morino, Toshikazu Ishikawa, Nobuhiro Kinoshita
  • Publication number: 20140091474
    Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravi V. Mahajan
  • Patent number: 8674516
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a first substrate; attaching vertical interconnects along a periphery of the first substrate; mounting an integrated circuit over the first substrate, the integrated circuit surrounded by the vertical interconnects; and mounting a second substrate directly on the vertical interconnects and the integrated circuit.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: March 18, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Joon Han, In Sang Yoon, JoHyun Bae
  • Patent number: 8674513
    Abstract: A device for use with integrated circuits is provided. The device includes a substrate having a through-substrate via formed therethrough. Dielectric layers are formed over at least one side of the substrate and metallization layers are formed within the dielectric layers. A first metallization layer closest to the through-substrate via is larger than one or more overlying metallization layers. In an embodiment, a top metallization layer is larger than one or more underlying metallization layers. Integrated circuit dies may be attached to the substrate on either or both sides of the substrate, and either side of the substrate may be attached to another substrate, such as a printed circuit board, a high-density interconnect, a packaging substrate, an organic substrate, a laminate substrate, or the like.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: March 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Shin-Puu Jeng, Tsang-Jiuh Wu
  • Patent number: 8670638
    Abstract: Methods and apparatus are disclosed for wirelessly communicating among integrated circuits and/or functional modules within the integrated circuits. A semiconductor device fabrication operation uses a predetermined sequence of photographic and/or chemical processing steps to form one or more functional modules onto a semiconductor substrate. The functional modules are coupled to an integrated waveguide that is formed onto the semiconductor substrate and/or attached thereto to form an integrated circuit. The functional modules communicate with each other as well as to other integrated circuits using a multiple access transmission scheme via the integrated waveguide. One or more integrated circuits may be coupled to an integrated circuit carrier to form Multichip Module. The Multichip Module may be coupled to a semiconductor package to form a packaged integrated circuit.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: March 11, 2014
    Assignee: Broadcom Corporation
    Inventors: Ahmadreza Rofougaran, Arya Reza Behzad, Sam Ziqun Zhao, Jesus Alfonso Castaneda, Michael Boers
  • Publication number: 20140061950
    Abstract: In one embodiment, an electronic memory module may be provided to couple two or more stacked memory dies. The memory module may include a first substrate that couples the first memory die in a flip chip configuration. The substrate also includes connectors to couple to a second substrate, which has a flip chip connection to a second memory die. A surface of the first substrate opposite the flip chip connection of the first memory die may include connectors to couple to the first memory die (through the first substrate) and may include connectors to couple to the second memory die (through the connectors that couple to the second substrate, and through the first substrate.
    Type: Application
    Filed: September 6, 2012
    Publication date: March 6, 2014
    Inventor: Jun Zhai
  • Patent number: 8664763
    Abstract: Disclosed herein is a semiconductor apparatus including: a first semiconductor part including a first wiring; a second semiconductor part which is adhered to the first semiconductor part and which includes a second wiring electrically connected to the first wiring; and a metallic oxide formed by a reaction between oxygen and a metallic material which reacts with oxygen more easily than hydrogen does, the metallic oxide having been diffused into a region which includes a joint interface between the first wiring and the second wiring and the inside of at least one of the first wiring and the second wiring.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: March 4, 2014
    Assignee: Sony Corporation
    Inventors: Yoshihisa Kagawa, Naoki Komai
  • Patent number: RE45507
    Abstract: An integrated circuit includes electrical components that include one or more electrical elements on one or more dielectric layers. The electrical element has a geometric shape that exceeds prescribed integrated circuit manufacturing limits in at least one dimension. To achieve compliance with foundry rules, the electrical element is fabricated to include a non-conducting region that negligibly effects the electrical characteristics. The non-conducting region includes a hole, a series of holes, a slot and/or a series of slots spaced within the electrical element at dimensions that are less than the integrated circuit manufacturing limits.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: May 5, 2015
    Assignee: Broadcom Corporation
    Inventors: Harry Contopanagos, Christos Komninakis