METHODS AND APPARATUS FOR DATA ACCESS BY A REPROGRAMMABLE CIRCUIT MODULE
In some embodiments, an apparatus includes a set of memory modules, a reprogrammable circuit module and a set of data channels. Each memory module is associated with an address translation table configured to store a set of address pairs each including a physical memory address and a logical memory address. The reprogrammable circuit module is configured to retrieve a first physical memory address associated with a first logical memory address and a second physical memory address associated with a second logical memory address. Each data channel couples the reprogrammable circuit module to at least one memory module. The reprogrammable circuit module is configured to send a first and a second query to the first and the second memory module, via a first data channel based on the first physical memory address or a second data channel based on the second physical memory address, respectively.
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Some embodiments described herein relate generally to memory systems, and, in particular, to systems and methods for accessing data from a memory system using a reprogrammable circuit module.
Some known systems for performing database searches employ an array of individual computers each programmed to perform a similar search function on one or more databases, in order to increase the speed of retrieving data from the databases. Such a scheme, however, is difficult to manage and coordinate different computers. Some other known systems use an array of disk drives connected to an array of processor units. To perform a search function, data is read from the disk drives and processed at the processor units. With this approach, large amount of data is transmitted from the disk drives to the processors, which causes a substantial latency in retrieving data.
Accordingly, a need exists for a system where high speed database searches can be performed, and particularly, improvement in speed over the existing design using disk drives can be achieved.
SUMMARYIn some embodiments, an apparatus includes a set of memory modules, a reprogrammable circuit module and a set of data channels. Each memory module is associated with an address translation table configured to store a set of address pairs each including a physical memory address and a logical memory address. The reprogrammable circuit module is configured to retrieve a first physical memory address associated with a first logical memory address and a second physical memory address associated with a second logical memory address. Each data channel couples the reprogrammable circuit module to at least one memory module. The reprogrammable circuit module is configured to send a first and a second query to the first and the second memory module, via a first data channel based on the first physical memory address or a second data channel based on the second physical memory address, respectively.
In some embodiments, an apparatus includes a set of memory modules, a reprogrammable circuit module and a set of data channels. Each memory module from the set of memory modules is associated with an address translation table configured to store a set of address pairs, where each address pair includes (1) a physical memory address associated with a physical location in a memory module from the set of memory modules and (2) a logical memory address associated with the physical memory address. The reprogrammable circuit module is configured to execute a search process based at least in part on data stored at the set of memory modules. The search process is configured to retrieve a first physical memory address associated with a first logical memory address from an address translation table associated with a first memory module from the set of memory modules, and a second physical memory address associated with a second logical memory address from an address translation table associated with a second memory module from the set of memory modules. In some embodiments, the reprogrammable circuit module is configured to randomly associate the first physical memory address with the first logical memory address and randomly associate the second physical memory address with the second logical memory address, such that the first logical memory address is adjacent to the second logical memory address while the first physical memory address is not adjacent to the second physical memory address.
Furthermore, each data channel from the set of data channels operably couples the reprogrammable circuit module to at least one memory module from the set of memory modules. The reprogrammable circuit module is configured to send, based on the search process, a first query to the first memory module via a first data channel from the set of data channels based on the first physical memory address and a second query to the second memory module via a second data channel from the set of data channels based on the second memory address. In some embodiments, the reprogrammable circuit module is configured to send the first query at substantially a same time as the second query. In some embodiments, the reprogrammable circuit module is a Field Programmable Gate Array (FPGA), and configured to be modified by a driver module. In some embodiments, each memory module from the set of memory modules is a flash memory module included in a dual in-line memory module (DIMM), and the set of memory modules are removably coupled to a Peripheral Component Interconnect Express (PCIe) card including the reprogrammable circuit module.
In some embodiments, an apparatus comprises a first reprogrammable circuit module and a memory package including a set of memory modules. The memory package is removably coupled to the first reprogrammable circuit module. Specifically, the memory package is operatively coupled to the first reprogrammable circuit module via a set of channels when in a first configuration, and physically coupled to a second reprogrammable circuit module when in a second configuration. At least one memory module from the set of memory modules is configured to store an address translation table having a set of address pairs associated with the set of memory modules. Each address pair from the set of address pairs includes (1) a physical memory address associated with a physical location in the set of memory modules and (2) a logical memory address associated with the physical memory address. In some embodiments, the memory package is a DIMM, where each memory module from the set of memory modules is a flash memory module on the DIMM. In some embodiments, the first reprogrammable circuit module is a FPGA.
Furthermore, the first reprogrammable circuit module is configured to use the set of address pairs to execute a search process via the set of channels after the memory package is moved from the second configuration to the first configuration, where the search process is substantially the same as a search process executed by the second reprogrammable circuit module when the memory package is in the second configuration. The search process executed by the first reprogrammable circuit module is configured to retrieve a physical memory address associated with a received logical memory address using the address translation table. Furthermore, in some embodiments, the first reprogrammable circuit module is configured to send a first query to a first memory module from the set of memory modules during a first time period, and send a second query to a second memory module from the set of memory modules during a second time period overlapping the first time period.
As shown in
The expansion board 100 can be any removable device that can be used to implement a FPE structure, i.e., to access and retrieve data stored in the memory package 140, and locally process the retrieved data within the expansion board 100. Specifically, reprogrammable circuit module 120 can be used to access and retrieve data from the memory modules (e.g., memory modules 161-166) included in the memory package 140 via the data channels (e.g., data channels 131-133), and then process the retrieved data within the expansion board 100. For example, the expansion board 100 can be an add-in circuit board directly coupled to a motherboard of a PC. For another example, the expansion board 100 can be a removable module connected to a processor of a computer server via an interface and/or a bus. Furthermore, the expansion board 100 can be operatively coupled to host computer 110 via for example, a high speed serial data and/or command interface over a data channel. In some embodiments, the expansion board 100 can be connected to a motherboard of host computer 110.
In some embodiments, the expansion board 100 can be a PCIe card. In such embodiments, the FPE system including reprogrammable circuit module 120, the memory package 140 and other components (not shown in
Reprogrammable circuit module 120 can be any circuit module that is capable of retrieving data from the memory package 140. In some embodiments, reprogrammable circuit module 120 can be capable of on-board processing of retrieved data. In some embodiments, reprogrammable circuit module 120 can be a FPGA. For example, reprogrammable circuit module 120 can be an Altera Stratix 4GX-530 FPGA. More specifically, reprogrammable circuit module 120 can be a FPGA consisting of a large number of logic elements and/or data-processing elements, which is programmed to retrieve data stored at memory modules in the memory package 140 and further process the retrieved data within reprogrammable circuit module 120. In other embodiments, a reprogrammable circuit module can be an application-specific integrated circuit (ASIC) or any other suitable programmable logic device (PLD), such as a programmable logic array (PLA), a programmable array logic (PAL), a complex programmable logic device (CPLD), etc.
Particularly, reprogrammable circuit module 120 can be used to perform a search function. That is, reprogrammable circuit module 120 can be configured to search specific data (e.g., a string, a term) from the data stored within the memory modules included in the memory package 140. Details of a reprogrammable circuit module being configured to perform a search function are described with respect to
In some embodiments, reprogrammable circuit module 120 includes an on-board configuration storage, such as an on-board configuration ROM (read-only memory), to store a configuration file. The configuration ROM, although not shown in
In some embodiments, reprogrammable circuit module 120 can also be configured, or “reprogrammed”, by a driver module (not shown in
As shown in
In some embodiments, each memory module contained in the memory package 140 is associated with an address translation table, which is from a set of one or more address translation tables stored in one or more memory modules contained in the memory package 140. That is, at least one memory segment unit in each memory module is associated with an entry of an address translation table stored in a memory module. For example, as shown in
In some embodiments, although not shown in
The memory package 140 can be any replaceable module that can contain one or more memory modules (e.g., memory modules 161-166) and enable the memory modules to be accessed by an on-board data-processing module (e.g., reprogrammable circuit module 120) via for example, one or more data channels (e.g., data channels 131-133). The memory package 140 is replaceable in the sense that it can be mounted onto any suitable circuit board via a suitable interface socket, or removed from the circuit board if necessary. For example, the memory package 140 can be mounted onto the expansion board 100 via a socket 150 when in a first configuration as shown in
Accordingly, the memory modules (e.g., memory modules 161-166) can be removed from the expansion board 100 containing the on-board data-processing module (e.g., reprogrammable circuit module 120) and other associated interface components (not shown in
In some embodiments, the memory package 140 can be a DIMM. In such embodiments, the SLFM design using a DIMM as a memory package can be compatible with a variety of flash memory devices as memory modules, including MLC NAND chips, SLC NAND chips, Clear NAND chips, etc. Also, a DIMM flash mounting scheme uses DIMM slot connectors to mount the flash memory devices (e.g., memory modules 161-166) onto the memory package 140, which is then coupled to the expansion board via socket 150. For example, the memory package 140 can be a DIMM with a memory of 1T bytes that contains 16 Clear NAND chips, each of which has a memory of 64G bytes. Additionally, the use of the DIMM flash mounting scheme also permits alternative types of flash memory devices to be used on the memory package 140 without re-spinning the expansion board 100, by only providing a new DIMM containing the new type of flash memory devices, and adjusting reprogrammable circuit module 120 accordingly (e.g., changing the FPGA code consistent with the state machine requirements of the new part in reprogrammable circuit module 120).
As shown in
In some embodiments, more than one memory module can be connected to reprogrammable circuit module 120 by a single data channel. For example, as shown in
Furthermore, the number of memory modules (e.g., flash memory devices) that can be supported by reprogrammable circuit module 120 (e.g., a FPGA) can be limited by the I/O pin count of reprogrammable circuit module 120, as well as the internal logic resources of reprogrammable circuit module 120 needed to support the memory modules. The internal resources include for example, logic support for generating the state machine timing signals needed to meet the flash interface requirements, data buffers needed for alignment and error correction of the transferred pages, etc. For example, a Stratix EP4S530 FPGA has 744 I/O pins, allowing for various I/O interface standards needed by the FPGA to connect flashing memory devices and other components. As a result, a Stratix EP4S530 FPGA can support as many as 33 flash memory chips (e.g., contained in one or more memory packages).
Each memory segment unit in memory module 200 can be identified by, for example, a physical memory address representing a physical location of the starting point of that memory segment unit. A physical memory address can be for example, a binary number from a finite monotonically ordered sequence of binary numbers that uniquely describes the physical location of a memory itself. For example, as shown in
In some embodiments, a memory segment unit of memory module 200 can be accessed by for example, a reprogrammable circuit module (e.g., reprogrammable circuit module 120 in
As shown in
The second column, physical memory address 320, contains physical memory addresses (e.g., 465/0x002010, 463/0x006a24, 466/0x00f92a, 461/0x00ff00), each of which uniquely identifies a physical memory location of a memory segment unit in the memory package. In some embodiments, an address translation table stored in a memory module can store physical memory addresses identifying physical memory locations within other memory modules. In such embodiments, a physical memory address stored in this address translation table can include both information associated with a hosting memory module and information identifying a physical memory location within that hosting memory module. In the example of the physical memory address “465/002010” shown in
Address translation table 300 associates each logical memory address with a physical memory address. Specifically, each logical memory address stored in the column of logical memory address 310 can be mapped to a physical memory address stored in the column of physical memory address 320. For example, logical memory address “1000” is mapped to physical memory address “465/0x002010” in the first entry of address translation table 300. For another example, logical memory address “1001” is mapped to physical memory address “463/0x006a24” in the second entry of address translation table 300.
110381 In some embodiments, the logical memory addresses can be stored in a logical order in address translation table 300, such as a monotonically-increasing order as shown in
In some embodiments, a reprogrammable circuit module can be configured to associate a physical memory address with a logical memory address stored in an address translation table. That is, the reprogrammable circuit module can be configured to assign a physical memory address to each logical memory address, and then store the pair of addresses (i.e., the physical memory address and the logical memory address) as an entry in the address translation table. Furthermore, in some embodiments, the reprogrammable circuit module can be configured to randomly assign a physical memory address to a logical memory address, such that the logical memory addresses are stored in a logical order in the address translation table, while the physical memory addresses associated with those logical memory addresses are randomly distributed across the entire available memory space provided by the memory modules, as shown in
In some embodiments, a SLFM system described with respect to
A search process can be executed by the system shown in
In some embodiments, one or more logical memory addresses associated with a searchable string or term can be determined based on the string or term. Specifically, a logical memory address is associated with a string or term in a sense that data stored in the memory segment unit represented by the logical memory address is likely to contain information associated with the string or term. Thus, to search for the string or term, data stored in the memory segment unit represented by the logical memory address needs to be searched. In some embodiments, the desired logical memory addresses can be determined at host computer 410, and then sent from host computer 410 to reprogrammable circuit module 420. In such embodiments, reprogrammable circuit module 420 is configured to receive the logical memory addresses. In some other embodiments, the desired logical memory addresses can be determined at reprogrammable circuit module 420 or another component of the system (not shown in
Next, reprogrammable circuit module 420 can be configured to send an address-translation query including the desired logical memory addresses to an address translation table stored in a memory module in the memory package 440 via a data channel. As shown in
In some embodiments, reprogrammable circuit module 420 can be configured to send more than one address-translation queries, each of which contains a different set of logical memory addresses and is destined to a different address translation table. For example, although not shown in
After an address-translation query containing a logical memory address is received at an address translation table, an entry associated with the logical memory address can be determined based on the logical memory address. Physical memory address associated with the logical memory address can be retrieved from the entry, and sent to reprogrammable circuit module 420 via a data channel. In the example of
Subsequently, reprogrammable circuit module 420 can be configured to send one or more data queries to one or more memory segment units, each of which is identified by a retrieved physical memory address associated with a logical memory address. Specifically, a data query destined to a memory segment unit in a memory module within the memory package 440 can be sent over a data channel connecting reprogrammable circuit module 420 and the memory module. Furthermore, in some embodiments, multiple data queries to different memory modules can be sent from reprogrammable circuit module 420 at substantially a same time. In other words, a first data query can be sent to a first memory module during a first time period, and a second data query can be sent to a second memory module during a second time period overlapping the first time period. Thus, sending multiple data queries or retrieving data from multiple memory modules can be performed in a substantially simultaneous fashion via multiple data channels.
In the example of
A data query sent from reprogrammable circuit module 420 to a memory segment unit in a memory module is designed to retrieve data from the memory segment unit. In some embodiments, data stored in the memory segment unit can be retrieved completely and the original data can be sent to reprogrammable circuit module 420 for further processing. In some other embodiments, data stored in the memory segment unit can be partially retrieved and sent to reprogrammable circuit module 420 for further processing, according to the data query. Further processing can include for example, search the desired string or term in the original data or processed data. Such further processing can be performed at reprogrammable circuit module 420, or alternatively, at another component of host computer 410.
In some embodiments, information of the associations between logical memory addresses and physical memory addresses with respect to memory segment units contained in a memory package can be stored in one or more address translation tables included in the memory package. In other words, the remapping information (e.g., between logical memory addresses and physical memory addresses) for a memory package can be carried by the one or more address translation tables included in the memory package. As a result, the memory package can be swapped from one circuit board to another that is suitable for the memory package, without loosing the remapping information. In the example of
In the example shown and described with respect to
Additionally, in some embodiments, an instruction can be received at the reprogrammable circuit module from a driver module operatively coupled to the reprogrammable circuit module, such that the search process can be modified based on the instruction. Such a modification can be for example, to reconfigure the reprogrammable circuit module, to update the address for an address translation table (e.g., after a new memory package is coupled to the reprogrammable circuit module), etc. In the example of
At 504, a first physical memory address associated with the first logical memory address is retrieved by the reprogrammable circuit module, where the first physical memory address is associated with a memory location at a first memory module coupled to the reprogrammable circuit module by a first data channel. Specifically, the reprogrammable circuit module can be configured to send an address-translation query including the first logical memory address to a first address translation table that includes an entry for the first logical memory address. The first address translation table is stored in a memory module operatively coupled to the reprogrammable circuit module via a data channel. As a result, the first physical memory address, which is associated with the first logical memory address (i.e., the first logical memory address and the first physical memory address are stored as a pair in an entry of the first address translation table), can be retrieved from the first address translation table and sent to the reprogrammable circuit module via the data channel. The first physical memory address identifies a memory location, such as a memory segment unit, in a first memory module that is coupled to the reprogrammable circuit module by a first data channel.
In the example of
At 506, a second physical memory address associated with the second logical memory address is retrieved by the reprogrammable circuit module, where the second physical memory address is associated with a memory location at a second memory module coupled to the reprogrammable circuit module by a second data channel. Similarly to retrieving the first physical memory address, the reprogrammable circuit module can be configured to send an address-translation query including the second logical memory address to a second address translation table that includes an entry for the second logical memory address. In some embodiments, the second address translation table can be the same as the first address translation table, and thus the second logical memory address can be included in the same address-translation query for the first logical memory address. In some other embodiments, the entry for the second logical memory address is stored in a different address-translation table from that for the first logical memory address, and therefore, a separate address-translation query including the second logical memory address is sent to the second address-translation table, which is probably stored in a different memory module from that for the first address-translation table. As a result, the second physical memory address, which is associated with the second logical memory address (i.e., the second logical memory address and the second physical memory address are stored as a pair in an entry of the second address translation table), can be retrieved from the second address translation table and sent to the reprogrammable circuit module via the data channel. Similar to the first physical memory address, the second physical memory address identifies a memory location, such as a memory segment unit, in a second memory module that is coupled to the reprogrammable circuit module by a second data channel. In some embodiments, the second memory module can be different than the first memory module. In some embodiments, both the first memory module and the second memory module can be included within a common memory package, such as a common DIMM.
In the example of
At 508, the first memory module is accessed, during a first time period, by the reprogrammable circuit module via the first data channel using the first physical memory address. Specifically, based on the first physical memory address retrieved from the address translation table, the reprogrammable circuit module can be configured to locate and access the memory segment unit identified by the first physical memory address, which is included in the first memory module. Particularly, the reprogrammable circuit module can be configured to send a data query to the memory segment unit identified by the first physical memory address via the first data channel. As a result, data can be retrieved, during the first time period, from the memory segment unit identified by the first physical memory address.
In the example of
At 510, the second memory module is accessed, during a second time period overlapping the first time period, by the reprogrammable circuit module via the second data channel using the second physical memory address. Similar to the case for the first physical memory address, the reprogrammable circuit module can be configured to send a data query to the memory segment unit identified by the second physical memory address, which is included in the second memory module, via the second data channel. As a result, data can be retrieved, during the second time period, from the memory segment unit identified by the second physical memory address. Furthermore, because the first memory module and the second memory module are two different memory modules, and the first data channel and the second data channel are two separate data channels, the operation of retrieving data from the first memory module and the operation of retrieving data from the second memory module are independent, therefore can be executed in parallel. Thus, the first time period can be overlapping the second time period.
In the example of
While various embodiments have been described above, it should be understood that they have been presented by way of example only, not limitation, and various changes in form and details may be made. Any portion of the apparatus and/or methods described herein may be combined in any combination, except mutually exclusive combinations. The embodiments described herein can include various combinations and/or sub-combinations of the functions, components and/or features of the different embodiments described.
While shown and described above with respect to
While shown and described above with respect to
Some embodiments described herein relate to a computer storage product with a computer-readable medium (also can be referred to as a processor-readable medium) having instructions or computer code thereon for performing various computer-implemented operations. The media and computer code (also can be referred to as code) may be those designed and constructed for the specific purpose or purposes. Examples of computer-readable media include, but are not limited to: magnetic storage media such as hard disks, floppy disks, and magnetic tape; optical storage media such as Compact Disc/Digital Video Discs (CD/DVDs), Compact Disc-Read Only Memories (CD-ROMs), and holographic devices; magneto-optical storage media such as optical disks; carrier wave signal processing modules; and hardware devices that are specially configured to store and execute program code, such as Application-Specific Integrated Circuits (ASICs), Programmable Logic Devices (PLDs), and read-only memory (ROM) and RAM devices.
Claims
1. An apparatus, comprising:
- a plurality of memory modules, each memory module from the plurality of memory modules being associated with an address translation table configured to store a plurality of address pairs, each address pair from the plurality of address pairs including (1) a physical memory address associated with a physical location in a memory module from the plurality of memory modules and (2) a logical memory address associated with the physical memory address;
- a reprogrammable circuit module configured to execute a search process based at least in part on data stored at the plurality of memory modules, the search process configured to retrieve a first physical memory address associated with a first logical memory address from an address translation table associated with a first memory module from the plurality of memory modules and a second physical memory address associated with a second logical memory address from an address translation table associated with a second memory module from the plurality of memory modules; and
- a plurality of data channels, each data channel from the plurality of data channels operably coupling the reprogrammable circuit module to at least one memory module from the plurality of memory modules, the reprogrammable circuit module configured to send, based on the search process, a first query to the first memory module via a first data channel from the plurality of data channels based on the first physical memory address and a second query to the second memory module via a second data channel from the plurality of data channels based on the second memory address.
2. The apparatus of claim 1, wherein each memory module from the plurality of memory modules is included in a dual in-line memory module (DIMM).
3. The apparatus of claim 1, wherein the reprogrammable circuit module is configured to randomly associate the first physical memory address with the first logical memory address.
4. The apparatus of claim 1, wherein the first logical memory address is adjacent to the second logical memory address, the first physical memory address not adjacent to the second physical memory address.
5. The apparatus of claim 1, wherein the reprogrammable circuit module is configured to send the first query at substantially a same time as the second query.
6. The apparatus of claim 1, wherein the reprogrammable circuit module is a Field Programmable Gate Array (FPGA).
7. The apparatus of claim 1, wherein each memory module from the plurality of memory modules is a flash memory module.
8. The apparatus of claim 1, wherein the reprogrammable circuit module is configured to be modified by a driver module.
9. The apparatus of claim 1, wherein the plurality of memory modules are removably coupled to a Peripheral Component Interconnect Express (PCIe) card including the reprogrammable circuit module.
10. A method, comprising:
- receiving a query associated with a data lookup, the query including a first logical memory address and a second logical memory address;
- retrieving a first physical memory address associated with the first logical memory address, the first physical memory address being associated with a memory location at a first memory module coupled to a reprogrammable circuit module by a first data channel;
- retrieving a second physical memory address associated with the second logical memory address, the second physical memory address being associated with a memory location at a second memory module coupled to the reprogrammable circuit module by a second data channel;
- accessing, during a first time period, the first memory module via the first data channel using the first physical memory address; and
- accessing, at a second time period overlapping the first time period, the second memory module via the second data channel using the second physical memory address.
11. The method of claim 10, wherein the retrieving the first physical memory address includes retrieving the first physical memory address from a first address translation table, the retrieving the second physical memory address includes retrieving the second physical memory address from a second address translation table.
12. The method of claim 10, wherein the retrieving the first physical memory address includes retrieving the first physical memory address from an address translation table stored at the first memory module.
13. The method of claim 10, wherein the first memory module is included within a common dual in-line memory module (DIMM) as the second memory module.
14. The apparatus of claim 10, wherein the first memory module is a flash memory module.
15. The method of claim 10, wherein the accessing the first memory module and the accessing the second memory module are associated with a search process, the method further comprising:
- receiving an instruction from a driver associated with the reprogrammable circuit module to modify the search process.
16. An apparatus, comprising:
- a first reprogrammable circuit module; and
- a memory package including a plurality of memory modules, the memory package being removably coupled to the first reprogrammable circuit module such that the memory package is physically coupled to the first reprogrammable circuit module when in a first configuration and physically coupled to a second reprogrammable circuit module when in a second configuration,
- the memory package being operatively coupled to the first reprogrammable circuit module via a plurality of channels when in the first configuration,
- at least one memory module from the plurality of memory modules configured to store an address translation table having a plurality of address pairs associated with the plurality of memory modules, each address pair from the plurality of address pairs including (1) a physical memory address associated with a physical location in the plurality of memory modules and (2) a logical memory address associated with the physical memory address,
- the first reprogrammable circuit module configured to use the plurality of address pairs to execute a search process via the plurality of channels after the memory package is moved from the second configuration to the first configuration, wherein the search process is substantially the same as a search process executed by the second reprogrammable circuit module when the memory package is in the second configuration.
17. The apparatus of claim 16, wherein the memory package is a dual in-line memory module (DIMM), each memory module from the plurality of memory modules being a flash memory module.
18. The apparatus of claim 16, wherein the first reprogrammable circuit module is a Field Programmable Gate Array (FPGA).
19. The apparatus of claim 16, wherein the search process executed by the first reprogrammable circuit module is configured to retrieve a physical memory address associated with a received logical memory address using the address translation table.
20. The apparatus of claim 16, wherein the first reprogrammable circuit module is configured to send a first query to a first memory module from the plurality of memory modules during a first time period, the first reprogrammable circuit module configured to send a second query to a second memory module from the plurality of memory modules during a second time period overlapping the first time period.
Type: Application
Filed: Jun 15, 2011
Publication Date: Dec 20, 2012
Applicant: Data Design Corporation (Gaithersburg, MD)
Inventors: John J. Giganti (Damascus, MD), Andrew Huo (Rockville, MD), Richard A. Baum (Rockville, MD), John M. Cavallo (Beltsville, MD)
Application Number: 13/161,141
International Classification: G06F 12/10 (20060101);