Abstract: Superconducting tunnel junctions for use in, for instance, quantum processors are provided. In one example, a method can include forming a first superconducting layer on a substrate, the first superconducting layer comprising aluminum. The method can include forming a dielectric layer on the first superconducting layer. The method can include forming a trench structure in the dielectric layer. The method can include forming a crystalline dielectric layer having a spinel crystal structure in the trench structure. The method can include forming a second superconducting layer on the crystalline dielectric layer.

Abstract: A first metal layer extends across memory and logic device regions of a semiconductor structure. A dielectric barrier layer is disposed over the first metal layer. A first dielectric layer is disposed over the dielectric barrier layer in the memory device region and not in the logic device region. Multiple magnetic tunneling junction (MTJ) devices are disposed in the memory device region. A second dielectric layer is disposed in the memory device region and not in the logic device region. The second dielectric layer is disposed over the first dielectric layer and the MTJ devices. An extreme low-k dielectric layer is disposed over the dielectric barrier layer in the logic device region. A conductive feature in the logic device region penetrates the extreme low-k dielectric layer and the dielectric barrier layer to electrically connect to the first metal layer.

Abstract: A magnetoresistive random access memory device includes a pinned layer; a tunnel barrier layer on the pinned layer; a free layer structure on the tunnel barrier layer, the free layer structure including a plurality of magnetic layers and a plurality of metal insertion layers between the magnetic layers; and an upper oxide layer on the free layer structure, wherein each of the metal insertion layers includes a non-magnetic metal material doped with a magnetic material, and the metal insertion layers are spaced apart from each other.

Abstract: An antiferromagnetic (AFM) memory device includes a heavy metal (HM) layer having electrical terminals at two ends, and an AFM tunnel junction (ATJ) interfaced with the HM layer between the two ends. The ATJ includes an AFM material interfaced with a surface of the HM layer, a tunnel barrier layer including an oxide and interfaced with a top of the AFM layer, and a capping layer interfaced with a top of the tunnel barrier layer. The capping layer includes a heavy metal material or a ferromagnetic material. An electrode disposed on top of the capping layer facilitates reading information from the AFM memory device according to a magnetoresistance value measured between the electrode and one of the terminals of the HM layer. Information is written into the AFM memory device by passing current through the HM layer and below the AFM layer.

Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a MTJ on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes a stripe pattern according to a top view and the blocking layer could include metal or a dielectric layer.

Abstract: A magnetic memory element including first and second magnetic free layers having a variable magnetization direction substantially perpendicular to layer planes thereof; a first perpendicular enhancement layer (PEL) interposed between the first and second magnetic free layers; first and second magnetic reference layers having a first invariable magnetization direction substantially perpendicular to layer planes thereof; a second PEL interposed between the first and second magnetic reference layers; an insulating tunnel junction layer formed between the first magnetic free layer and reference layer; an anti-ferromagnetic coupling layer formed adjacent to the second magnetic reference layer; a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer and having a second invariable magnetization direction substantially opposite to the first invariable magnetization direction; a non-magnetic layer comprising oxygen and a transition metal and formed adjacent to the second magnetic free layer; an

Abstract: A method of fabricating magnetoresistive random access memory, including providing a substrate, forming a bottom electrode layer, a magnetic tunnel junction stack, a top electrode layer and a hard mask layer sequentially on the substrate, wherein a material of the top electrode layer is titanium nitride, a material of the hard mask layer is tantalum or tantalum nitride, and a percentage of nitrogen in the titanium nitride gradually decreases from a top surface of top electrode layer to a bottom surface of top electrode layer, and patterning the bottom electrode layer, the magnetic tunnel junction stack, the top electrode layer and the hard mask layer into multiple magnetoresistive random access memory cells.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.

Abstract: A magnetic memory device includes a first fixed layer maintaining a particular magnetization direction, a first non-magnetic layer, a free layer having perpendicular magnetic anisotropy and a variable magnetization direction, a second non-magnetic layer, and a second fixed layer maintaining a separate particular magnetization direction that is opposite to the particular magnetization direction of the first fixed layer. A resistance value of a first magnetic tunnel junction (MTJ) element including the first fixed layer, the first non-magnetic layer, and the free layer is different from that of a second MTJ element that includes the second fixed layer, the second non-magnetic layer, and the free layer, based on a first portion of the free layer in the first MTJ and a second portion of the free layer in the second MTJ being separated by a domain wall.

Abstract: A device includes a spin orbit coupling layer and a Magnetic Tunnel Junction (MTJ) stack. The MTJ stack includes a dielectric layer over the spin orbit coupling layer, a free layer over the dielectric layer, a tunnel barrier layer over the free laver, and a reference layer over the tunnel barrier layer. The spin orbit coupling layer extends beyond edges of the MTJ stack in a first direction and a second direction opposite to the first direction.

Abstract: Provided is a semiconductor structure, a memory cell and a memory array. An nT-MRAM can be realized by a relatively simple structure. Transistors connected to multiple MTJs are connected by connecting pads.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a device substrate, a resistance variable layer and a top electrode. The bottom electrode is disposed on the device substrate. The resistance variable layer is disposed on the bottom electrode. The top electrode is disposed on the resistance variable layer. The bottom electrode is formed with a tensile stress, while the top electrode is formed with a compressive stress.

Abstract: Disclosed are examples of multiple bit magnetoresistive random access memory (MRAM) cells. A multiple bit MRAM cell may comprise a fixed layer, alternately stacked N tunnel barriers and N free layers, and a tunnel cap. N, which may represent number of bits of the MRAM cell, may be greater than or equal to two. Magnetic moment of the fixed layer may be fixed in one perpendicular direction. Magnetic moments of the free layers may be switchable from one to other perpendicular directions upon application of switch currents. The switch currents may be different for different layers. The magnetic moments of the free layers may be switched separately or otherwise independently of other free layers when the switch currents are applied separately.

Abstract: A method of making an integrated circuit includes depositing a first ferromagnetic material over a substrate. The method includes applying a first magnetic field to the first ferromagnetic material. The method includes annealing the first ferromagnetic material while applying the first magnetic field to the first ferromagnetic material to set a magnetic field orientation in the first ferromagnetic material. The method includes depositing barrier material over the first ferromagnetic material. The method includes depositing a second ferromagnetic material over the barrier material. The method includes depositing an antiferromagnetic material over the second ferromagnetic material.

Abstract: This spin current magnetization rotational type magnetoresistive element includes a magnetoresistive effect element having a first ferromagnetic metal layer having a fixed magnetization orientation, a second ferromagnetic metal layer having a variable magnetization orientation, and a non-magnetic layer sandwiched between the first ferromagnetic metal layer and the second ferromagnetic metal layer, and spin-orbit torque wiring which extends in a direction that intersects the stacking direction of the magnetoresistive effect element, and is connected to the second ferromagnetic metal layer, wherein the electric current that flows through the magnetoresistive effect element and the electric current that flows through the spin-orbit torque wiring merge or are distributed in the portion where the magnetoresistive effect element and the spin-orbit torque wiring are connected.

Abstract: A semiconductor structure and a fabrication method of the semiconductor structure are provided in the present disclosure. The semiconductor structure includes a base substrate, a bottom electrode layer on the substrate, a magnetic tunnel junction layer on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction layer. An opening is formed at least exposing a portion of one of an upper surface and a lower surface of the magnetic tunnel junction layer.

Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region and a second cell region and a diffusion region on the substrate extending through the first cell region and the second cell region. Preferably, the diffusion region includes a first H-shape and a second H-shape according to a top view.

Abstract: A magnetic cell includes a magnetic region formed from a precursor magnetic material comprising a diffusive species and at least one other species. An amorphous region is proximate to the magnetic region and is formed from a precursor trap material comprising at least one attractor species having at least one trap site and a chemical affinity for the diffusive species. The diffusive species is transferred from the precursor magnetic material to the precursor trap material where it bonds to the at least one attractor species at the trap sites. The species of the enriched trap material may intermix such that the enriched trap material becomes or stays amorphous. The depleted magnetic material may then be crystallized through propagation from a neighboring crystalline material without interference from the amorphous, enriched trap material. This enables high tunnel magnetoresistance and high magnetic anisotropy strength. Methods of fabrication and semiconductor devices are also disclosed.

Abstract: A magnetic cell core includes a seed region with a plurality of magnetic regions and a plurality of nonmagnetic regions thereover. The seed region provides a template that enables formation of an overlying nonmagnetic region with a microstructure that enables formation of an overlying free region with a desired crystal structure. The free region is disposed between two nonmagnetic regions, which may both be configured to induce surface/interface magnetic anisotropy. The structure is therefore configured to have a high magnetic anisotropy strength, a high energy barrier ratio, high tunnel magnetoresistance, a low programming current, low cell-to-cell electrical resistance variation, and low cell-to-cell variation in magnetic properties. Methods of fabrication, memory arrays, memory systems, and electronic systems are also disclosed.

Abstract: A method for forming a semiconductor structure is provided. The method includes providing a substrate, where the substrate includes a conductive layer therein, and a surface of the substrate exposes a surface of the conductive layer; forming a groove adjacent to the conductive layer in the substrate, where the groove exposes a portion of a sidewall surface of the conductive layer; and forming a lower electrode layer in the groove and on a top surface of the conductive layer.

Abstract: A device package includes a die that includes a substrate having first and second surfaces. A sensor is formed at a sensor region of the first surface. A trench extends entirely through the substrate between the first and second surfaces, in which the trench at least partially surrounds the sensor region. An isolation material, formed at the first surface, may extend across the trench A ring structure is coupled to the first surface of the substrate to create a first cavity in which the sensor is contained, the ring structure being laterally displaced away from and surrounding the sensor region and the trench. A molded compound body may abut an outer wall of the ring structure. The molded compound body has a second cavity that is concentric with the first cavity to enable fluid communication between the sensor and an environment external to the device package.

Abstract: A magnetic memory device including a magnetic tunnel junction is provided. The magnetic tunnel junction includes a fixed layer, a polarization enhancement structure on the fixed layer, a tunnel barrier layer on the polarization enhancement structure, and a free layer on the tunnel barrier layer, wherein the polarization enhancement structure includes a plurality of polarization enhancement layers and at least one spacer layer which separates the plurality of polarization enhancement layers from each other. A thickness of each of the plurality of polarization enhancement layers is from 5 ? to about 20 ?, and a thickness of the at least one spacer layer is from about 2 ? to about 15 ?.

Abstract: A conductive via layer is deposited on a bottom electrode, then patterned and trimmed to form a sub 20 nm conductive via on the bottom electrode. The conductive via is encapsulated with a first dielectric layer, which is planarized to expose a top surface of the conductive via. A MTJ stack is deposited on the encapsulated conductive via wherein the MTJ stack comprises at least a pinned layer, a barrier layer, and a free layer. A top electrode layer is deposited on the MTJ stack and patterned and trimmed to form a sub 30 nm hard mask. The MTJ stack is etched using the hard mask to form an MTJ device and over etched into the encapsulation layer but not into the bottom electrode wherein metal re-deposition material is formed on sidewalls of the encapsulation layer underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device.

Abstract: A magnetoresistance effect element has a first ferromagnetic metal layer, a second ferromagnetic metal layer, and a tunnel barrier layer that is sandwiched between the first and second ferromagnetic metal layers, and the tunnel barrier layer has a spinel structure represented by a composition formula of AIn2Ox (0<x?4), and an A-site is a non-magnetic divalent cation which is one or more selected from a group consisting of magnesium, zinc and cadmium.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the first IMD layer; forming a bottom electrode layer and a pinned layer on the first IMD layer; forming a sacrificial layer on the pinned layer; patterning the sacrificial layer, the pinned layer, and the bottom electrode layer to form a first magnetic tunneling junction (MTJ); forming a second IMD layer around the first MTJ; removing the sacrificial layer to form a recess; forming a barrier layer and a free layer in the recess; forming a top electrode layer on the free layer; and patterning the top electrode layer and the free layer to form a second MTJ.

Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a MTJ on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes a stripe pattern according to a top view and the blocking layer could include metal or a dielectric layer.

Abstract: A semiconductor device includes a first dielectric layer, a second dielectric layer and a memory device. The second dielectric layer includes a first layer and a second layer. The memory device includes a first conductive structure under the first dielectric layer, a second conductive structure over the second dielectric layer, and a memory cell between the first and the second dielectric layers. The memory cell includes a bottom electrode via, a bottom electrode over the bottom electrode via, a top electrode over the bottom electrode, a top electrode via over the top electrode, and a MTJ between the top electrode and the bottom electrode. The second layer of the second dielectric layer surrounds sidewalls of the top electrode via entirely. The first layer of the second dielectric layer surrounds sidewalls of the bottom electrode entirely, sidewalls of the MTJ entirely, and sidewalls of the top electrode entirely.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a memory region, the memory region includes a first metal line, a magnetic tunneling junction (MTJ) over the first metal line, a cap, wherein at least a portion of the cap is above the MTJ, a first stop layer above the cap, and a first metal via being disposed over the MTJ and in direct contact with the first stop layer, and a logic region adjacent to the memory region, the logic region includes a second metal line, a third metal line over the second metal line, a second stop layer being disposed over the third metal line, and a second metal via over the third metal line.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the first IMD layer; forming a bottom electrode layer and a pinned layer on the first IMD layer; forming a sacrificial layer on the pinned layer; patterning the sacrificial layer, the pinned layer, and the bottom electrode layer to form a first magnetic tunneling junction (MTJ); forming a second IMD layer around the first MTJ; and removing the sacrificial layer.

Abstract: A package includes a first die that includes a first metallization layer, one or more first bond pad vias on the first metallization layer, wherein a first barrier layer extends across the first metallization layer between each first bond pad via and the first metallization layer, and one or more first bond pads on the one or more first bond pad vias, wherein a second barrier layer extends across each first bond pad via between a first bond pad and the first bond pad via, and a second die including one or more second bond pads, wherein a second bond pad is bonded to a first bond pad of the first die.

Abstract: A Magnetic Tunnel Junction (MTJ) device can include a reference magnetic layer having one or more trenches disposed therein. One or more sections of a tunnel barrier layer can be disposed on the walls of the one or more trenches. One or more sections of a free magnetic layer can be disposed on the one or more sections of the tunnel barrier layer in the one or more trenches. One or more sections of a conductive layer can be disposed on the one or more sections of the free magnetic layer in the one or more trenches. One or more insulator blocks can be disposed between corresponding sections of the tunnel barrier layer, corresponding sections of the free magnetic layer and corresponding sections of the conductive layer in the one or more trenches.

Abstract: A magnetoresistive effect element includes: a first ferromagnetic layer; a second ferromagnetic layer; and a non-magnetic layer located between the first ferromagnetic layer and the second ferromagnetic layer, wherein a crystal structure of the non-magnetic layer is a spinel structure, wherein the non-magnetic layer contains Mg, Al, X, and O as elements constituting the spinel structure, and wherein the X is at least one or more elements selected from a group consisting of Ti, Pt, and W.

Abstract: An MRAM device includes a bottom electrode over a substrate, a magnetic tunnel junction (MTJ) structure on the bottom electrode, and a top electrode on the MTJ structure. The MRAM device also includes spacers on sidewalls of the top electrode and the MTJ structure, and a first dielectric layer surrounding the spacers. The MRAM device further includes a patterned etch stop layer on the first dielectric layer and the spacers. In addition, the MRAM device includes a second dielectric layer on the patterned etch stop layer, and a top electrode via embedded in the second dielectric layer and in contact with the top electrode and the patterned etch stop layer.

Abstract: A magnetoresistive stack/structure and method of manufacturing same comprising wherein the stack/structure includes a seed region, a fixed magnetic region disposed on and in contact with the seed region, a dielectric layer(s) disposed on the fixed magnetic region and a free magnetic region disposed on the dielectric layer(s). In one embodiment, the seed region comprises an alloy including nickel and chromium having (i) a thickness greater than or equal to 40 Angstroms (+/?10%) and less than or equal to 60 Angstroms (+/?10%), and (ii) a material composition or content of chromium within a range of 25-60 atomic percent (+/?10%) or 30-50 atomic percent (+/?10%).

Abstract: A device is provided that includes a semiconductor substrate on which a free magnetic element is positioned, which has first and second magnetic domains separated by a domain wall. A first magnet is positioned on the substrate near a first end of the free magnetic element, and has a first polarity and a first value of coercivity. A second magnet is positioned on the substrate near a second end of the free magnetic element, and has a second polarity, antiparallel relative to the first polarity, and a second value of coercivity different from the first value of coercivity.

Abstract: A magnetic element is disclosed wherein a composite seed layer such as TaN/Mg enhances perpendicular magnetic anisotropy (PMA) in an overlying magnetic layer that may be a reference layer, free layer, or dipole layer. The first seed layer is selected from one or more of Ta, Zr, Nb, TaN, ZrN, NbN, and Ru. The second seed layer is selected from one or more of Mg, Sr, Ti, Al, V, Hf, B, and Si. A growth promoting layer made of NiCr or an alloy thereof is inserted between the seed layer and magnetic layer. In some embodiments, a first composite seed layer/NiCr stack is formed below the reference layer, and a second composite seed layer/NiCr stack is formed between the free layer and a dipole layer. The magnetic element has thermal stability to at least 400° C.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first patterned mask on the first IMD layer, in which the first patterned mask includes a first slot extending along a first direction; forming a second patterned mask on the first patterned mask, in which the second patterned mask includes a second slot extending along a second direction and the first slot intersects the second slot to form a third slot; and forming a first metal interconnection in the third slot.

Abstract: Data storage devices are provided. A data storage device includes a memory transistor on a substrate and a data storage structure electrically connected to the memory transistor. The data storage structure includes a magnetic tunnel junction pattern and a top electrode on the magnetic tunnel junction pattern. The top electrode includes a first top electrode and a second top electrode on the first top electrode, and the first and second top electrodes include the same metal nitride. The first top electrode includes first crystal grains of the metal nitride, and the second top electrode includes second crystal grains of the metal nitride. In a section of the top electrode, the number of the first crystal grains per a unit length is greater than the number of the second crystal grains per the unit length.

Abstract: A magnetoresistance effect element has an underlayer, a first ferromagnetic metal layer, a second ferromagnetic metal layer, and a tunnel barrier layer that is sandwiched between the first and second ferromagnetic metal layers. The tunnel barrier layer has a spinel structure and includes at least one lattice-matched portion, and at least one lattice-mismatched portion. The underlayer is made of a nitride layer; a layer having a (001)-oriented tetragonal or cubic structure; or a layer having a stacked structure with a combination of a nitride layer having a (001)-oriented NaCl structure and a layer having a (001)-oriented tetragonal or cubic structure.

Abstract: A tunnel barrier layer includes a non-magnetic oxide, wherein a crystal structure of the tunnel barrier layer includes both an ordered spinel structure and a disordered spinel structure.

Abstract: A magnetoresistive effect element includes: a first ferromagnetic layer; a second ferromagnetic layer; and a non-magnetic layer provided between the first ferromagnetic layer and the second ferromagnetic layer, wherein the non-magnetic layer includes a first layer and a second layer, and wherein a lattice constant ? of the first layer and a lattice constant ? of the second layer satisfy a relationship of ??0.04×??2×???+0.04×?.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a transistor layer, a memory region over the transistor layer, and a logic region adjacent to the memory region. The memory region includes a first Nth metal line, a magnetic tunneling junction (MTJ) over the first Nth metal line, a cap over the MTJ, a first stop layer on the cap, and a first (N+1)th metal via over the MTJ. The first (N+1)th metal via is laterally surrounded by the cap and the first stop layer. The logic region includes a second Nth metal line, a second stop layer over an (N+1)th metal line, and a second (N+1)th metal via over the (N+1)th metal line. N is an integer greater than or equal to 1.

Abstract: A magnetic tunnel junction with perpendicular magnetic anisotropy (PMA MTJ) is disclosed wherein a free layer interfaces with a tunnel barrier and has a second interface with an oxide layer. A lattice-matching layer adjoins an opposite side of the oxide layer with respect to the free layer and is comprised of CoXFeYNiZLWMV or an oxide or nitride of Ru, Ta, Ti, or Si, wherein L is one of B, Zr, Nb, Hf, Mo, Cu, Cr, Mg, Ta, Ti, Au, Ag, or P, and M is one of Mo, Mg, Ta, Cr, W, or V, (x+y+z+w+v)=100 atomic %, x+y>0, and each of v and w are >0. The lattice-matching layer grows a BCC structure during annealing thereby promoting BCC structure growth in the oxide layer that results in enhanced free layer PMA and improved thermal stability.

Abstract: An apparatus for generation of tunable terahertz radiation is provided. The apparatus comprises: a plurality of terahertz magnon laser generators, whereas at least one such terahertz magnon laser generator comprises a multilayer column, and a terahertz transparent medium separating at least two such terahertz magnon laser generators. At least one such multilayer column further comprises: a substrate, a bottom electrode coupled with the substrate, a bottom layer coupled with the bottom electrode, a tunnel junction coupled with the bottom layer, a top layer coupled with the tunnel junction, a pinning layer coupled with the spin injector, and a top electrode coupled with the pinning layer.

Abstract: A magnetic memory structure that includes a two-terminal resistive memory element electrically connected with a selector structure. The selector structure includes a semiconductor pillar structure formed on a semiconductor substrate. The selector structure is surrounded by a gate dielectric layer, and the semiconductor pillar structure and gate dielectric layer are surrounded by an electrically conductive gate structure. The semiconductor pillar has first and second dimensions in a plane parallel with the surface of the semiconductor substrate that are unequal with one another. The semiconductor pillar structure can have a cross-section parallel with the semiconductor substrate surface that is in the shape of a: rectangle; oval elongated polygon, etc. The length of the longer dimension can be adjusted to provide a desired amount of current though the semiconductor pillar structure to drive the two-terminal resistive memory element.

Abstract: A method includes depositing a plurality of layers, which includes depositing a spin orbit coupling layer, depositing a dielectric layer over the spin orbit coupling layer, depositing a free layer over the dielectric layer, depositing a tunnel barrier layer over the free layer, and depositing a reference layer over the tunnel barrier layer. The method further includes performing a first patterning process to pattern the plurality of layers, and performing a second patterning process to pattern the reference layer, the tunnel barrier layer, the free layer, and the dielectric layer. The second patterning process stops on a top surface of the spin orbit coupling layer.

Abstract: A first magnetic member is provided in a region farther inward than an outer peripheral edge of a first magnetoresistance element. A second magnetoresistance element is provided in a region farther inward than an inner peripheral edge of the first magnetoresistance element and is covered by the first magnetic member or is provided in a region farther outward than the outer peripheral edge of the first magnetoresistance element and is covered by a second magnetic member. A first conductor includes a first base section and a first narrow section. The area of the exterior surface of the first narrow section as viewed from a direction perpendicular to an insulating layer is smaller than that of the first base section. In the first conductor, the first base section and the first narrow section are arranged side by side in the direction perpendicular to the insulating layer.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, forming a magnetic tunneling junction (MTJ) on the MRAM region, forming a metal interconnection on the MTJ, forming a dielectric layer on the metal interconnection, patterning the dielectric layer to form openings, and forming the blocking layer on the patterned dielectric layer and the metal interconnection and into the openings.

Abstract: A magnetoresistive element comprises a novel iPMA cap layer on a surface of a recording layer to induce a giant interfacial perpendicular magnetic anisotropy (G-iPMA) of the recording layer and a method of making the same. The recording layer comprises a first free layer immediately contacting to the tunnel barrier layer and having a body-centered cubic structure with a (100) texture, and a second free layer having a body-centered cubic structure with a (110) texture or a face-centered cubic structure with a (111) texture, and a crystal-breaking layer inserted between the first free layer and the second free layer.

Abstract: A first conductive layer is patterned and trimmed to form a sub 30 nm conductive via on a first bottom electrode. The conductive via is encapsulated with a first dielectric layer and planarized to expose a top surface of the conductive via. A second conductive layer is deposited over the first dielectric layer and the conductive via. The second conductive layer is patterned to form a sub 60 nm second conductive layer wherein the conductive via and second conductive layer together form a T-shaped second bottom electrode. MTJ stacks are deposited on the T-shaped second bottom electrode and on the first bottom electrode wherein the MTJ stacks are discontinuous. A second dielectric layer is deposited over the MTJ stacks and planarized to expose a top surface of the MTJ stack on the T-shaped second bottom electrode. A top electrode contacts the MTJ stack on the T-shaped second bottom electrode plug.