Controllable By Variation Of Magnetic Field Applied To Device (epo) Patents (Class 257/E29.323)
  • Patent number: 10310029
    Abstract: A method for determining a magnetic field of a magnet along a surface of the magnet, the method comprising: performing a relative movement between the surface of the magnet and a magnetic camera device; measuring the magnetic field by means of the magnetic camera device, to thereby obtain magnetic field measurements for the surface; wherein the relative movement is a continuous movement which is a combination of a relative translational movement and a relative rotational movement; and apparatus.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: June 4, 2019
    Assignee: MAGCAM NV
    Inventors: Koen Vervaeke, Stephan Kliché
  • Patent number: 9831419
    Abstract: A magneto-resistive (MR) device and process for making the MR device are disclosed. The MR device has a pinned layer, a spacer layer proximate to the pinned layer, and a free layer proximate to the spacer layer. The free layer comprises a first magnetic layer proximate to the spacer layer, the first magnetic layer having a positive magnetostriction, a laminate magnetic insertion layer proximate to the first magnetic layer, and a second magnetic layer proximate to the magnetic insertion layer, the second magnetic layer having a negative magnetostriction. The laminate magnetic insertion layer has a first magnetic sublayer and a first non-magnetic sublayer proximate to the first magnetic sublayer. With the disclosed laminate magnetic insertion layer, the free layer has a low overall magnetostriction and results in a MR device with a high MR ratio.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: November 28, 2017
    Assignee: Western Digital Technologies, Inc.
    Inventors: James Freitag, Zheng Gao
  • Patent number: 9034679
    Abstract: A method entails providing a substrate with a structural layer having a thickness. A partial etch process is performed at locations on the structural layer so that a portion of the structural layer remains at the locations. An oxidation process is performed at the locations which consumes the remaining portion of the structural layer and forms an oxide having a thickness that is similar to the thickness of the structural layer. The oxide electrically isolates microstructures in the structural layer, thus producing a structure. A device substrate is coupled to the structure such that a cavity is formed between them. An active region is formed in the device substrate. A short etch process can be performed to expose the microstructures from an overlying oxide layer.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: May 19, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Lianjun Liu
  • Patent number: 9029964
    Abstract: A method for manufacturing a semiconductor device includes forming plural layers of a MTJ device, depositing a conductive layer over the plural layers, forming a hard mask pattern used for patterning the plural layers over the conductive layer, where the conductive layer is exposed through the hard mask pattern, performing hydrogen peroxide process to volatilize the exposed conductive layer and removing the volatilized conductive layer, and patterning the plural layers by using the hard mask pattern as an etch mask to form the MTJ device.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: May 12, 2015
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ga Young Ha, Ki Seon Park
  • Patent number: 9023662
    Abstract: A spintronic device and a method for making said spintronic device. The spintronic device includes an epitaxial crystalline ferromagnetic oxide formed directly on the semiconductor material thereby allowing spin-polarized current to be efficiently injected from the ferromagnetic oxide into the semiconductor material. A host crystal lattice includes multiple sets of stacked oxide layers of material A and B of a perovskite structure with a formula of ABO3. After an oxide layer of B is grown, magnetic ions are introduced to intermix with the B material, which may replace some of the ions of the B material. The process of growing additional stacked oxide layers of material A and B and introducing further magnetic ions after the deposition of the oxide layer of B continues until enough magnetic ions are sufficiently close to one another that they align in the same direction thereby forming a ferromagnetic oxide on the semiconductor material.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: May 5, 2015
    Assignee: Board of Regents, The University of Texas System
    Inventors: Alexander A. Demkov, Agham-Bayan S. Posadas
  • Patent number: 9024415
    Abstract: An electrical device includes a current transport layer formed using a layer of a topological material selected from the group of a topological insulator, a quantum anomalous hall (QAH) insulator, a topological insulator variant, and a topological magnetic insulator. In one embodiment, the current transport layer forms a conductive wire on an integrated circuit where the conductive wire includes two spatially separated edge channels, each edge channel carrying charge carriers propagating in one direction only. In other embodiments, an optical device includes an optical layer formed using a layer of the topological material. The optical layer can be a light absorbing layer, a light emitting layer, a light transport layer, or a light modulation layer.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: May 5, 2015
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Shoucheng Zhang, Xiao Zhang
  • Patent number: 9018719
    Abstract: According to one embodiment, a magnetoresistive element includes a storage layer having a perpendicular and variable magnetization, a reference layer having a perpendicular and invariable magnetization, a shift adjustment layer having a perpendicular and invariable magnetization in a direction opposite to a magnetization of the reference layer, a first nonmagnetic layer between the storage layer and the reference layer, and a second nonmagnetic layer between the reference layer and the shift adjustment layer. A switching magnetic field of the reference layer is equal to or smaller than a switching magnetic field of the storage layer, and a magnetic relaxation constant of the reference layer is larger than a magnetic relaxation constant of the storage layer.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: April 28, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuya Nishiyama, Hisanori Aikawa, Tadashi Kai, Toshihiko Nagase, Koji Ueda, Hiroaki Yoda
  • Patent number: 9005997
    Abstract: Provided are a magneto resistive element and a method of manufacturing the same, and in particular, a magneto resistive element and a method of manufacturing the same that may be applied to a digitizer sensing panel. The magneto resistive element includes a substrate, a first electrode disposed on the substrate, a first hole transport layer disposed on the first electrode, a first magneto resistive layer disposed on the first hole transport layer, wherein the first magneto resistive layer comprises an organic material, a first transport layer disposed on the first magneto resistive layer, a second magneto resistive layer disposed on the first transport layer, wherein the second magneto resistive layer comprises an organic material, a first electron transport layer disposed on the second magneto resistive layer, and a second electrode disposed on the first electron transport layer.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: April 14, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyun-Sung Bang, Won-Jong Kim, Ji-Young Choung, Joon-Gu Lee, Jin-Baek Choi, Yeon-Hwa Lee
  • Patent number: 9006849
    Abstract: This invention comprises a method to make small MTJ element using hybrid etching and oxygen plasma immersion ion implantation. The method has no removal of the magnetic free layer (or memory layer) and hence prevents any possible physical damage near the free layer edges. After photolithography patterning, alternative Ta, Ru, Ta etchings are performed before it stops on an MgO intermediate layer above the free layer. Then an oxygen plasma immersion ion implantation is performed to completely oxidize the exposed portion of the free layer, leaving the hard mask covered portion unchanged which define the lateral width of the MTJ element.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: April 14, 2015
    Inventor: Yimin Guo
  • Patent number: 9006704
    Abstract: A magnetic element is disclosed wherein first and second interfaces of a free layer with a Hk enhancing layer and tunnel barrier, respectively, produce enhanced surface perpendicular anisotropy to lower switching current or increase thermal stability in a magnetic tunnel junction (MTJ). In a MTJ with a bottom spin valve configuration where the Hk enhancing layer is an oxide, the capping layer contacting the Hk enhancing layer is selected to have a free energy of oxide formation substantially greater than that of the oxide. The free layer may be a single layer or composite comprised of an Fe rich alloy such as Co20Fe60B20. With a thin free layer, the interfacial perpendicular anisotropy may dominate the shape anisotropy to generate a magnetization perpendicular to the planes of the layers. The magnetic element may be part of a spintronic device or serve as a propagation medium in a domain wall motion device.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: April 14, 2015
    Assignee: Headway Technologies, Inc.
    Inventors: Guenole Jan, Ru Ying Tong, Witold Kula, Cheng Horng
  • Patent number: 9000540
    Abstract: The performances of semiconductor elements disposed in a multilayer wiring layer are improved. A semiconductor device includes: a first wire disposed in a first wiring layer; a second wire disposed in a second wiring layer stacked over the first wiring layer; a gate electrode arranged between the first wire and the second wire in the direction of stacking of the first wiring layer and the second wiring layer, and not coupled with the first wire and the second wire; a gate insulation film disposed over the side surface of the gate electrode; and a semiconductor layer disposed over the side surface of the gate electrode via the gate insulation film, and coupled with the first wire and the second wire.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: April 7, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Sunamura, Naoya Inoue, Kishou Kaneko
  • Patent number: 9000546
    Abstract: A spin-wave waveguide includes a ferromagnetic thin film resembling a wire in shape. A part of the ferromagnetic thin film, large in film thickness, is formed at one end of the ferromagnetic thin film, and a part of the ferromagnetic thin film, small in film thickness, and a part of the ferromagnetic thin film, large in film thickness, are alternately formed on the same plane, for at least not less than one cycle. A part of the ferromagnetic thin film, large in film thickness, is formed at the other end of the ferromagnetic thin film, wherein an insulating film, and an electrode film are stacked in this order on the ferromagnetic thin film in the part of the ferromagnetic thin film, large in film thickness.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: April 7, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Kenchi Ito, Masaki Yamada, Susumu Ogawa
  • Patent number: 8994130
    Abstract: A magnetic memory element includes: a first magnetization free layer formed of a ferromagnetic material having perpendicular magnetic anisotropy; a second magnetization free layer provided near the first magnetization free layer and formed of a ferromagnetic material having in-plane magnetic anisotropy; a reference layer formed of a ferromagnetic material having in-plane magnetic anisotropy; and a non-magnetic layer provided between the second magnetization free layer and the reference layer. The first magnetization free layer includes: a first magnetization fixed region of which magnetization is fixed, a second magnetization fixed region of which magnetization is fixed, and a magnetization free region which is connected to the first magnetization fixed region and the second magnetization fixed region, and of which magnetization can be switched. The second magnetization free layer is included in the first magnetization free layer in a plane parallel to a substrate.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: March 31, 2015
    Assignee: NEC Corporation
    Inventors: Shunsuke Fukami, Tetsuhiro Suzuki, Kiyokazu Nagahara, Nobuyuki Ishiwata, Norikazu Ohshima
  • Patent number: 8987848
    Abstract: A MTJ for a spintronic device that is a domain wall motion device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)n or (CoX)n composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: March 24, 2015
    Assignee: Headway Technologies, Inc.
    Inventors: Guenole Jan, Ru-Ying Tong, Yu-Jen Wang
  • Patent number: 8987847
    Abstract: A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)n or (CoX)n composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: March 24, 2015
    Assignee: Headway Technologies, Inc.
    Inventors: Guenole Jan, Ru-Ying Tong, Yu-Jen Wang
  • Patent number: 8987849
    Abstract: A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)n or (CoX)n? composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: March 24, 2015
    Assignee: Headway Technologies, Inc.
    Inventors: Guenole Jan, Ru-Ying Tong, Yu-Jen Wang
  • Patent number: 8987798
    Abstract: Provided is a magnetic tunneling junction device including a first structure including a magnetic layer; a second structure including at least two extrinsic perpendicular magnetization structures, each including a magnetic layer and; a perpendicular magnetization inducing layer on the magnetic layer; and a tunnel barrier between the first and second structures.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: March 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong Heon Park, Woo Chang Lim, Se Chung Oh, Young Hyun Kim, Sang Hwan Park, Jang Eun Lee
  • Patent number: 8982614
    Abstract: According to one embodiment, a magnetoresistive effect element includes a first ferromagnetic layer, a tunnel barrier provided on the first ferromagnetic layer, and a second ferromagnetic layer provided on the tunnel barrier. The tunnel barrier includes a nonmagnetic mixture containing MgO and a metal oxide with a composition which forms, in a solid phase, a single phase with MgO.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Nagamine, Daisuke Ikeno, Katsuya Nishiyama, Katsuaki Natori, Koji Yamakawa
  • Patent number: 8981508
    Abstract: A magnetic field sensor having a support with a top side and a bottom side, whereby a Hall plate is provided on the top side of the support and the Hall plate comprises a carbon-containing layer.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: March 17, 2015
    Assignee: Micronas GmbH
    Inventor: Joerg Franke
  • Patent number: 8981442
    Abstract: A semiconductor magnetic field sensor comprising a semiconductor well on top of a substrate layer is disclosed. The semiconductor well includes a first current collecting region and a second current collecting region and a current emitting region placed between the first current collecting region and the second current collecting region. The semiconductor well also includes a first MOS structure, having a first gate terminal, located between the first current collecting region and the current emitting region and a second MOS structure, having a second gate terminal, located between the current emitting region and the second current collecting region. In operation, the first gate terminal and the second gate terminal are biased for increasing a deflection length of a first current and of a second current. The deflection length is perpendicular to a plane defined by a surface of the semiconductor magnetic field sensor and parallel to a magnetic field.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: March 17, 2015
    Assignee: NXP B.V.
    Inventors: Victor Zieren, Anco Heringa, Olaf Wunnicke, Jan Slotboom, Robert Hendrikus Margaretha van Veldhoven, Jan Claes
  • Patent number: 8981505
    Abstract: A MTJ is disclosed with a discontinuous Mg or Mg alloy layer having a thickness from 1 to 3 Angstroms between a free layer and a capping layer in a bottom spin valve configuration. It is believed the discontinuous Mg layer serves to block conductive material in the capping layer from diffusing through the free layer and into the tunnel barrier layer thereby preventing the formation of conductive channels that function as electrical shunts within the insulation matrix of the tunnel barrier. As a result, the “low tail” percentage in a plot of magnetoresistive ratio vs Rp is minimized which means the number of high performance MTJ elements in a MTJ array is significantly increased, especially when a high temperature anneal is included in the MTJ fabrication process. The discontinuous layer is formed by a low power physical vapor deposition process.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: March 17, 2015
    Assignee: Headway Technologies, Inc.
    Inventors: Takahiro Moriyama, Yu-Jen Wang, Ru-Ying Tong
  • Patent number: 8975091
    Abstract: The present disclosure relates to a magnetic tunnel junction (MTJ) device and its fabricating method. Through forming MTJ through a damascene process, device damage due to the etching process and may be avoided. In some embodiments, a spacer is formed between a first portion and a second portion of the MTJ to prevent the tunnel insulating layer of the MTJ from being damaged in subsequent processes, greatly increasing product yield thereby. In other embodiments, signal quality may be improved and magnetic flux leakage may be reduced through the improved cup-shaped MTJ structure of this invention.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: March 10, 2015
    Assignee: Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Min-Hwa Chi, Mieno Fumitake
  • Patent number: 8962348
    Abstract: A method for forming a MTJ in a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/Ni)n composition. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. There may be a Ta insertion layer between the CoFeB layer and laminated layer to promote (100) crystallization in the CoFeB layer. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: February 24, 2015
    Assignee: Headway Technologies, Inc.
    Inventors: Guenole Jan, Witold Kula, Ru Ying Tong, Yu Jen Wang
  • Patent number: 8957498
    Abstract: The present invention relates to an on-chip electronic device and a method for manufacturing the same. The on-chip electronic device according to the present invention comprises a substrate, a porous layer, a plurality of magnetic bodies, and an electronic member layer. The porous layer is disposed on the substrate and has a plurality of voids; each of the plurality of magnetic bodies is disposed in the plurality of voids, respectively; and the electronic member layer is disposed on one side of the porous layer, such as upper side of or lower sider of the porous layer. Because the plurality of magnetic bodies is used as the core of the inductance, the inductance is increased effectively and the area of the on-chip electronic device is reduced. Besides the manufacturing method according to the present invention is simple and compatible with the current CMOS process, the manufacturing cost can be lowered.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: February 17, 2015
    Assignee: National Chiao Tung University
    Inventors: Yu-Ting Cheng, Tzu-Yuan Chao, Kuan-Ming Chen, Hsin-Fu Hsu
  • Patent number: 8953369
    Abstract: According to one embodiment, a magnetoresistive element includes first and second magnetic layers and a first nonmagnetic layer. The first magnetic layer has an axis of easy magnetization perpendicular to a film plane, and a variable magnetization. The second magnetic layer has an axis of easy magnetization perpendicular to a film plane, and an invariable magnetization. The first nonmagnetic layer is provided between the first and second magnetic layers. The second magnetic layer includes third and fourth magnetic layers, and a second nonmagnetic layer formed between the third and fourth magnetic layers. The third magnetic layer is in contact with the first nonmagnetic layer and includes Co and at least one of Zr, Nb, Mo, Hf, Ta, and W.
    Type: Grant
    Filed: January 20, 2014
    Date of Patent: February 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshihiko Nagase, Eiji Kitagawa, Katsuya Nishiyama, Tadashi Kai, Koji Ueda, Daisuke Watanabe
  • Patent number: 8952471
    Abstract: An integrated circuit can have a first substrate supporting a magnetic field sensing element and a second substrate supporting another magnetic field sensing element. The first and second substrates can be arranged in a variety of configurations. Another integrated circuit can have a first magnetic field sensing element and second different magnetic field sensing element disposed on surfaces thereof.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: February 10, 2015
    Assignee: Allegro Microsystems, LLC
    Inventors: Michael C. Doogue, William P. Taylor, Vijay Mangtani
  • Patent number: 8946836
    Abstract: In one embodiment a magnetic memory includes a memory device base and a plurality of memory cells disposed on the memory cell base, where each memory cell includes a layer stack comprising a plurality of magnetic and electrically conductive layers arranged in a stack of layers common to each other memory cell. The magnetic memory further includes an implanted matrix disposed between the memory cells and surrounding each memory cell, where the implanted matrix includes component material of the layer stack of each memory cell inter mixed with implanted species, where the implanted matrix comprises a non-conducting material and a non-magnetic material, wherein each memory cell is electrically and magnetically isolated from each other memory cell.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: February 3, 2015
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Alexander C. Kontos, Steven Sherman, John J. Hautala, Simon Ruffell
  • Patent number: 8941195
    Abstract: In a method for fabricating a semiconductor device, a conductive layer is formed on a substrate, where the substrate has a bottom layer formed thereon. A magnetic tunnel junction layer is formed on the conductive layer. The magnetic tunnel junction layer is patterned using an etching gas containing oxygen. An insulating layer is formed by oxidizing the conductive layer exposed outside the patterned magnetic tunnel junction layer using the etching gas.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: January 27, 2015
    Assignee: SK Hynix Inc.
    Inventors: Min Suk Lee, Bo Kyoung Jung
  • Patent number: 8941196
    Abstract: Orthogonal spin-torque bit cells whose spin torques from a perpendicular polarizer and an in-plane magnetized reference layer are constructively or destructively combined. An orthogonal spin-torque bit cell includes a perpendicular magnetized polarizing layer configured to provide a first spin-torque; an in-plane magnetized free layer and a reference layer configured to provide a second spin-torque. The first spin-torque and the second spin-torque combine and the combined first spin-torque and second spin-torque influences the magnetic state of the in-plane magnetized free layer. The in-plane magnetized free layer and the reference layer form a magnetic tunnel junction. The first spin-torque and second spin-torque can combine constructively to lower a switching current, increase a switching speed, and/or torque decrease an operating energy of the orthogonal spin-torque bit cell.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: January 27, 2015
    Assignee: New York University
    Inventors: Daniel Bedau, Huanlong Liu, Andrew David Kent
  • Patent number: 8933521
    Abstract: A device including at least two spintronic devices and a method of making the same. A magnetic connector extends between the two spintronic devices to conduct a magnetization between the two. The magnetic connector may further be disposed to conduct current to switch a magnetization of one of the two spintronic devices.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: January 13, 2015
    Assignee: Intel Corporation
    Inventors: Dmitri E. Nikonov, Ian A. Young
  • Patent number: 8932893
    Abstract: A method of fabricating a microelectromechanical (MEMS) device includes bonding a transducer wafer to a substrate wafer along a bond interface. An unpatterned transducer layer included within the transducer wafer is patterned. A release etch process is then performed during which a sacrificial layer is exposed to a selected release etchant to remove at a least a portion of the sacrificial layer through the openings in the patterned transducer layer. A release etch stop layer is formed between the sacrificial layer and the bond interface prior to exposing the sacrificial layer to the release etchant. The release etch stop layer prevents the ingress of the selected release etchant into the region of the MEMS device containing the bond interface during the release etch process.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: January 13, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Matthieu Lagouge
  • Patent number: 8921959
    Abstract: According to an embodiment, a magnetoresistive random access memory (MRAM) device comprises a bottom electrode, a stack, a dielectric material, a dielectric layer, and a conductive material. The bottom electrode is over a substrate, and the stack is over the bottom electrode. The stack comprises a magnetic tunnel junction (MTJ) and a top electrode. The dielectric material is along a sidewall of the stack, and the dielectric material has a height greater than a thickness of the MTJ and less than a stack height. The dielectric layer is over the stack and the dielectric material. The conductive material extends through the dielectric layer to the top electrode of the stack.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fu-Ting Sung, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 8912013
    Abstract: A magnetic tunneling junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, an apparatus is disclosed that includes an MTJ device. The MTJ device includes a free layer and a spin torque enhancing layer. The spin torque enhancing layer includes a nano-oxide layer.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: December 16, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Xiaochun Zhu, Seung H. Kang, Xia Li
  • Patent number: 8912614
    Abstract: Semiconductor stack structures such as magnetic tunnel junction structures having a magnetic free layer that is grown on composite, obliquely deposited seed layers to induce an increased in-plane magnetic anisotropy Hk of the magnetic free layer. In one aspect, a semiconductor device includes a composite seed layer formed on a substrate, and a magnetic layer formed on the composite seed layer. The composite seed layer includes a first seed layer obliquely formed with an incident angle from a surface normal of the substrate along a first direction of the substrate, and a second seed layer obliquely formed with the incident angle on the first seed layer along a second direction of the substrate, opposite the first direction.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Francesco A. Vetrò, Daniel C. Worledge
  • Patent number: 8907436
    Abstract: Provided are magnetic memory devices with a perpendicular magnetic tunnel junction. The device includes a magnetic tunnel junction including a free layer structure, a pinned layer structure, and a tunnel barrier therebetween. The pinned layer structure may include a first magnetic layer having an intrinsic perpendicular magnetization property, a second magnetic layer having an intrinsic in-plane magnetization property, and an exchange coupling layer interposed between the first and second magnetic layers. The exchange coupling layer may have a thickness maximizing an antiferromagnetic exchange coupling between the first and second magnetic layers, and the second magnetic layer may exhibit a perpendicular magnetization direction, due at least in part to the antiferromagnetic exchange coupling with the first magnetic layer.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: December 9, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: SeChung Oh, Ki Woong Kim, Younghyun Kim, Whankyun Kim, Sang Hwan Park
  • Patent number: 8907437
    Abstract: A current sensor packaged in an integrated circuit package to include a magnetic field sensing circuit, a current conductor and an insulator that meets the safety isolation requirements for reinforced insulation under the UL 60950-1 Standard is presented. The insulator is provided as an insulation structure having at least two layers of thin sheet material. The insulation structure is dimensioned so that plastic material forming a molded plastic body of the package provides a reinforced insulation. According to one embodiment, the insulation structure has two layers of insulating tape. Each insulating tape layer includes a polyimide film and adhesive. The insulation structure and the molded plastic body can be constructed to achieve at least a 500 VRMS working voltage rating.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: December 9, 2014
    Assignee: Allegro Microsystems, LLC
    Inventors: Shaun D. Milano, Weihua Chen
  • Patent number: 8901687
    Abstract: A magnetic device includes a substrate, a sensing block and a repair layer. The substrate has a registration layer and a barrier layer disposed on the registration layer. The sensing block is patterned to distribute on the barrier layer. The repair layer is disposed substantially on the barrier layer, wherein the barrier layer is configured to have a tunneling effect when a bias voltage exists between the sensing block and the registration layer.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: December 2, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Cheng Wei Chien, Kuei Hung Shen, Yung Hung Wang
  • Patent number: 8902644
    Abstract: A magnetoresistive element 10 having a memory cell 100 according to the present invention contains a first lower terminal n1 and a second lower terminal n2 respectively connected to both ends of a conductive layer 3 whose longitudinal direction is different from the column direction (X direction). Further, the gates of the first transistors M1 respectively included in two memory cells among the plurality of memory cells 100 and adjacent to each other in a row direction (Y direction) are commonly connected to a first word line 14. As a result, without increase of the cell area, it becomes possible to reserve a margin in the dimension of the cell structure or in the process for MRMA.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: December 2, 2014
    Assignee: NEC Corporation
    Inventors: Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi
  • Patent number: 8902634
    Abstract: According to one embodiment, a memory includes a resistance change element on an interlayer insulating film and including a lower electrode and an upper electrode, a sidewall insulating film on a side surface of the element, a plug in the interlayer insulating film and connected to the lower electrode, an interconnect on the interlayer insulating film and connected to the upper electrode. The element is provided immediately above the plug, the interconnect covers the side surface of the element via the sidewall insulating film, an upper surface of the first plug is covered with the lower electrode and the sidewall insulating film.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 2, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masayoshi Iwayama
  • Patent number: 8897060
    Abstract: According to one embodiment, a magnetoresistance effect element includes first and second magnetic layers having an axis of easy magnetization in a direction perpendicular to a film surface, a first nonmagnetic layer formed between the first and second magnetic layers, a first interface magnetic layer formed between the first magnetic layer and the first nonmagnetic layer, and a second nonmagnetic layer formed in the first interface magnetic layer and having an amorphous structure. An electric current flowing through the first magnetic layer, the first nonmagnetic layer, and the second magnetic layer makes a magnetization direction in the first magnetic layer variable.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: November 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiko Nakayama, Katsuya Nishiyama
  • Patent number: 8890266
    Abstract: A magnetic sensor includes a plurality of groups, each group comprising a plurality of magnetic tunnel junction (MTJ) devices having a plurality of conductors configured to couple the MTJ devices within one group in parallel and the groups in series enabling independent optimization of the material resistance area (RA) of the MTJ and setting total device resistance so that the total bridge resistance is not so high that Johnson noise becomes a signal limiting concern, and yet not so low that CMOS elements may diminish the read signal. Alternatively, the magnetic tunnel junction devices within each of at least two groups in series and the at least two groups in parallel resulting in the individual configuration of the electrical connection path and the magnetic reference direction of the reference layer, leading to independent optimization of both functions, and more freedom in device design and layout.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: November 18, 2014
    Assignee: EverSpin Technologies, Inc.
    Inventors: Phillip Mather, Jon Slaughter, Nicholas Rizzo
  • Patent number: 8884388
    Abstract: A magnetic memory element includes: a first magnetization free layer configured to be composed of ferromagnetic material with perpendicular magnetic anisotropy; a reference layer configured to be provided near the first magnetization free layer; a non-magnetic layer configured to be provided adjacent to the reference layer; and a step formation layer configured to be provided under the first magnetization free layer. The first magnetization free layer includes: a first magnetization fixed region of which magnetization is fixed, a second magnetization fixed region of which magnetization is fixed, and a magnetization free region configured to be connected with the first magnetization fixed region and the second magnetization fixed region. The first magnetization free layer has at least one of a step, a groove and a protrusion inside.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: November 11, 2014
    Assignee: NEC Corporation
    Inventors: Shunsuke Fukami, Kiyokazu Nagahara, Tetsuhiro Suzuki
  • Patent number: 8884386
    Abstract: A magnetoresistive random access memory (MRAM) device and a method of manufacture are provided. The MRAM device comprises a magnetic pinned layer, a compound GMR structure acting as a free layer, and a non-magnetic barrier layer separating the pinned and GMR layers. The barrier layer is provided to reduce the magnetic coupling of the free layer and GMR structure, as well as provide a resistive state (high or low) for retaining binary data (0 or 1) in the device. The GMR structure provides physical electrode connectivity for set/clear memory functionality which is separated from the physical electrode connectivity for the read functionality for the memory device.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tien-Wei Chiang, Chwen Yu, Ya-Chen Kao
  • Patent number: 8884387
    Abstract: A semiconductor device includes a substrate including an M2 patterned area. A VA pillar structure is formed over the M2 patterned area. The VA pillar structure includes a substractively patterned metal layer. The VA pillar structure is a sub-lithographic contact. An MTJ stack is formed over the oxide layer and the metal layer of the VA pillar. A size of the MTJ stack and a shape anisotropy of the MTJ stack are independent of a size and a shape anisotropy of the sub-lithographic contact.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: November 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Solomon Assefa, Michael C. Gaidis, Eric A. Joseph, Eugene J. O'Sullivan
  • Patent number: 8878320
    Abstract: According to one embodiment, a semiconductor memory device includes plural magneto-resistance elements being two-dimensionally arrayed on a semiconductor substrate. In the semiconductor memory device, each of the magneto-resistance elements includes: a first magnetic layer formed on the semiconductor substrate; a non-magnetic layer formed on the first magnetic layer; and a second magnetic layer formed on the non-magnetic layer, and an insulating film buried between the magneto-resistance elements adjacent to each other, a powder made of a metallic material or a magnetic material being dispersed in the insulating film.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: November 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Yamakawa, Daisuke Ikeno, Yasuki Sonoda
  • Patent number: 8878323
    Abstract: A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/Ni)n composition or the like where n is from 2 to 30. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. There may be a Ta insertion layer between the CoFeB layer and laminated layer to promote (100) crystallization in the CoFeB layer. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: November 4, 2014
    Assignee: Headway Technologies, Inc.
    Inventors: Guenole Jan, Witold Kula, Ru Ying Tong, Yu Jen Wang
  • Patent number: 8878317
    Abstract: A magnetoresistive element according to an embodiment includes: a first to third ferromagnetic layers, and a first nonmagnetic layer, the first and second ferromagnetic layers each having an axis of easy magnetization in a direction perpendicular to a film plane, the third ferromagnetic layer including a plurality of ferromagnetic oscillators generating rotating magnetic fields of different oscillation frequencies from one another. Spin-polarized electrons are injected into the first ferromagnetic layer and induce precession movements in the plurality of ferromagnetic oscillators of the third ferromagnetic layer by flowing a current between the first and third ferromagnetic layers, the rotating magnetic fields are generated by the precession movements and are applied to the first ferromagnetic layer, and at least one of the rotating magnetic fields assists a magnetization switching in the first ferromagnetic layer.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: November 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadaomi Daibou, Minoru Amano, Daisuke Saida, Junichi Ito, Yuichi Ohsawa, Chikayoshi Kamata, Saori Kashiwada, Hiroaki Yoda
  • Patent number: 8866242
    Abstract: A memory device may comprise a magnetic tunnel junction (MTJ) stack, a bottom electrode (BE) layer, and a contact layer. The MTJ stack may include a free layer, a barrier, and a pinned layer. The BE layer may be coupled to the MTJ stack, and encapsulated in a planarized layer. The BE layer may also have a substantial common axis with the MTJ stack. The contact layer may be embedded in the BE layer, and form an interface between the BE layer and the MTJ stack.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: October 21, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Seung H. Kang, Matthew M. Nowak
  • Patent number: 8866244
    Abstract: A semiconductor device includes: a spin torque written in-plane magnetization magnetoresistive element, placed over the main surface of a semiconductor substrate, whose magnetization state can be changed according to the direction of a current flow; and a first wiring electrically coupled with the magnetoresistive element and extended toward the direction along the main surface. The aspect ratio of the magnetoresistive element as viewed in a plane is a value other than 1. In a memory cell area where multiple memory cells in which the magnetoresistive element and a switching element are electrically coupled with each other are arranged, the following measure is taken: multiple magnetoresistive elements adjoining to each other in the direction of length of each magnetoresistive element as viewed in a plane are so arranged that they are not on an identical straight line extended in the direction of length.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: October 21, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Fumihiko Nitta
  • Patent number: 8866243
    Abstract: For the present ferromagnetic tunnel junction structure, employed is a means characterized by using an MgO barrier and using a Co2FeAl full-Heusler alloy for any of the ferromagnetic layers therein. The ferromagnetic tunnel junction structure is characterized in that Co2FeAl includes especially a B2 structure and one of the ferromagnetic layers is formed on a Cr buffer layer. The magnetoresistive element is characterized in that the ferromagnetic tunnel junction structure therein is any of the above-mentioned ferromagnetic tunnel junction structure. Accordingly, a large TMR, especially a TMR over 100% at room temperature can be attained, using Co2FeAl having a smallest ? though not a half-metal.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: October 21, 2014
    Assignee: National Institute for Materials Science
    Inventors: Koichiro Inomata, Wenhong Wang, Hiroaki Sukegawa