METHOD FOR SELF ALIGNED METAL GATE CMOS
A semiconductor device is formed by first providing a dual gate semiconductor device structure having FET pair precursors, which includes an nFET precursor and a pFET precursor, wherein each of the nFET precursor and the pFET precursor includes a dummy gate structure. At least one protective layer is deposited across the FET pair precursors, leaving the dummy gate structures exposed. The dummy gate structure is removed from one of the nFET precursor and the pFET precursor to create therein one of an nFET gate hole and a pFET gate hole, respectively. A fill is deposited into the formed one of the nFET gate hole and the pFET gate.
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Priority is claimed as a continuation application to U.S. patent application Ser. No. 13/108,138, filed May 16, 2011, the disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION1. Field of the Invention
The field of the present invention is semiconductor fabrication, particularly CMOS semiconductor fabrication in which preformed dummy gates are selectively removed.
2. Background
One major drawback of fabricating metal gate CMOS semiconductors using replacement gate or semi-replacement gate methods is the challenges presented by ground rule requirements. Specifically, the n to p spacing, in an SRAM for example, makes removing the dummy gate from one FET while being selective to the other FET difficult at best. However, even with these challenges, certain CMOS fabrication processes may find replacement gate or semi-replacement gate methods advantageous, thereby enabling removal of the dummy gate from one FET while being selective of the other FET.
SUMMARY OF THE INVENTIONThe present invention is directed toward a method of forming a semiconductor device in which preformed dummy gates are selectively removed and intermediate semiconductor device products. The semiconductor device includes precursors to a FET pair, and may be a dual gate CMOS structure. The FET pair precursors includes an nFET precursor and a pFET precursor, each of which includes a dummy gate structure. At least one protective layer is deposited across the FET pair precursors, leaving the dummy gate structures exposed. The dummy gate structure is removed from at least the nFET precursor and the pFET precursor, leaving one of an nFET gate hole and a pFET gate hole, respectively. A fill is then deposited within the formed gate hole.
As a further aspect of the method, depositing at least one protective layer may include depositing a first protective layer across the FET pair precursors, depositing a second protective layer onto the first protective layer, and then removing a portion of the first and second protective layers to expose the dummy gate structures. The first protective layer may be a SiN liner, and the second protective layer may be a high density plasma oxide.
As another further aspect of the method, the dummy gate structure of the nFET precursor may include an N-type poly Si, and the dummy gate structure of the pFET precursor may include a P-type poly Si. When removing the dummy gate structure from either of the nFET precursor and the pFET precursor, the dummy gate structure from one of the nFET precursor and the pFET precursor is selectively removed.
As another further aspect of the method, depositing the first fill may include depositing a first conformal film onto the FET pair precursors and removing a portion of the first film to expose the first fill and the dummy gate structure from the other of the nFET precursor and the pFET precursor. This aspect may be achieved by further removing the dummy gate structure from the other of the nFET precursor and the pFET precursor to create therein one of the nFET gate hole and the pFET gate hole, respectively, and depositing a second fill into one of the nFET gate hole and the pFET gate hole. A second conformal film may thereafter be deposited onto the FET pair precursors, then a portion of the second film may be removed to expose the first fill and the second fill.
As another further aspect of the invention, an oxygen treatment may be used to add O2 to vacancies in a high K material, thereby providing a lower threshold voltage in a pFET by filling in the holes without changing the threshold voltage for the paired nFET.
A first intermediate semiconductor device product includes FET pair precursors disposed on a substrate. One of the FET pair precursors may be an nFET precursor, and the other may be a pFET precursor. One of the FET precursors includes a fill disposed above and in contact with its respective metal gate layer, and the other of the FET precursors includes a dummy gate structure disposed above and in contact with its respective second metal gate later, with the fill and the dummy gate structure sharing a common interface.
A second intermediate semiconductor device product includes FET pair precursors disposed on a substrate, with one of the FET pair precursors being an nFET precursor, and the other being a pFET precursor. Each FET precursor includes spacers disposed on two sides of and extending above a gate stack. Each gate stack is topped by a metal gate layer. A fill is disposed over the pair of FET precursors and between the spacers of each FET precursor. The fill is in contact with each of the metal gate layers. This fill may also extend above the spacers and continuously between the nFET and pFET precursors. The fill may overlay at least one protective layer disposed over parts of the FET precursors, and it may be deposited as a conformal film, such as, for example, a SiN film.
Any of the above aspects of the method may be employed alone or in combination.
Accordingly, an improved method of forming a semiconductor device is disclosed. Advantages of the improvements will appear from the drawings and the description of the preferred embodiment.
In the drawings, wherein like reference numerals refer to similar components:
Turning in detail to the drawings,
As shown in
Next, as shown in
With the two dummy gates 116, 118 exposed, the N-poly is removed, as shown in
A conformal SiN film 146 is then deposited on the semiconductor device structure 110, thereby depositing a SiN fill 148 in the nFET gate hole 144, as shown in
At this stage, the other dummy gate, shown as the P-poly dummy gate in
A conformal SiN film 154 is again deposited on the semiconductor device structure 110, thereby depositing an SiN fill 156 in the pFET gate hole, as shown in
As a final step in the preferred process, the conformal SiN is etched, preferably using RIE processes, to remove the SiN film 154 down to the level of the gate spacers 136, leaving the SiN fill 156 between the gate spacers 136 of the pFET precursor 114.
The semiconductor device structure 110 resulting from this final step is shown in
Thus, a method of forming a semiconductor device is disclosed. While embodiments of this invention have been shown and described, it will be apparent to those skilled in the art that many more modifications are possible without departing from the inventive concepts herein. The invention, therefore, is not to be restricted except in the spirit of the following claims.
Claims
1. A method of forming a semiconductor device, the method comprising:
- providing a dual gate semiconductor device structure having FET pair precursors, including an nFET precursor and a pFET precursor, wherein each of the nFET precursor and the pFET precursor includes a dummy gate structure;
- depositing at least one protective layer across the FET pair precursors, leaving the dummy gate structures exposed;
- removing the dummy gate structure from one of the nFET precursor and the pFET precursor to form therein one of an nFET gate hole and a pFET gate hole, respectively;
- depositing a first fill into the formed one of the nFET gate hole and the pFET gate hole.
2. The method of claim 1, wherein depositing at least one protective layer includes:
- depositing a first protective layer across the FET pair precursors;
- depositing a second protective layer onto the first protective layer; and
- removing a portion of the first and second protective layers to expose the dummy gate structures.
3. The method of claim 2, wherein the first protective layer is a SiN liner.
4. The method of claim 2, wherein the second protective layer is a high density plasma oxide.
5. The method of claim 1, wherein the dummy gate structure of the nFET precursor comprises an N-type poly Si, and the dummy gate structure of the pFET precursor comprises a P-type poly Si, and wherein removing the dummy gate structure from one of the nFET precursor and the pFET precursor includes selectively removing the dummy gate structure from one of the nFET precursor and the pFET precursor.
6. The method of claim 1, further comprising, following formation of the pFET gate hole and before depositing the first fill, performing an oxidation treatment.
7. The method of claim 1, wherein depositing the first fill comprises:
- depositing a first conformal film onto the FET pair precursors; and
- removing a portion of the first film to expose the first fill and the dummy gate structure from the other of the nFET precursor and the pFET precursor.
8. The method of claim 7, wherein the first conformal film comprises a SiN film.
9. The method of claim 7, further comprising:
- removing the dummy gate structure from the other of the nFET precursor and the pFET precursor to create therein one of the nFET gate hole and the pFET gate hole, respectively; and
- depositing a second fill into one of the nFET gate hole and the pFET gate hole.
10. The method of claim 9, further comprising, following formation of the pFET gate hole and before depositing the first fill, performing an oxidation treatment.
11. The method of claim 9, wherein depositing the second fill comprises:
- depositing a second conformal film onto the FET pair precursors; and
- removing a portion of the second film to expose the first fill and the second fill.
12. The method of claim 11, wherein the second conformal film comprises a SiN film.
Type: Application
Filed: Sep 14, 2012
Publication Date: Jan 10, 2013
Applicant: International Business Machines Corporation (YT) (Somers, NY)
Inventors: Kangguo Cheng (Yorktown Heights, NY), Bruce B. Doris (Brewster, NY), Ying Zhang (Yorktown Heights, NY)
Application Number: 13/617,528
International Classification: H01L 21/283 (20060101);