Making Electrode Structure Comprising Conductor-insulator-semiconductor, E.g., Mis Gate (epo) Patents (Class 257/E21.19)

  • Patent number: 10566328
    Abstract: One illustrative integrated circuit product disclosed herein includes a plurality of FinFET transistor devices, a plurality of fins, each of the fins having an upper surface, and an elevated isolation structure having an upper surface that is positioned at a level that is above a level of the upper surface of the fins. In this example, the product also includes a first gate structure having an axial length in a direction corresponding to the gate width direction of the transistor devices, wherein at least a portion of the axial length of the first gate structure is positioned above the upper surface of the elevated isolation structure.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: February 18, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Bala Haran, Christopher Sheraw, Mahender Kumar
  • Patent number: 10522401
    Abstract: A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: December 31, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sungwoo Myung, GeumJung Seong, Jisoo Oh, JinWook Lee, Dohyoung Kim, Yong-Ho Jeon
  • Patent number: 10468406
    Abstract: A circuit is provided that includes a castellated channel device that comprises a heterostructure overlying a substrate structure, a castellated channel device area formed in the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, and a three-sided castellated conductive gate contact that extends across the castellated channel device area. The three-sided gate contact substantially surrounds each ridge channel around their tops and their sides to overlap a channel interface of heterostructure of each of the plurality of ridge channels. The three-sided castellated conductive gate contact extends along at least a portion of a length of each ridge channel.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: November 5, 2019
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Justin Andrew Parke, Eric J. Stewart, Robert S. Howell, Howell George Henry, Bettina Nechay, Harlan Carl Cramer, Matthew Russell King, Shalini Gupta, Ronald G. Freitag, Karen Marie Renaldo
  • Patent number: 10160938
    Abstract: According to the present invention, it is possible to provide a cleaning method for removing a photoresist and dry etching residue on a surface of a semiconductor element having a low-k film and a material that contains 10 atom % or more of tantalum, wherein the cleaning method is characterized by using a cleaning solution that contains 0.002-50 mass % of hydrogen peroxide, 0.001-1 mass % of an alkaline earth metal compound, an alkali, and water.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: December 25, 2018
    Assignee: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Toshiyuki Oie, Kenji Shimada
  • Patent number: 10134748
    Abstract: Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming Chyi Liu, Shih-Chang Liu, Sheng-Chieh Chen, Yu-Hsing Chang
  • Patent number: 10134604
    Abstract: A method includes forming a metal gate structure over a first fin, where the metal gate structure is surrounded by a first dielectric material, and forming a capping layer over the first dielectric material, where an etch selectivity between the metal gate structure and the capping layer is over a pre-determined threshold. The method also includes forming a patterned hard mask layer over the first fin and the first dielectric material, where an opening of the patterned hard mask layer exposes a portion of the metal gate structure and a portion of the capping layer. The method further includes removing the portion of the metal gate structure exposed by the opening of the patterned hard mask layer.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Jie Huang, Syun-Ming Jang, Ryan Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Tai-Chun Huang, Chunyao Wang, Tze-Liang Lee, Chi On Chui
  • Patent number: 9859388
    Abstract: Aspects of the disclosure include a semiconductor structure that includes a vertical fin structure having a top portion, a bottom portion, vertical side walls, a source area in contact with the vertical fin structure, a drain area in contact with the vertical fin structure, a plurality of spacers comprising a first oxide layer in contact with the source area, and a second oxide layer in contact with the drain area. The first oxide layer can have a thickness that is equal to a thickness of the second oxide layer.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: January 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li
  • Patent number: 9773783
    Abstract: A semiconductor device comprises a transistor device arranged on a substrate. The transistor device comprises a first metal gate stack arranged over a channel region, a source/drain region arranged adjacent to the metal gate stack, the source/drain region located on a fin, and a capacitor device arranged on the substrate. The capacitor device comprises a second metal gate stack arranged on the substrate, a spacer arranged along a sidewall of the second metal gate stack, and a first conductive contact arranged on the substrate adjacent to the spacer such that the spacer is disposed between the first conductive contact and the second metal gate stack.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: September 26, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng
  • Patent number: 9633860
    Abstract: A semiconductor structure includes an isolation structure, a gate stack, a spacer and a patterned resist protective oxide. The isolation structure is formed in a semiconductor substrate, and electrically isolates device regions of the semiconductor substrate. The gate stack is located on the isolation structure. The spacer is formed along a sidewall of the gate stack on the isolation structure. The patterned resist protective oxide is located on the isolation structure and covers a sidewall of the spacer such that the spacer is interposed between the patterned resist protective oxide and the gate stack.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: April 25, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Liang Liao, Chia-Yao Liang, Jui-Long Chen, Sheng-Yuan Lin, Yi-Lii Huang, Kuo-Hsi Lee, Po-An Chen
  • Patent number: 9496409
    Abstract: A first source electrode is formed in contact with a semiconductor layer; a first drain electrode is formed in contact with the semiconductor layer; a second source electrode which extends beyond an end portion of the first source electrode to be in contact with the semiconductor layer is formed; a second drain electrode which extends beyond an end portion of the first drain electrode to be in contact with the semiconductor layer is formed; a first sidewall is formed in contact with a side surface of the second source electrode and the semiconductor layer; a second sidewall is formed in contact with a side surface of the second drain electrode and the semiconductor layer; and a gate electrode is formed to overlap the first sidewall, the second sidewall, and the semiconductor layer with a gate insulating layer provided therebetween.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: November 15, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Daisuke Matsubayashi
  • Patent number: 9418903
    Abstract: Embodiments of the present invention provide methods and structures by which the inherent discretization of effective width can be relaxed through introduction of a fractional effective device width, thereby allowing greater flexibility for design applications, such as SRAM design optimization. A portion of some fins are clad with a capping layer or workfunction material to change the threshold voltage (Vt) for a part of the fin, rendering that part of the fin electrically inactive, which changes the effective device width (Weff). Other fins are unclad, and provide maximum area of constant threshold voltage. In this way, the effective device width of some devices is reduced. Therefore, the effective device width is controllable by controlling the level of cladding of the fin.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: August 16, 2016
    Assignee: Globalfoundries Inc.
    Inventors: Ramachandra Divakaruni, Arvind Kumar, Carl Radens
  • Patent number: 9257289
    Abstract: The present disclosure provides a method of forming a gate structure of a semiconductor device with reduced gate-contact parasitic capacitance. In a replacement gate scheme, a high-k gate dielectric layer is deposited on a bottom surface and sidewalls of a gate cavity. A metal cap layer and a sacrificial cap layer are deposited sequentially over the high-k gate dielectric layer to form a material stack. After ion implantation in vertical portions of the sacrificial cap layer, at least part of the vertical portions of the material stack is removed. The subsequent removal of a remaining portion of the sacrificial cap layer provides a gate component structure. The vertical portions of the gate component structure do not extend to a top of the gate cavity, thereby significantly reducing gate-contact parasitic capacitance.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: February 9, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Effendi Leobandung, Vijay Narayanan
  • Patent number: 9029225
    Abstract: The present disclosure discloses a method for manufacturing an N-type MOSFET, comprising: forming a part of the MOSFET on a semiconductor substrate, the part of the MOSFET comprising source/drain regions in the semiconductor substrate, a replacement gate stack between the source/drain regions above the semiconductor substrate, and a gate spacer surrounding the replacement gate stack; removing the replacement gate stack of the MOSFET to form a gate opening exposing a surface of the semiconductor substrate; forming an interface oxide layer on the exposed surface of the semiconductor; forming a high-K gate dielectric layer on the interface oxide layer in the gate opening; forming a first metal gate layer on the high-K gate dielectric layer; implanting dopant ions into the first metal gate layer; and performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high-K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate diel
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: May 12, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Qiuxia Xu, Huilong Zhu, Huajie Zhou, Gaobo Xu
  • Patent number: 9029209
    Abstract: A method of manufacturing a thin film transistor substrate (1) includes at least the steps of: forming a gate electrode (15) on an insulating substrate (10) by using a first photomask; forming a channel protective film (21) on an oxide semiconductor layer (13) so as to cover a channel region (C) by using a second photomask; forming a source electrode (19) on the oxide semiconductor layer (13) by using a third photomask; and forming a planarizing film (18) on an interlayer insulating film (17) by using a fourth photomask.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: May 12, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Mitsunobu Miyamoto
  • Patent number: 9018710
    Abstract: A semiconductor device includes a substrate including first and second regions. A first gate stack structure containing a first effective work function adjust species is formed over the first region and a second gate stack structure containing a second effective work function adjust species is formed over the second region. A channel region is formed under the first gate stack structure and contains a threshold voltage adjust species.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: April 28, 2015
    Assignee: SK Hynix Inc.
    Inventors: Seung-Mi Lee, Yun-Hyuck Ji
  • Patent number: 8999794
    Abstract: An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. In an example, the method includes forming a gate structure over a substrate; forming a doped region in the substrate; performing a first etching process to remove the doped region and form a trench in the substrate; and performing a second etching process that modifies the trench by removing portions of the substrate.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ziwei Fang, Ying Zhang, Jeff J. Xu
  • Patent number: 8999830
    Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: April 7, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Yeng-Peng Wang, Chun-Hsien Lin, Chan-Lon Yang, Guang-Yaw Hwang, Shin-Chi Chen, Hung-Ling Shih, Jiunn-Hsiung Liao, Chia-Wen Liang
  • Patent number: 8987100
    Abstract: Provided are methods of forming field effect transistors. The method includes preparing a substrate with a first region and a second region, forming fin portions on the first and second regions, each of the fin portions protruding from the substrate and having a first width, forming a first mask pattern to expose the fin portions on the first region and cover the fin portions on the second region, and changing widths of the fin portions provided on the first region.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: March 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang Woo Oh, Shincheol Min, Jongwook Lee, Choongho Lee
  • Patent number: 8975179
    Abstract: The present disclosure provides a method of semiconductor fabrication including forming a dielectric layer is formed on and interposing a first feature and a second feature. A first CMP process is performed on the dielectric layer to removing the dielectric layer from a top surface of the first feature to expose an underlying layer and decreasing a thickness of the dielectric layer disposed on a top surface of the second feature such that a portion of the dielectric layer remains disposed on the top surface of the second feature. Thereafter, a second CMP process is performed which removes the dielectric layer remaining on the top surface of the second feature.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: March 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Hao Tu, Weilun Hong, Ying-Tsung Chen, Liang-Guang Chen
  • Patent number: 8975174
    Abstract: A gate stack for a transistor is formed by a process including forming a high dielectric constant layer on a semiconductor layer. A metal layer is formed on the high dielectric constant layer. A silicon containing layer is formed over the metal layer. An oxidized layer incidentally forms during the silicon containing layer formation and resides on the metal layer beneath the silicon containing layer. The silicon containing layer is removed. The oxidized layer residing on the metal layer is removed after removing the silicon containing layer.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: March 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Kisik Choi, Matthew W. Copel, Richard A. Haight
  • Patent number: 8975173
    Abstract: A semiconductor device includes buried gates formed over a substrate, storage node contact plugs which are formed over the substrate and include a pillar pattern and a line pattern disposed over the pillar pattern, and a bit line structure which is formed over the substrate and isolates adjacent ones of the storage node contact plugs from each other.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: March 10, 2015
    Assignee: SK Hynix Inc.
    Inventors: Jong-Han Shin, Bo-Min Park
  • Patent number: 8969187
    Abstract: A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Wilfried E. A. Haensch, Shu-Jen Han, Chung-Hsun Lin
  • Patent number: 8969930
    Abstract: A gate stack structure comprises an isolation dielectric layer formed on and embedded into a gate. A sidewall spacer covers opposite side faces of the isolation dielectric layer, and the isolation dielectric layer located on an active region is thicker than the isolation dielectric layer located on a connection region. A method for manufacturing the gate stack structure comprises removing part of the gate in thickness, the thickness of the removed part of the gate on the active region is greater than the thickness of the removed part of the gate on the connection region so as to expose opposite inner walls of the sidewall spacer; forming an isolation dielectric layer on the gate to cover the exposed inner walls. There is also provided a semiconductor device and a method for manufacturing the same. The methods can reduce the possibility of short-circuit occurring between the gate and the second contact hole and can be compatible with the dual-contact-hole process.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: March 3, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Haizhoou Yin, Zhijiong Luo, Huilong Zhu
  • Patent number: 8969188
    Abstract: Methods of manufacturing a semiconductor device including a multi-layer of dielectric layers may include forming a metal oxide layer on a semiconductor substrate and forming a multi-layer of silicate layers including metal atoms and silicon atoms, on the metal oxide layer. The multi-layer of silicate layers may include at least two metallic silicate layers having different silicon concentrations, which are a ratio of silicon atoms among all metal atoms and silicon atoms included in the metallic silicate layer.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-chul Kim, Jong-cheol Lee, Heung-ahn Kwon, Hyun-wook Lee
  • Patent number: 8963257
    Abstract: The disclosure relates to a Fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a top surface; a first fin and a second fin extending above the substrate top surface, wherein each of the fins has a top surface and sidewalls; an insulation layer between the first and second fins extending part way up the fins from the substrate top surface; a first gate dielectric covering the top surface and sidewalls of the first fin having a first thickness and a second gate dielectric covering the top surface and sidewalls of the second fin having a second thickness less than the first thickness; and a conductive gate strip traversing over both the first gate dielectric and second gate dielectric.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Yuan Shih, Yi-Tang Lin, Chih-Sheng Chang
  • Patent number: 8951902
    Abstract: The present invention is provided in order to remove contamination due to contaminant impurities of the interfaces of each film which forms a TFT, which is the major factor that reduces the reliability of TFTs. By connecting a washing chamber and a film formation chamber, film formation can be carried out without exposing TFTs to the air during the time from washing step to the film formation step and it becomes possible to maintain the cleanliness of the interfaces of each film which form the TFT.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: February 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Taketomi Asami, Mitsuhiro Ichijo, Satoshi Toriumi, Takashi Ohtsuki, Shunpei Yamazaki
  • Patent number: 8952451
    Abstract: A semiconductor device having a metal gate includes a substrate having a first gate trench and a second gate trench formed thereon, a gate dielectric layer respectively formed in the first gate trench and the second gate trench, a first work function metal layer formed on the gate dielectric layer in the first gate trench and the second gate trench, a second work function metal layer respectively formed in the first gate trench and the second gate trench, and a filling metal layer formed on the second work function metal layer. An opening width of the second gate trench is larger than an opening width of the first gate trench. An upper area of the second work function metal layer in the first gate trench is wider than a lower area of the second work function metal layer in the first gate trench.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: February 10, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Yeng-Peng Wang, Chun-Hsien Lin, Chan-Lon Yang, Guang-Yaw Hwang, Shin-Chi Chen, Hung-Ling Shih, Jiunn-Hsiung Liao, Chia-Wen Liang
  • Patent number: 8946069
    Abstract: A fabricating method of a semiconductor device includes providing a substrate having a first region and a second region, forming a plurality of first gates in the first region of the substrate, such that the first gates are spaced apart from each other at a first pitch, forming a plurality of second gates in the second region of the substrate, such that the second gates are spaced apart from each other at a second pitch different from the first pitch, implanting an etch rate adjusting dopant into the second region to form implanted regions, while blocking the first region, forming a first trench by etching the first region between the plurality of first gates, and forming a second trench by etching the second region between the plurality of second gates.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: February 3, 2015
    Assignee: Samsung Electronics Co. Ltd.
    Inventors: Jin-Wook Lee, Myeong-Cheol Kim, Sang-Min Lee, Young-Ju Park, Hyung-Yong Kim, Myung-Hoon Jung
  • Patent number: 8946828
    Abstract: A semiconductor device includes a semiconductor substrate; a gate stack overlying the substrate, a spacer formed on sidewalls of the gate stack, and a protection layer overlying the gate stack for filling at least a portion of a space surrounded by the spacer and the top surface of the gate stack. A top surface of the spacer is higher than a top surface of the gate stack.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sey-Ping Sun, Tsung-Lin Lee, Chin-Hsiang Lin, Chih-Hao Chang, Chen-Nan Yeh, Chao-An Jong
  • Patent number: 8940623
    Abstract: A process for obtaining an array of nanodots (212) for microelectronic devices, characterized in that it comprises the following steps: deposition of a silicon layer (210) on a substrate (100, 132), formation, above the silicon layer (210), of a layer (240) of a material capable of self-organizing, in which at least one polymer substantially forms cylinders (242) organized into an array within a matrix (244), formation of patterns (243) in the layer (240) of a material capable of self-organizing by elimination of the said cylinders (242), formation of a hard mask (312) by transfer of the said patterns (243), production of silicon dots (212) in the silicon layer (210) by engraving through the hard mask (312), silicidation of the silicon dots (212), comprising deposition of a metal layer (510).
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: January 27, 2015
    Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, CNRS-Centre National de la Recherche Scientifique, Universite Joseph Fourier
    Inventors: Guillaume Gay, Thierry Baron, Eric Jalaguier
  • Patent number: 8927407
    Abstract: Disclosed herein is a method of forming self-aligned contacts for a semiconductor device. In one example, the method includes forming a plurality of spaced-apart sacrificial gate electrodes above a semiconducting substrate, wherein each of the gate electrodes has a gate cap layer positioned on the gate electrode, and performing at least one etching process to define a self-aligned contact opening between the plurality of spaced-apart sacrificial gate electrodes. The method further includes removing the gate cap layers to thereby expose an upper surface of each of the sacrificial gate electrodes, depositing at least one layer of conductive material in said self-aligned contact opening and removing portions of the at least one layer of conductive material that are positioned outside of the self-aligned contact opening to thereby define at least a portion of a self-aligned contact positioned in the self-aligned contact opening.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: January 6, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Peter Baars, Andy Wei, Erik Geiss, Martin Mazur
  • Patent number: 8907410
    Abstract: A through-the silicon via (TSV) structure providing a built-in TSV U-shaped FET that includes an annular gate shaped as a TSV partially embedded in a substrate, the annular gate having an inner and an outer surface bound by an oxide layer; a drain formed on an isolated epitaxial layer on top of the substrate conformally connecting the gate oxide layer surrounding the inner annular surface of the TSV; a source partially contacting said gate oxide layer conformally contacting gate oxide layer surrounding the outer surface of the TSV.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chandrasekharan Kothandaraman, Sami Rosenblatt, Geng Wang
  • Patent number: 8901665
    Abstract: The present disclosure provides a method of semiconductor fabrication including forming an inter-layer dielectric (ILD) layer on a semiconductor substrate. The ILD layer has an opening defined by sidewalls of the ILD layer. A spacer element is formed on the sidewalls of the ILD layer. A gate structure is formed in the opening adjacent the spacer element. In an embodiment, the sidewall spacer also for a decrease in the dimensions (e.g., length) of the gate structure formed in the opening.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: December 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Andrew Joseph Kelly, Pei-Shan Chien, Yung-Ta Li, Chan Syun Yang
  • Patent number: 8883621
    Abstract: Provided is a semiconductor structure including a gate structure, a first spacer, and a second spacer. The gate structure is formed on a substrate and includes a gate material layer, a first hard mask layer disposed on the gate material layer, and a second hard mask layer disposed on the first hard mask layer. The first spacer is disposed on sidewalls of the gate structure. The second spacer is disposed adjacent to the first spacer. The etch rate of the first hard mask layer, the etch rate of the first spacer, and the etch rate of the second spacer are substantially the same and significantly smaller than the etch rate of the second hard mask layer in a rinsing solution.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: November 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chia-Jung Li, Po-Chao Tsao
  • Patent number: 8860141
    Abstract: A semiconductor chip has shapes on a particular level that are small enough to require a first mask and a second mask, the first mask and the second mask used in separate exposures during processing. A circuit on the semiconductor chip requires close tracking between a first and a second FET (field effect transistor). For example, the particular level may be a gate shape level. Separate exposures of gate shapes using the first mask and the second mask will result in poorer FET tracking (e.g., gate length, threshold voltage) than for FETs having gate shapes defined by only the first mask. FET tracking is selectively improved by laying out a circuit such that selective FETs are defined by the first mask. In particular, static random access memory (SRAM) design benefits from close tracking of six or more FETs in an SRAM cell.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: October 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Derick Gardner Behrends, Todd Alan Christensen, Travis Reynold Hebig, Michael Launsbach, Daniel Mark Nelson
  • Patent number: 8853068
    Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer in the first region, forming a first metal layer over capping layer in the first region and over the high-k dielectric in the second region, thereafter, forming a first gate stack in the first region and a second gate stack in the second region, protecting the first metal layer in the first gate stack while performing a treatment process on the first metal layer in the second gate stack, and forming a second metal layer over the first metal layer in the first gate stack and over the treated first metal layer in the second gate stack.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: October 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Peng-Fu Hsu, Kang-Cheng Lin, Kuo-Tai Huang
  • Patent number: 8853796
    Abstract: A device includes a substrate with a device region surrounded by an isolation region, in which the device region includes edge portions along a width of the device region and a central portion. The device further includes a gate layer disposed on the substrate over the device region, in which the gate layer includes a graded thickness in which the gate layer at edge portions of the device region has a thickness TE that is different from a thickness TC at the central portion of the device region.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: October 7, 2014
    Assignees: GLOBALFOUNDIERS Singapore Pte. Ltd.
    Inventors: Young Way Teh, Michael V. Aquilino, Arifuzzaman (Arif) Sheikh, Yun Ling Tan, Hao Zhang, Deleep R. Nair, Jinghong H. (John) Li
  • Patent number: 8853769
    Abstract: Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: October 7, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Deepak Thimmegowda, Andrew R. Bicksler, Roland Awusie
  • Patent number: 8846514
    Abstract: A thin film transistor array panel according to an exemplary embodiment of the present disclosure includes: an insulating substrate; a gate electrode disposed on the insulating substrate; a gate insulating layer disposed on the gate electrode; a semiconductor disposed on the gate insulating layer; a source electrode and a drain electrode disposed on the semiconductor; an ohmic contact layer disposed at an interface between at least one of the source and drain electrodes and the semiconductor. Surface heights of the source and drain electrodes different, while surface heights of the semiconductor and the ohmic contact layer are the same. The ohmic contact layer is made of a silicide of a metal used for the source and drain electrodes.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: September 30, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sang Ho Park, Yoon Ho Khang, Se Hwan Yu, Yong Su Lee, Chong Sup Chang, Myoung Geun Cha, Hyun Jae Na
  • Patent number: 8836039
    Abstract: A semiconductor device includes a high dielectric gate insulating film formed on a substrate, and a metal gate electrode formed on the high dielectric gate insulating film. The metal gate electrode includes a crystalline portion and an amorphous portion. A halogen element is eccentrically located in the amorphous portion.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: September 16, 2014
    Assignee: Panasonic Corporation
    Inventors: Jun Suzuki, Hiroshi Nakagawa
  • Patent number: 8828838
    Abstract: An integrated circuit device and methods of manufacturing the same are disclosed. In an example, integrated circuit device includes a capacitor having a doped region disposed in a semiconductor substrate, a dielectric layer disposed over the doped region, and an electrode disposed over the dielectric layer. At least one post feature embedded in the electrode.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: September 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Ming Zhu
  • Patent number: 8809186
    Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: August 19, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hirokazu Sayama, Kazunobu Ohta, Hidekazu Oda, Kouhei Sugihara
  • Patent number: 8809959
    Abstract: The performances of a semiconductor device are improved. The device includes a first MISFET in which hafnium is added to the gate electrode side of a first gate insulation film including silicon oxynitride, and a second MISFET in which hafnium is added to the gate electrode side of a second gate insulation film including silicon oxynitride. The hafnium concentration in the second gate insulation film of the second MISFET is set smaller than the hafnium concentration in the first gate insulation film of the first MISFET; and the nitrogen concentration in the second gate insulation film of the second MISFET is set smaller than the nitrogen concentration in the first gate insulation film of the first MISFET. As a result, the threshold voltage of the second MISFET is adjusted to be smaller than the threshold voltage of the first MISFET.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: August 19, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hiromasa Yoshimori, Hirofumi Shinohara, Toshiaki Iwamatsu
  • Patent number: 8809133
    Abstract: There is provided a technique to form a single crystal semiconductor thin film or a substantially single crystal semiconductor thin film. A catalytic element for facilitating crystallization of an amorphous semiconductor thin film is added to the amorphous semiconductor thin film, and a heat treatment is carried out to obtain a crystalline semiconductor thin film. After the crystalline semiconductor thin film is irradiated with ultraviolet light or infrared light, a heat treatment at a temperature of 900 to 1200° C. is carried out in a reducing atmosphere. The surface of the crystalline semiconductor thin film is extremely flattened through this step, defects in crystal grains and crystal grain boundaries disappear, and the single crystal semiconductor thin film or substantially single crystal semiconductor thin film is obtained.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: August 19, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Tamae Takano
  • Patent number: 8803207
    Abstract: In one general aspect, an apparatus can include a trench disposed in a semiconductor region, a shield dielectric layer lining a lower portion of a sidewall of the trench and a bottom surface of the trench, and a gate dielectric lining a upper portion of the sidewall of the trench. The apparatus can also include a shield electrode disposed in a lower portion of the trench and insulated from the semiconductor region by the shield dielectric layer, and an inter-electrode dielectric (IED) disposed in the trench over the shield electrode where the shield electrode has a curved top surface.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: August 12, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Thomas E. Grebs, Nathan Lawrence Kraft, Rodney Ridley, Gary M. Dolny, Joseph A. Yedinak, Christopher Boguslaw Kocon, Ashok Challa
  • Patent number: 8796130
    Abstract: A method patterns a polysilicon gate over two immediately adjacent, opposite polarity transistor devices. The method patterns a mask over the polysilicon gate. The mask has an opening in a location where the opposite polarity transistor devices abut one another. The method then removes some (a portion) of the polysilicon gate through the opening to form at least a partial recess (or potentially a complete opening) in the polysilicon gate. The recess separates the polysilicon gate into a first polysilicon gate and a second polysilicon gate. After forming the recess, the method dopes the first polysilicon gate using a first polarity dopant and dopes the second polysilicon gate using a second polarity dopant having an opposite polarity of the first polarity dopant.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Russell T. Herrin, Mark D. Jaffe, Laura J. Schutz
  • Patent number: 8796124
    Abstract: The present disclosure provides a method to dope fins of a semiconductor device. The method includes forming a first doping film on a first fin and forming a second doping film on the second fin. The first and second doping films include a different dopant type (e.g., n-type and p-type). An anneal process is performed which drives a first dopant from the first doping film into the first fin and drives a second dopant from the second doping film into the second fin. In an embodiment, the first and second dopants are driven into the sidewall of the respective fin.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: August 5, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Pei-Ren Jeng
  • Patent number: 8796128
    Abstract: A structure and method for forming a dual metal fill and dual threshold voltage for replacement gate metal devices is disclosed. A selective deposition process involving titanium and aluminum is used to allow formation of two adjacent transistors with different fill metals and different workfunction metals, enabling different threshold voltages in the adjacent transistors.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: Lisa F. Edge, Nathaniel Berliner, James John Demarest, Balasubramanian S. Haran, Raymond J. Donohue
  • Patent number: 8796778
    Abstract: Apparatuses and methods for transposing select gates, such as in a computing system and/or memory device, are provided. One example apparatus can include a group of memory cells and select gates electrically coupled to the group of memory cells. The select gates are arranged such that a pair of select gates are adjacent to each other along a first portion of each of the pair of select gates and are non-adjacent along a second portion of each of the pair of select gates.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: August 5, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Patent number: 8791003
    Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate and forming a gate structure on the semiconductor substrate. The gate includes a high-k dielectric material. In the method, a fluorine-containing liquid is contacted with the high-k dielectric material and fluorine is incorporated into the high-k dielectric material.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: July 29, 2014
    Assignee: Globalfoundries, Inc.
    Inventors: Dina Triyoso, Elke Erben, Robert Binder