STACKED INTEGRATED CIRCUIT PACKAGES THAT INCLUDE MONOLITHIC CONDUCTIVE VIAS
Microelectronic packages are fabricated by stacking integrated circuits upon one another. Each integrated circuit includes a semiconductor layer having microelectronic devices and a wiring layer on the semiconductor layer having wiring that selectively interconnects the microelectronic devices. After stacking, a via is formed that extends through at least two of the integrated circuits that are stacked upon one another. Then, the via is filled with conductive material that selectively electrically contacts the wiring. Related microelectronic packages are also described.
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This application is a continuation of U.S. patent application Ser. No. 13/359,047, filed Jan. 26, 2012, which itself is a continuation of U.S. patent application Ser. No. 12/606,799, filed Oct. 27, 2009, which itself claims priority under 35 USC §119 to Korean Patent Application No. 10-2008-0107855, filed on Oct. 31, 2008, the disclosures of all of which are hereby incorporated herein by reference in their entirety as if set forth fully herein.
BACKGROUND OF THE INVENTIONThis invention relates to methods of packaging integrated circuits and integrated circuits so packaged, and more particularly to methods of stacking integrated circuits to form three-dimensional (3D) microelectronic packages and microelectronic packages so formed.
Integrated circuits are widely used in consumer, commercial and other applications to provide memory devices, logic devices, processor devices, sensor devices, electro-optical devices and many other microelectronic devices. Integrated circuits generally include therein large numbers of active and passive devices. An integrated circuit generally includes at least one single element and/or compound semiconductor layer. The semiconductor layer may also include a single element and/or compound semiconductor substrate, and one or more epitaxial layers. Active devices are generally formed in the semiconductor layer. A wiring layer is also provided on the semiconductor layer to provide a wiring pattern that is used to interconnect the semiconductor devices that are in the semiconductor layer and/or to provide input/output (I/O) connections to devices that are external of the integrated circuit. The wiring layer may include one or more wiring patterns that are insulated from one another and from the semiconductor layer by one or more insulating layers.
The integration density of integrated circuits continues to increase, so that more and more active and passive devices may be provided in a given integrated circuit. Additional integration density may also be provided by stacking integrated circuit substrates upon one another to provide stacked or three-dimensional (3D) integrated circuit structures. More specifically, integrated circuits may be stacked upon one another, face-to-face. These stacked devices may decrease the wiring lengths and may provide high packing density, high speed operation, low power consumption, low cost, and/or parallel processing. Stacked integrated circuits generally include a conductive via that extends through a given integrated circuit, so that both faces of the integrated circuit may be connected to other devices. Since integrated circuits often include a silicon semiconductor layer, these conductive vias that extend through the integrated circuit are often referred to as “through-silicon vias” (TSVs).
As is well known to those having skill in the art, integrated circuits are generally fabricated as wafers, in which tens, hundreds or more chips are fabricated and then singulated into individual chips. The active/passive devices may be formed in the integrated circuits at the wafer stage, and the wiring layers may also be formed on the semiconductor layer at the wafer stage. Through-silicon vias may be fabricated in the integrated circuits at the wafer stage as well, prior to forming the active devices therein and/or after forming the active devices therein. The wafers, including the through-silicon vias may then be bonded together and stacked.
SUMMARY OF THE INVENTIONMicroelectronic packages may be fabricated, according to various embodiments, by stacking of plurality of integrated circuits upon one another. A respective integrated circuit includes a semiconductor layer having active microelectronic devices therein and a wiring layer on the semiconductor layer having wiring that selectively interconnects the active microelectronic devices. After stacking, a via is formed that extends through at least two of the plurality of integrated circuits that are stacked upon one another, including through the semiconductor layers and through the wiring layers thereof. Then, after forming the via that extends through at least two the plurality of integrated circuits that are stacked upon one another, the via is filled with conductive material that selectively electrically contacts the wiring. In some embodiments, the wiring includes input/output pads and the via is filled to selectively electrically contact the input/output pads. Accordingly, vias are formed and filled after stacking the integrated circuits upon one another, which can thereby reduce the cost and/or complexity of the fabrication process.
In some embodiments, the via is a linear via that extends through at least two of the plurality of integrated circuits including through the semiconductor layers and through the wiring layers thereof, to define a continuous sidewall in the plurality of integrated circuits. The sidewalls of the semiconductor layers are then recessed relative to the wiring layers. In other embodiments, an insulating layer is formed on the recessed sidewalls of the semiconductor layers. The insulating layer may be formed on the recessed sidewalls of the semiconductor layers by forming an insulating layer on the sidewalls of the wiring layers and on the recessed sidewalls of the semiconductor layers, and then removing the insulating layer from the sidewalls of the wiring layers. More specifically, the sidewalls of the semiconductor layers may be recessed relative to the wiring layers by wet etching the semiconductor layers and wiring layers using an etchant that selectively etches the semiconductor layers relative to the wiring layers. Moreover, the insulating layer may be formed using low-temperature plasma oxide deposition.
In still other embodiments, stepped vias may be formed and filled. In particular, in some embodiments, a first and a second integrated circuit are stacked upon one another, such that the wiring layer of the first integrated circuit is adjacent the substrate of the second integrated circuit. A stepped via is then formed that recesses a sidewall of the semiconductor layer of the second integrated circuit relative to a sidewall of the wiring layer of the first integrated circuit, so as to expose a portion of the wiring of the first integrated circuit. The via is then filled with conductive material that selectively electrically contacts the portion of the wiring of the first integrated circuit. In some of these embodiments, the wirings of the first and second integrated circuits are laterally offset from one another, so that the stepped via may be formed by etching the wiring layer of the second and first integrated circuits using the laterally offset wiring of the first integrated circuit as an etch mask. Moreover, in some of these offset via embodiments, an insulating layer may be formed on the sidewalls of the stepped via that exposes the portion of the wiring of the first integrated circuit. The insulating layer maybe formed using low temperature plasma oxide deposition and multiple masking steps.
The integrated circuits may be stacked on one another by bonding the integrated circuits to one another. In some embodiments, direct bonding of the plurality of integrated circuits may be used, for example by forming a direct oxygen bond between adjacent faces of the integrated circuits. The direct bonding may avoid the use of a glue layer between the adjacent faces of the integrated circuits, in some embodiments. In other embodiments, a glue layer may be used.
In still other embodiments, the via extends through at least two of the plurality of integrated circuits that are stacked upon one another, but only extends partially through an outermost semiconductor layer of a first one of the plurality of integrated circuits. After filling the via, the outermost semiconductor layer of the first one of the plurality of integrated circuits is then thinned to expose the via that is filled.
In still other embodiments, the stacking, forming a via and filling the via may be performed on the integrated circuits at a wafer level. Thus, in some embodiments, a plurality of integrated circuit wafers are stacked upon one another. Then, a via that extends through at least two of the plurality of integrated circuit wafers is formed. Linear vias, stepped vias, direct bonding and other techniques that were described above may be employed. After filling the via, the stacked integrated circuit wafers having the filled via are diced.
Microelectronic packages according to various embodiments include a plurality of integrated circuits that are stacked upon one another, wherein a respective integrated circuit includes a semiconductor layer including active microelectronic devices therein, and a wiring layer on the semiconductor layer having wiring that selectively interconnects the active microelectronic devices. A monolithic conductive via extends through the plurality of integrated circuits including through the semiconductor layers and through the wiring layers thereof. The monolithic conductive via selectively electrically contacts the wiring.
In some embodiments, the semiconductor layers include recessed sidewalls relative to the wiring layers, and an insulating layer is provided between the recessed sidewalls and the monolithic conductive via. In other embodiments, the monolithic conductive via selectively electrically contacts the wiring at the wiring layer sidewalls. In yet other embodiments, a sidewall of a semiconductor layer of a second integrated circuit is recessed relative to a sidewall of a wiring layer of a first integrated circuit, so as to expose a portion of the wiring layer of the first integrated circuit, and a stepped monolithic conductive via electrically contacts the portion of the wiring layer of the first integrated circuit. An insulating layer also may be provided between the sidewalls of the first and second integrated circuits and the monolithic conductive via. The integrated circuits may be directly attached to one another, for example by oxygen bonds and without an intervening glue layer. The integrated circuits may be integrated circuit chips, or integrated circuit wafers, and the vias may selectively interconnect input/output pads thereof.
The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. However, this invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions may be exaggerated for clarity. Like numbers refer to like elements throughout. As used herein the term “and/or” includes any and all combinations of one or more of the associated listed items and may be abbreviated as “/”.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “having,” “having,” “includes,” “including” and/or variations thereof, when used in this specification, specify the presence of stated features, regions, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, steps, operations, elements, components, and/or groups thereof.
It will be understood that when an element such as a layer or region is referred to as being “on” or extending “onto” another element (or variations thereof), it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element (or variations thereof), there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element (or variations thereof), it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element (or variations thereof), there are no intervening elements present.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, materials, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, material, region, layer or section from another element, material, region, layer or section. Thus, a first element, material, region, layer or section discussed below could be termed a second element, material, region, layer or section without departing from the teachings of the present invention.
Relative terms, such as “lower”, “back”, and “upper” may be used herein to describe one element's relationship to another element as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the structure in the Figure is turned over, elements described as being on the “backside” of substrate would then be oriented on “upper” surface of the substrate. The exemplary term “upper”, can therefore, encompasses both an orientation of “lower” and “upper,” depending on the particular orientation of the figure. Similarly, if the structure in one of the figures is turned over, elements described as “below” or “beneath” other elements would then be oriented “above” the other elements. The exemplary terms “below” or “beneath” can, therefore, encompass both an orientation of above and below. However, as used herein, and as conventionally used, the “vertical” direction is generally orthogonal to the face of the substrate regardless of its orientation, whereas the “horizontal” direction is generally parallel to (extending along) the face of the substrate. Moreover, as used herein, “monolithic” means constituting one undifferentiated whole. Thus, a monolithic conductive via means a conductive via that is fabricated as one single structure and constitutes one undifferentiated whole, without seams or other interrupting structures therein.
Embodiments of the present invention are described herein with reference to cross section and perspective illustrations that are schematic illustrations of idealized embodiments of the present invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as flat may, typically, have rough and/or nonlinear features. Moreover, sharp angles that are illustrated, typically, may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present invention.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Various embodiments can provide microelectronic packages and fabrication methods therefor, wherein wafers are stacked and bonded and then through-silicon vias are collectively formed in the stacked wafers. The conductive vias may be insulated from the semiconductor layers by providing a selective silicon wet etch to recess the sidewalls of the semiconductor layers, and using a low temperature plasma oxide deposition to form an insulating layer on the recessed sidewalls of the semiconductor layers. Thus, the monolithic conductive via may be insulated from the semiconductor layers, but may be electrically connected to input/output (I/O) pads in the wiring layers. Accordingly, low cost and/or reduced complexity fabrication processes may be provided.
Continuing with the description of
From a functional standpoint, the integrated circuits 100a, 200 or 300 may include identical functionality and/or different functionality. For example, each of the integrated circuits 100a, 200, 300 may be an identical memory chip in some embodiments. However, in other embodiments, at least some of the integrated circuits may have different functionalities to operate as a processor, sensor, controller, memory, optical device, etc.
The wiring layers 120, 220, 320 may include a plurality of wiring patterns therein that are used to selectively interconnect the microelectronic devices in the associated semiconductor layer. Moreover, one or more of the wiring layers may also include an input/output pad 130, 230, 330 that is used to provide a connection external of the integrated circuit 100a, 200, 300. The various wiring patterns may be insulated from one another by inter-dielectric layers of various types. Moreover, each integrated circuit may include the same number or different numbers of wiring layers.
It will also be understood that
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As described above, the base substrate 10 may be attached to the preliminary device substrate 20a using direct bonding techniques that may include silicon direct bonding or anodic bonding. In one example of silicon direct bonding, two silicon wafers may be directly attached to one another by placing the wafers face-to-face and heating an oxidizing ambient to create oxygen bonds therebetween. This bonding may take place without the need for an intervening glue layer or adhesive layer. Direct wafer bonding need not be described further herein.
In other embodiments, the base substrate 10 may be attached to the preliminary device substrate 20a using an adhesive, glue or other interlayer using, for example, epoxy bonding, eutectic bonding, polyimide bonding or other direct bonding techniques, such as thermocompressive bonding, low melting temperature glass bonding and/or other techniques.
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The I/O pads 130, 230, 330 may be vertically aligned, as shown in
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The conductive electrode 400 may be formed of the same material that is used to form the pads 130, 230, 330, in some embodiments. For example, copper (Cu) and/or aluminum (Au) may be used. The conductive electrode 400 may be formed using chemical vapor deposition (CVD) to fill the via 402, followed by planarization to remove the metal from outside the via. In other embodiments, the conductive electrode may be formed using physical vapor deposition (PVD), chemical vapor deposition (CVD) plating and/or direct electrode implantation,
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In other embodiments, the first, second and third semiconductor layers 112, 210 and 310 may be recessed before performing the heat treatment.
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Then, a conductive electrode may be formed in the via 502 and the semiconductor substrate 512, and the insulating layer 514 may be removed, as was described in connection with
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Thus, a stepped via 1202 is formed that includes the first, second and third vias 1204, 1206 and 1208. Subsequent processing may occur as was described in
The mounting substrate 600 may include an upper surface 622 adjacent the integrated circuits 700 and a lower surface 624 remote from the integrated circuits 700. A first package pad 608a is provided on the upper surface 622 and is electrically connected to a wire 612 that itself is connected to the conductive via 740. The first package pad 608a may comprise copper (Cu), aluminum (Al), nickel (Ni), platinum (Pt), silver (Ag) and/or gold (Au). The first package pad 608a may be close to an edge of the mounting substrate 600. Moreover, a second package pad 608b may be provided in an insulating layer 604 that is on the upper surface 622 of the mounting substrate 600. A plurality of second package pads 608b may be provided in an array at regular intervals in a row parallel to an edge of the mounting substrate 600 and/or in other arrangements.
A plurality of outer package pads 606 may be provided in an insulating layer 602 on the bottom surface 624 of the mounting substrate 600. One or more connection terminals 610 may be disposed on the lower surface 624 and electrically connected to the outer package pads 606. The connection terminals 610 may be solder balls or solder bumps for connection with an external device, and may comprise gold (Au), lead (Pb), silver (Ag), nickel (Ni), copper (Cu) and/or tin (Sn) alloys. For example, the connection terminal 610 may comprise Cu—Ni—Pb, Cu—Ni—Au, Cu—Ni, Ni—Au and/or Ni—Ag. The outer package pads 606 may have relatively good conductivity and may comprise copper (Cu), aluminum (Al), nickel (Ni), platinum (Pt), silver (Ag) and/or gold (Au).
In some embodiments, the integrated circuits 710, 720 and 730 may be memory integrated circuits that include a peripheral circuit region and a cell region. The integrated circuits 710, 720 and 730 may include a nonvolatile memory, a random access memory and/or other memories, such as a flash memory chip, a PRAM chip, an SRAM chip, and MRAM chip and/or a DRAM chip.
It will be understood that the various internal and external connections shown in
Many different embodiments have been disclosed herein, in connection with the above description and the drawings. It will be understood that it would be unduly repetitious and obfuscating to literally describe and illustrate every combination and subcombination of these embodiments. Accordingly, the present specification, including the drawings, shall be construed to constitute a complete written description of all combinations and subcombinations of the embodiments described herein, and of the manner and process of making and using them, and shall support claims to any such combination or subcombination.
In the drawings and specification, there have been disclosed embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.
Claims
1. A microelectronic package, comprising:
- a plurality of integrated circuits that are stacked upon one another, a respective integrated circuit including a semiconductor layer having microelectronic devices therein and a wiring layer on the semiconductor layer having wiring that selectively interconnects the microelectronic devices; and
- a monolithic conductive via that extends through the plurality of integrated circuits including through the semiconductor layers and through the wiring layers thereof, the monolithic conductive via selectively electrically contacting the wiring.
2. A microelectronic package according to claim 1 wherein the semiconductor layers include recessed sidewalls relative to the wiring layers, the microelectronic package further comprising an insulating layer between the recessed sidewalls and the monolithic conductive via.
3. A microelectronic package according to claim 1:
- wherein the plurality of integrated circuits comprises a first and a second integrated circuit that are stacked upon one another such that the wiring layer of the first integrated circuit is adjacent the semiconductor layer of the second integrated circuit;
- wherein a sidewall of the semiconductor layer of second integrated circuit is recessed relative to a sidewall of the wiring layer of the first integrated circuit so as to expose a portion of the wiring of the first integrated circuit; and
- wherein the monolithic conductive via is a stepped monolithic conductive via that electrically contacts the portion of the wiring of the first integrated circuit.
4. A microelectronic package according to claim 3 further comprising an insulating layer between the sidewalls of the first and second integrated circuits and the monolithic conductive via.
5. A microelectronic package according to claim 1 wherein the plurality of integrated circuits are directly attached to one another.
6. A microelectronic package according to claim 5 wherein the plurality of integrated circuits are directly attached to one another by oxygen bonds.
7. A microelectronic package according to claim 1 wherein the plurality of integrated circuits are directly attached to one another without an intervening glue layer.
8. A microelectronic package according to claim 1 wherein the plurality of integrated circuits comprise a plurality of integrated circuit wafers that are stacked upon one another.
9. A microelectronic package according to claim 1 wherein the wiring includes input/output pads and wherein the monolithic conductive via selectively electrically contacts the input/output pads.
10. A microelectronic package according to claim 1 wherein the plurality of integrated circuits comprise a memory integrated circuit, a memory controller integrated circuit, a processor integrated circuit and/or an input/output controller integrated circuit.
Type: Application
Filed: Oct 25, 2012
Publication Date: Feb 28, 2013
Applicant: Samsung Electronics Co., Ltd. (Suwon-si)
Inventor: Samsung Electronics Co., Ltd. (Suwon-si)
Application Number: 13/660,177
International Classification: H01L 23/48 (20060101);