DIFFUSION BARRIER AND METHOD OF FORMATION THEREOF
A method of forming a device is presented. The method includes providing a structure having first and second regions. A diffusion barrier is formed between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions.
Latest GLOBALFOUNDRIES SINGAPORE PTE. LTD. Patents:
- Photodiodes with serpentine shaped electrical junction
- High-voltage electrostatic discharge devices
- Thin film based passive devices and methods of forming the same
- Laterally-diffused metal-oxide-semiconductor devices with a multiple-thickness buffer dielectric layer
- Non-volatile memory devices with asymmetrical floating gates
The present invention relates to diffusion barriers and to a method of forming a diffusion barrier. In particular but not exclusively the invention relates to a diffusion barrier in an integrated circuit device and a method of forming a diffusion barrier in an integrated circuit device.
BACKGROUNDDiffusion of dopant atoms and other atoms in integrated circuit (IC) structures is responsible for a number of problems associated with the fabrication and long term stability of IC structures. For example, electrical characteristics of static random access memory (SRAM) structures are adversely affected by lateral diffusion in polysilicon of dopant such as phosphorus from strongly n+ doped regions. This causes N−/P+ junctions between NFET and PFET devices to shift towards the PFET device.
In order to ameliorate the problem, a shallower n+ pre-doped implant and a smaller N+implanted area have been adopted. However, substantial diffusion of dopant still occurs during subsequent thermal processing such as polysilicon reoxidation processes and rapid thermal annealing (RTA).
Furthermore, diffusion of extrinsic dopant and source/drain dopant into the channel region can occur, again resulting in an adverse effect on electrical characteristics of the structure. For example, the threshold voltage at which a channel region of a transistor device begins to conduct typically reduces with increased amounts of lateral diffusion of extrinsic and source/drain dopant. Consequently, sub-threshold leakage can be increased by several orders of magnitude.
To mitigate this problem, a reduced dose of dopant may be applied when forming a halo region, and a lower temperature employed in the course of rapid thermal annealing of the structure. However, such measures may introduce further problems such as gate induced drain leakage (GIDL) and a lack of dopant activation.
SUMMARYA method of forming a device or a semiconductor device is disclosed. The method includes providing a structure or substrate having first and second regions. The method further includes forming a diffusion barrier between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions.
In another aspect, a device that comprises a structure having first and second regions is presented. The device further includes a diffusion barrier disposed between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions.
These and other objects along with advantages and features of the present invention herein disclosed, will become apparent through reference to the following description and the accompanying drawings. Furthermore, it is to be understood that the features of the various embodiments described herein are not mutually exclusive and can exist in various combinations and permutations.
In the drawings, like reference characters generally refer to the same parts throughout the different views. Also, the drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. Various embodiments of the present invention are described with reference to the following drawings, in which:
The structure has a silicon substrate 102 having a plurality of, for example, P-type doped well regions (P-wells) 104 and a plurality of N-type doped well regions (N-wells) 106. Respective P-wells 104 and N-wells 106 are separated by shallow trench isolation (STI) regions 108.
The substrate 102 has a layer of a gate dielectric medium 110 formed thereover. In the embodiment of
The layer of gate dielectric medium 110 has a gate electrode layer 120 formed thereover. The gate electrode layer, for example, comprises polysilicon. In the embodiment of
Other substrate materials are also useful. Other thicknesses of polysilicon layer 120 are also useful. Other layer materials are also useful for forming a gate electrode instead of or in addition to polysilicon.
In some embodiments, the implant region 132 is arranged to partially span the thickness of the polysilicon layer 120. For example, non-implant regions without implant medium therein can be provided above and/or below the implant region 132. Other configurations of implant and non-implant regions are also useful. The non-implant regions can facilitate the formation of metal silicide therein.
In the embodiment of
As shown in
In the embodiment of
In one embodiment, the implant conditions are established such that implantation of atoms occurs to a depth in the range of from around at least 30% to around 70% of the thickness of the polysilicon layer 120. In some embodiments, the range of depth is around half of the thickness of the polysilicon layer 120. Other implant depths may also be useful.
In the embodiment of
Other annealing temperatures are also useful. In some embodiments, annealing is performed at a temperature in the range of from around 800° C. to around 1000° C. In some embodiments, the annealing process is performed for a period of time sufficient to form cavities 134 in the polysilicon layer 120 having a size in the range of from around 2 nm to around 60 nm. In some embodiments, portions of the polysilicon layer 120 in which cavities 134 form provide a barrier 135 to diffusion of dopant atoms in the polysilicon layer 120 from one side of the barrier 135 to the other.
In the embodiment of
It is to be understood that if the cavities 134 are formed to be too large, the polysilicon line may fail. For example, the polysilicon line may disintegrate due to fracture of polysilicon.
It is also to be understood that the depth at which the cavities 134 may be formed is dependent on the depth of the structure to which the implant medium is implanted.
In the embodiment of
The gate electrode and dielectric layers can be patterned to form gate conductors. In one embodiment, the gate electrode and dielectric layers are patterned to form a gate conductor passing through the N well and P well. Additional processes for completing transistors can be performed.
The embodiment of
In the structure of
For structures formed using 45 nm feature size technologies, an implant energy in the range of from around 4 keV to around 7 keV is used, and a dose of from around 1014 to 5×1015 cm −2 is provided.
The gate electrode 270 is formed from polysilicon by a process of blanket layer formation followed by a process of patterning and etching.
Subsequently, second spacer elements 274 have been formed on the first spacer elements 272 and deep source and drain regions 284, 264 respectively formed by implantation of dopant atoms.
The structure of
Other thicknesses of layers comprised by the mask member 350 are also useful. In some embodiments, the mask member is formed from a polymer-based photoresist material. Other photoresist materials are also useful.
In some embodiments, implantation of the implant medium is performed at an energy in the range of from around 2 keV to around 100 keV, and at a dose of around 1×1013 to around 5×1015cm−2.
Following implantation, the structure 300 is annealed at a temperature of 800° C. to form cavities 334 in the substrate 302 in a similar manner to that described above with respect to other embodiments of the invention. Other temperatures are also useful, as discussed in respect of other embodiments of the invention.
The structure is configured whereby the cavities provide a diffusion barrier 335 in a region of the substrate immediately below a channel region 380 of the structure.
In a subsequent step, a blanket layer of polysilicon 370 as shown in
The resulting structure 300 of
A gate electrode 470 has been formed over a channel region 480 of the structure. In the embodiment of
Implant regions 432 have been formed in the substrate 402 below source and drain regions of the structure by implantation of an implant medium as described above with respect to other embodiments. The capping layer 473 and first spacer elements 472 mask the channel region 480 of the substrate 402 from the implant medium in a similar manner to the mask member 350 of the embodiment of
It will be appreciated that implantation of source and drain dopant atoms may be performed before or after formation of the barrier regions 435. In the embodiment of
In the embodiment of
In embodiments of the invention in which FET devices are formed, the dopant medium used to form source and drain halo regions and deep source and drain regions may be an n-type dopant medium in the case of the formation of an NFET device or a p-type dopant medium in the case of formation of a PFET device.
It is understood that various embodiments of diffusion barriers can be combined, such as any two or more embodiments. For example, a diffusion barrier below the channel (as shown in
Some embodiments of the invention have the advantage that electrical properties of transistor devices of an integrated circuit structure are improved relative to integrated circuit structures not having diffusion barriers according to one or more embodiments of the invention. This is at least in part because in some embodiments of the invention an amount of diffusion of dopant atoms from one region of a device structure to another region is substantially reduced.
Throughout the description and claims of this specification, the words “comprise” and “contain” and variations of the words, for example “comprising” and “comprises”, means “including but not limited to”, and is not intended to (and does not) exclude other moieties, additives, components, integers or steps.
Throughout the description and claims of this specification, the singular encompasses the plural unless the context otherwise requires. In particular, where the indefinite article is used, the specification is to be understood as contemplating plurality as well as singularity, unless the context requires otherwise.
Features, integers and characteristics described in conjunction with a particular aspect, embodiment or example of the invention are to be understood to be applicable to any other aspect, embodiment or example described herein unless incompatible therewith.
The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The foregoing embodiments, therefore, are to be considered in all respects illustrative rather than limiting the invention described herein. Scope of the invention is thus indicated by the appended claims, rather than by the foregoing description, and all changes that come within the meaning and range of equivalency of the claims are intended to be embraced therein.
Claims
1-20. (canceled)
21. A method for forming a device comprising:
- providing a substrate;
- forming a gate structure over the substrate;
- forming first and second diffusion regions in the substrate on opposed sides of the gate structure;
- forming at least one diffusion barrier having cavities in the substrate, wherein the diffusion barrier abuts ends of the first and second diffusion regions, the diffusion barrier reduces out-diffusion of dopants from the first and second diffusion regions.
22. The method of claim 21 wherein the diffusion barrier abuts bottom ends of the first and second diffusion regions.
23. The method of claim 22 comprising:
- forming a plurality of shallow trench isolation (STI) regions in the substrate.
24. The method of claim 23 wherein the diffusion barrier spans a substantial distance from one STI region to another adjacent STI region.
25. The method of claim 24 wherein forming the diffusion barrier comprises:
- implanting an implant medium in the substrate to form an implant region of which the diffusion barrier is to be formed; and
- annealing the implant region to form the cavities.
26. The method of claim 25 wherein the implant medium comprises He, hydrogen, argon atoms or a combination thereof.
27. The method of claim 24 wherein forming the first and second diffusion regions comprises:
- forming spacers adjacent to sidewalls of the gate structure; and
- implanting the dopants to form the first and second diffusion regions.
28. The method of claim 21 wherein the diffusion barrier comprises:
- first and second diffusion barriers, wherein the first diffusion barrier abuts a bottom of the first diffusion region and the second diffusion barrier abuts a bottom of the second diffusion barriers.
29. The method of claim 28 wherein forming diffusion barrier is performed after forming the gate structure.
30. The method of claim 28 comprising:
- providing a capping layer over the gate structure; and
- forming spacers adjacent to sidewalls of the gate structure.
31. The method of claim 30 wherein forming the diffusion barrier comprises:
- implanting an implant medium in the substrate to form an implant region of which the diffusion barrier is to be formed, wherein the spacers and the capping layer mask a channel region below the gate structure from the implant medium; and
- annealing the implant region to form the cavities.
32. The method of claim 31 wherein the implant medium comprises He, hydrogen, argon atoms or a combination thereof.
33. A method for forming a device comprising:
- providing a substrate;
- forming a gate structure over the substrate;
- forming first and second diffusion regions in the substrate on opposed sides of the gate structure;
- forming a diffusion barrier having cavities in the substrate, wherein the diffusion barrier is disposed in between the first and second diffusion regions, the diffusion barrier reduces out-diffusion of dopants from the first and second diffusion regions.
34. The method of claim 33 wherein the diffusion barrier is formed immediately below a channel region which is disposed below the gate structure.
35. The method of claim 34 wherein the diffusion barrier is formed at a depth corresponding to lower portions of the first and second diffusion regions.
36. The method of claim 34 wherein forming the diffusion barrier comprises:
- providing a mask on top of the substrate, the mask comprises a cavity that exposes a portion of a top surface of the substrate of which the gate structure is to be formed;
- implanting an implant medium in the portion exposed by the cavity to form an implant region below a portion of the substrate which forms the channel region; and
- annealing the implant region to form the cavities.
37. The method of claim 36 wherein the implant medium comprises He, hydrogen, argon atoms or a combination thereof.
38. A device comprising:
- a substrate;
- a gate structure disposed on the substrate;
- first and second diffusion regions disposed in the substrate on opposed sides of the gate structure;
- at least one diffusion barrier having cavities disposed in the substrate, wherein the at least one diffusion barrier abuts ends of the first and second diffusion regions, the diffusion barrier reduces out-diffusion of dopants from the first and second diffusion regions.
39. The device of claim 38 comprising:
- a plurality of shallow trench isolation (STI) regions in the substrate, wherein the diffusion barrier spans a substantial distance from one STI region to another adjacent STI region.
40. The device of claim 39 wherein the diffusion barrier abuts bottom ends of the first and second diffusion regions.
Type: Application
Filed: Nov 29, 2012
Publication Date: Apr 11, 2013
Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD. (Singapore)
Inventor: GLOBALFOUNDRIES Singapore Pte. Ltd. (Singapore)
Application Number: 13/688,229
International Classification: H01L 29/66 (20060101); H01L 23/532 (20060101);