Implanting To Form Insulator Patents (Class 438/423)
  • Patent number: 10867910
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a conductive feature over the semiconductor substrate. The semiconductor device structure also includes a dielectric layer over the conductive feature and the semiconductor substrate. The semiconductor device structure further includes a conductive via surrounded by the dielectric layer and electrically connected to the conductive feature. The conductive via has a side surface extending from a topmost surface of the dielectric layer to a bottommost surface of the dielectric layer, and the side surface of the conductive via curves inward. An entirety of the side surface is in direct contact with the first dielectric layer.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Tai-Yen Peng
  • Patent number: 10777551
    Abstract: A semiconductor device includes a substrate including a first region and a second region, a first transistor and a second transistor formed in the first region and second region, respectively, wherein the first transistor includes a thick gate insulating layer and a thin buffer insulating layer formed in the substrate, a first gate electrode formed on the thick gate insulating layer, a first spacer formed on the thin buffer insulating layer, and a source region and a drain region formed in the substrate.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: September 15, 2020
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Young Bae Kim, Kwang Il Kim, Jun Hyun Kim, In Sik Jung, Jae Hyung Jang, Jin Yeong Son
  • Patent number: 9935197
    Abstract: Semiconductor devices with low junction capacitances and methods of fabrication thereof are described. In one embodiment, a method of forming a semiconductor device includes forming isolation regions in a substrate to form active areas. The sidewalls of the active areas are enclosed by the isolation regions. The isolation regions are recessed to expose first parts of the sidewalls of the active areas. The first parts of the sidewalls of the active areas are covered with spacers. The isolation regions are etched to expose second parts of the sidewalls of the active area, the second parts being disposed below the first parts. The active areas are etched through the exposed second parts of the sidewalls to form lateral openings. The lateral openings are filled with a spin on dielectric.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hung Chang, Yu-Rung Hsu, Chen-Hua Yu
  • Patent number: 9129892
    Abstract: A vertical super junction MOSFET and a lateral MOSFET are integrated on the same semiconductor substrate. The lateral MOSFET is electrically isolated from the vertical super junction MOSFET by an n-buried isolating layer and an n-diffused isolating layer. The lateral MOSFET is formed of a p-well region formed in an n? semiconductor layer bounded by the n-buried isolating layer and n-diffused isolating layer, an n-source region and n-drain region formed in the p-well region, and a gate electrode that covers a portion of the p-well region sandwiched by the n-source region and n-drain region. As the n-buried isolating layer is formed at the same time as an n-layer (3) of the vertical super junction MOSFET, it is possible to reduce cost. Also, it is possible to suppress parasitic action between the elements with the n-buried isolating layer.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: September 8, 2015
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yoshiaki Toyoda, Akio Kitamura
  • Patent number: 9093477
    Abstract: An implantation processing step includes the following steps for a recess in a FinFET. At least a fin structure is formed on a substrate. A gate is formed across the fin structure. A recess is formed in the fin structure beside the gate. An angle anti-punch through implant is performed to form an embedded layer in the fin structure right below the gate. An angle barrier implant is performed to form a barrier liner in the fin structure surrounding the recess. A junction implant is performed to form a junction doped region in the fin structure below the recess.
    Type: Grant
    Filed: November 9, 2014
    Date of Patent: July 28, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ting Lin, Chia-Jong Liu
  • Patent number: 9087851
    Abstract: Silicon-based circuitry is dissolved or otherwise disabled in a controlled manner by reactive materials provided beneath the insulating layer on which the circuitry is formed. Heat and/or light induced acid generating materials are provided for corroding one or more circuitry components. Additionally and/or alternatively, gas-producing materials are deposited in compartments beneath the insulating layer. The gas-producing materials cause pressure to rise within the compartments, damaging the chip. Chemical reactions within the chip may be facilitated by heating elements and/or light generating elements embedded within the chip and actuated by triggering circuits.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: July 21, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, Bahman Hekmatshoartabari, Ali Khakifirooz, Davood Shahrjerdi
  • Patent number: 9087852
    Abstract: Silicon-based circuitry is dissolved or otherwise disabled in a controlled manner by reactive materials provided beneath the insulating layer on which the circuitry is formed. Heat and/or light induced acid generating materials are provided for corroding one or more circuitry components. Additionally and/or alternatively, gas-producing materials are deposited in compartments beneath the insulating layer. The gas-producing materials cause pressure to rise within the compartments, damaging the chip. Chemical reactions within the chip may be facilitated by heating elements and/or light generating elements embedded within the chip and actuated by triggering circuits.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: July 21, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, Bahman Hekmatshoartabari, Ali Khakifirooz, Davood Shahrjerdi
  • Patent number: 9059245
    Abstract: Semiconductor-on-insulator (SOI) substrates including a buried oxide (BOX) layer having a thickness of less than 300 ? are provided. The (SOI) substrates having the thin BOX layer are provided using a method including a step in which oxygen ions are implanted at high substrate temperatures (greater than 600° C.), and at a low implant energy (less than 40 keV). An anneal step in an oxidizing atmosphere follows the implant step and is performed at a temperature less than 1250° C. The anneal step in oxygen containing atmosphere converts the region containing implanted oxygen atoms formed by the implant step into a BOX having a thickness of less than 300 ?. In some instances, the top semiconductor layer of the SOI substrate has a thickness of less than 300 ?.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: June 16, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tze-Chiang Chen, Joel P. de Souza, Devendra K. Sadana, Ghavam G. Shahidi
  • Patent number: 8999811
    Abstract: An insulating layer containing a silicon peroxide radical is used as an insulating layer in contact with an oxide semiconductor layer for forming a channel. Oxygen is released from the insulating layer, whereby oxygen deficiency in the oxide semiconductor layer and an interface state between the insulating layer and the oxide semiconductor layer can be reduced. Accordingly, a semiconductor device where reliability is high and variation in electric characteristics is small can be manufactured.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: April 7, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Endo, Toshinari Sasaki, Kosei Noda, Mizuho Sato
  • Publication number: 20150064874
    Abstract: FinFET structures with dielectric fins and methods of fabrication are disclosed. A gas cluster ion beam (GCIB) tool is used to apply an ion beam to exposed fins, which converts the fins from a semiconductor material such as silicon, to a dielectric such as silicon nitride or silicon oxide. Unlike some prior art techniques, where some fins are removed prior to fin merging, in embodiments of the present invention, fins are not removed. Instead, semiconductor (silicon) fins are converted to dielectric (nitride/oxide) fins where it is desirable to have isolation between groups of fins that comprise various finFET devices on an integrated circuit (IC).
    Type: Application
    Filed: October 30, 2014
    Publication date: March 5, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Balasubramanian S. Haran, Ali Khakifirooz, Shom Ponoth, Theodorus Eduardus Standaert, Tenko Yamashita
  • Patent number: 8969997
    Abstract: A method of forming of a semiconductor structure has isolation structures. A substrate having a first region and a second region is provided. The first region and the second region are implanted with neutral dopants to form a first etching stop feature and a second stop feature in the first region and the second region, respectively. The first etching stop feature has a depth D1 and the second etching stop feature has a depth D2. D1 is less than D2. The substrate in the first region and the second region are etched to form a first trench and a second trench respectively. The first trench and the second trench land on the first etching stop feature and the second etching stop feature, respectively.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chang-Sheng Tsao
  • Patent number: 8951882
    Abstract: A method of fabricating an optoelectronic integrated circuit substrate includes defining a photonic device region on a first substrate, the photonic device region having a photonic device formed thereon, forming a trench in the photonic device region on a top surface of the first substrate, the trench having a first depth, filling the trench with a dielectric, bonding a second substrate on the first substrate to cover the trench, and thinning the second substrate to a first thickness.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seong-ho Cho
  • Patent number: 8912612
    Abstract: A FinFET structure which includes: silicon fins on a semiconductor substrate, each silicon fin having two sides and a horizontal surface; a gate wrapping around at least one of the silicon fins, the gate having a first surface and an opposing second surface facing the at least one of the silicon fins; a hard mask on a top surface of the gate; a silicon nitride layer formed in each of the first and second surfaces so as to be below and in direct contact with the hard mask on the top surface of the gate; spacers on the gate and in contact with the silicon nitride layer; and epitaxially deposited silicon on the at least one of the silicon fins so as to form a raised source/drain.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Sanjay Mehta, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 8906759
    Abstract: A method of forming a FinFET structure which includes forming fins on a semiconductor substrate; forming a gate wrapping around at least one of the fins, the gate having a first surface and an opposing second surface facing the fins; depositing a hard mask on a top of the gate; angle implanting nitrogen into the first and second surfaces of the gate so as to form a nitrogen-containing layer in the gate that is below and in direct contact with the hard mask on top of the gate; forming spacers on the gate and in contact with the nitrogen-containing layer; and epitaxially depositing silicon on the at least one fin so as to form a raised source/drain. Also disclosed is a FinFET structure.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Sanjay Mehta, Tenko Yamashita, Chun-Chen Yeh
  • Publication number: 20140349463
    Abstract: The present invention provides a method for improving anti-radiation performance of SOI structure comprising following steps: implementing particle implantations of high-energy neutrons, protons and ?-rays to an SOI structure, and then performing annealing process. The present invention aims to improving anti-radiation performance of SOI devices by means of introducing displacement damage into a buried oxide layer through implantation of high-energy particles.
    Type: Application
    Filed: October 25, 2012
    Publication date: November 27, 2014
    Inventors: Yinxue Lv, Jinshun Bi, Jiajun Luo, Zhengsheng Han, Tianchun Ye
  • Publication number: 20140252504
    Abstract: A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 11, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd
  • Publication number: 20140246752
    Abstract: Disclosed are guard ring structures with an electrically insulated gap in a substrate to reduce or eliminate device coupling of integrated circuit chips, methods of manufacture and design structures. The method includes forming a guard ring structure comprising a plurality of metal layers within dielectric layers. The method further includes forming diffusion regions to electrically insulate a gap in a substrate formed by segmented portions of the guard ring structure.
    Type: Application
    Filed: March 1, 2013
    Publication date: September 4, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert L. Barry, Phillip F. Chapman, Jeffrey P. Gambino, Michael L. Gautsch, Mark D. Jaffe, Kevin N. Ogg, Bradley A. Orner
  • Patent number: 8815701
    Abstract: A semiconductor device includes: a SOI substrate including a support layer, a first insulation film and a SOI layer; a first circuit; a second circuit; and a trench separation element. The SOI substrate further includes a first region and a second region. The first region has the support layer, the first insulation film and the SOI layer, which are stacked in this order, and the second region has only the support layer. The trench separation element penetrates the support layer, the first insulation film and the SOI layer. The trench separation element separates the first region and the second region. The first circuit is disposed in the SOI layer of the first region. The second circuit is disposed in the support layer of the second region.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: August 26, 2014
    Assignee: Denso Corporation
    Inventors: Masakiyo Sumitomo, Makoto Asai, Nozomu Akagi, Yasuhiro Kitamura, Hiroki Nakamura, Tetsuo Fujii
  • Patent number: 8785290
    Abstract: A method for manufacturing a semiconductor device, the method comprising, forming an opening in an insulating layer, which is formed on a semiconductor substrate, using a photoresist pattern formed on the insulating layer as a mask, forming a first element isolation portion in the semiconductor substrate by implanting an ion into the semiconductor substrate using the photoresist pattern as a mask, forming a second element isolation portion, in the semiconductor substrate, whose outer edge is outside an outer edge of the opening, by implanting an ion into the semiconductor substrate through the opening, and forming a third element isolation portion, which is inside the outer edge of the second element isolation portion, by embedding an insulating member in the opening and removing the insulating layer.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: July 22, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hiroaki Naruse
  • Patent number: 8778771
    Abstract: A method of manufacturing a semiconductor device includes steps of providing a substrate including a semiconductor portion, a non-porous semiconductor layer, and a porous semiconductor layer arranged between the semiconductor portion and the non-porous semiconductor layer, forming a porous oxide layer by oxidizing the porous semiconductor layer, forming a bonded substrate by bonding a supporting substrate to a surface, on a side of the non-porous semiconductor layer, of the substrate on which the porous oxide layer is formed, and separating the semiconductor portion from the bonded substrate by utilizing the porous oxide layer.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: July 15, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kazuo Kokumai
  • Patent number: 8772110
    Abstract: In a semiconductor device, a thin wall oxide film formed over sidewalls of an active region is formed, and a portion of the wall oxide film adjacent to a gate region is removed. A gate insulating film is formed where the portion of wall oxide film was removed to prevent a parasitic transistor from being generated by the wall oxide film.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: July 8, 2014
    Assignee: SK Hynix Inc.
    Inventor: Seung Joo Baek
  • Patent number: 8748204
    Abstract: Isolation of III-nitride devices may be performed with a dopant selective etch that provides a smooth profile with little crystal damage in comparison to previously used isolation techniques. The dopant selective etch may be an electro-chemical or photo-electro-chemical etch. The desired isolation area may be identified by changing the conductivity type of the semiconductor material to be etched. The etch process can remove a conductive layer to isolate a device atop the conductive layer. The etch process can be self stopping, where the process automatically terminates when the selectively doped semiconductor material is removed.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: June 10, 2014
    Assignee: International Rectifier Corporation
    Inventor: Paul Bridger
  • Patent number: 8728904
    Abstract: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: May 20, 2014
    Assignee: Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan
  • Patent number: 8710479
    Abstract: According to example embodiments, there is provided a semiconductor device including a substrate and an isolation layer structure. The substrate includes an active region having an upper active pattern and a lower active pattern on the upper active pattern. The active region has a first aspect ratio larger than about 13:1 and a second aspect ratio smaller than about 13:1. The first aspect ratio is defined as a ratio of a sum of heights of the upper active pattern and the lower active pattern with respect to a width of the upper active pattern. The second aspect ratio is defined as a ratio of the sum of the heights of the upper active pattern and the lower active pattern with respect to a width of the lower active pattern. The isolation layer structure is adjacent to the active region.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: April 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Won Kim, Yong-Kwan Kim
  • Patent number: 8679903
    Abstract: A method is provided for fabricating a vertical insulated gate transistor. A horizontal isolation region is formed in a substrate to separate and electrically isolate upper and lower portions of the substrate. A vertical semiconductor pillar with one or more flanks and a cavity is formed so as to rest on the upper portion, and a dielectrically isolated gate is formed so as to include an internal portion within the cavity and an external portion resting on the flanks and on the upper portion. One or more internal walls of the cavity are coated with an isolating layer and the cavity is filled with a gate material so as to form the internal portion of the gate within the cavity and the external portion of the gate that rests on the flanks, and to form two connecting semiconductor regions extending between source and drain regions of the transistor.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: March 25, 2014
    Assignee: STMicroelectronics, Inc.
    Inventor: Richard A. Blanchard
  • Publication number: 20140061798
    Abstract: A microelectronic device including: a substrate including a first semiconductor layer positioned on a dielectric layer and a second semiconductor layer, an isolation trench made through the first semiconductor layer, the dielectric layer and a part of the thickness of the second semiconductor layer, including at least one dielectric material and delimiting, in the first semiconductor layer, at least one rectangular active area of the device, and in which, in said part of the thickness of the second semiconductor layer, at least one portion of dielectric material of the isolation trench is positioned under the active area by forming two side walls, two other side walls of the isolation trench being not arranged under the active area.
    Type: Application
    Filed: September 4, 2013
    Publication date: March 6, 2014
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT
    Inventors: Maud VINET, Laurent Grenouillet, Yannick Le Tiec, Romain Wacquez
  • Patent number: 8658513
    Abstract: An improved method of creating LED arrays is disclosed. A p-type layer, multi-quantum well and n-type layer are disposed on a substrate. The device is then etched to expose portions of the n-type layer. To create the necessary electrical isolation between adjacent LEDs, an ion implantation is performed to create a non-conductive implanted region. In some embodiments, an implanted region extends through the p-type layer, MQW and n-type layer. In another embodiment, a first implanted region is created in the n-type layer. In addition, a second implanted region is created in the p-type layer and multi-quantum well immediately adjacent to etched n-type layer. In some embodiments, the ion implantation is done perpendicular to the substrate. In other embodiments, the implant is performed at an angle.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: February 25, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Fareen Adeni Khaja, Deepak Ramappa, San Yu, Chi-Chun Chen
  • Patent number: 8652887
    Abstract: The present invention relates to a method for providing a Silicon-On-Insulator (SOI) stack that includes a substrate layer, a first oxide layer on the substrate layer and a silicon layer on the first oxide layer (BOX layer). The method includes providing at least one first region of the SOI stack wherein the silicon layer is thinned by thermally oxidizing a part of the silicon layer and providing at least one second region of the SOI stack wherein the first oxide layer (BOX layer) is thinned by annealing.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: February 18, 2014
    Assignee: Soitec
    Inventors: Bich-Yen Nguyen, Carlos Mazure, Richard Ferrant
  • Publication number: 20130320483
    Abstract: Semiconductor-on-insulator (SOI) substrates including a buried oxide (BOX) layer having a thickness of less than 300 ? are provided. The (SOI) substrates having the thin BOX layer are provided using a method including a step in which oxygen ions are implanted at high substrate temperatures (greater than 600° C.), and at a low implant energy (less than 40 keV). An anneal step in an oxidizing atmosphere follows the implant step and is performed at a temperature less than 1250° C. The anneal step in oxygen containing atmosphere converts the region containing implanted oxygen atoms formed by the implant step into a BOX having a thickness of less than 300 ?. In some instances, the top semiconductor layer of the SOI substrate has a thickness of less than 300 ?.
    Type: Application
    Filed: May 30, 2012
    Publication date: December 5, 2013
    Applicant: International Business Machines Corporation
    Inventors: Tze-Chiang Chen, Joel P. de Souza, Devendra K. Sadana, Ghavam G. Shahidi
  • Publication number: 20130320460
    Abstract: In a semiconductor device, a thin wall oxide film formed over sidewalls of an active region is formed, and a portion of the wall oxide film adjacent to a gate region is removed. A gate insulating film is formed where the portion of wall oxide film was removed to prevent a parasitic transistor from being generated by the wall oxide film.
    Type: Application
    Filed: December 20, 2012
    Publication date: December 5, 2013
    Applicant: SK HYNIX INC.
    Inventor: Seung Joo BAEK
  • Patent number: 8587039
    Abstract: A semiconductor device is formed in a semiconductor layer. A gate stack is formed over the semiconductor layer and comprises a first conductive layer and a second layer over the first layer. The first layer is more conductive and provides more stopping power to an implant than the second layer. A species is implanted into the second layer. Source/drain regions are formed in the semiconductor layer on opposing sides of the gate stack. The gate stack is heated after the step of implanting to cause the gate stack to exert stress in the semiconductor layer in a region under the gate stack.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: November 19, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Brian A. Winstead, Konstantin V. Loiko, Voon-Yew Thean
  • Patent number: 8569833
    Abstract: The present invention discloses an LDMOS device structure, including a MOS transistor cell, wherein an isolation region is formed on each outer side of both a source region and a drain region of the MOS transistor cell; each isolation region includes a plurality of isolation trenches and isolates the MOS transistor cell from its surroundings; the height of the isolation region is smaller than that of a gate of the MOS transistor cell. The present invention also discloses a manufacturing method of the LDMOS device structure, including forming isolation trenches by lithography and etching processes, then forming isolation regions of SiO2 by depleting silicon between isolation trenches through high-temperature drive-in. The present invention can reduce parasitic capacitance, surface unevenness and difficulty of subsequent process and realize the production of small-size gate devices by forming a thicker field oxide layer and a gap structure of isolation trenches.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: October 29, 2013
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventors: Shuai Zhang, Haijun Wang
  • Publication number: 20130234280
    Abstract: A manufacturing method of STI in DRAM includes the following steps. Step 1 is providing a substrate and step 2 is forming at least one trench in the substrate. Step 3 is doping at least one of side portions and bottom portions of the trench with a dopant. Step 4 is forming an oxidation inside the trench and step 5 is providing a planarization step to remove the oxidation. The stress of the corners of STI is reduced so as to modify the defect of the substrate and improve the DRAM variability in retention time.
    Type: Application
    Filed: March 16, 2012
    Publication date: September 12, 2013
    Applicant: INOTERA MEMORIES, INC.
    Inventors: ARVIND KUMAR, ERIC LAHAUG, DEVESH KUMAR DATTA, KEEN WAH CHOW, CHIA MING YANG, CHIEN-CHI LEE, FREDERICK DAVID FISHBURN
  • Patent number: 8507356
    Abstract: Semiconductor device manufacturing method includes forming a first mask, having a first opening to implant ion into semiconductor substrate and being used to form first layer well, on semiconductor substrate; forming first-layer well having first and second regions by implanting first ion into semiconductor substrate using first mask; forming second mask, having second opening to implant ion into semiconductor substrate and being used to form second layer well, on semiconductor substrate; and forming second-layer well below first layer well by implanting second ion into semiconductor substrate using second mask. First region is formed closer to an edge of first-layer well than second region. Upon implanting first ion, first ion deflected by first inner wall of first mask is supplied to first region. Upon implanting second ion, second ion deflected by second inner wall of second mask is supplied to second region.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: August 13, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Noriaki Ikeda
  • Publication number: 20130200485
    Abstract: A method for manufacturing a semiconductor device, the method comprising, forming an opening in an insulating layer, which is formed on a semiconductor substrate, using a photoresist pattern formed on the insulating layer as a mask, forming a first element isolation portion in the semiconductor substrate by implanting an ion into the semiconductor substrate using the photoresist pattern as a mask, forming a second element isolation portion, in the semiconductor substrate, whose outer edge is outside an outer edge of the opening, by implanting an ion into the semiconductor substrate through the opening, and forming a third element isolation portion, which is inside the outer edge of the second element isolation portion, by embedding an insulating member in the opening and removing the insulating layer.
    Type: Application
    Filed: January 22, 2013
    Publication date: August 8, 2013
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: CANON KABUSHIKI KAISHA
  • Publication number: 20130181321
    Abstract: Disclosed is a structure for improved electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and an associated method for the structure's fabrication. The structure comprises a first portion of a trench extending through the top semiconductor layer and through a base oxide layer below the top semiconductor layer. A handle wafer is situated below the base oxide layer and a second portion of the trench, having sloped sidewalls, extends into the handle wafer. The sloped sidewalls are amorphized by an implant, for example, Xenon or Argon, to reduce carrier mobility in the handle wafer and improve electrical signal isolation between the adjacent devices situated in the top semiconductor layer.
    Type: Application
    Filed: October 8, 2012
    Publication date: July 18, 2013
    Applicant: NEWPORT FAB, LLC DBA JAZZ SEMICONDUCTOR
    Inventors: Paul D. Hurwitz, Robert L. Zwingman
  • Patent number: 8486750
    Abstract: A fabrication method for solid-state imaging devices includes having circuitry formed on a substrate, forming a lower electrode layer on the circuitry, patterning the lower electrode layer to separate pixel-wise into a set of segments, and forming a compound-semiconductor film of chalcopyrite structure over a whole area of element regions. A resist layer is applied on the compound-semiconductor thin film to pixel-wise pattern in accordance with the lower electrode layer as a base separated into the set of segments, and an ion doping is applied over a whole area of element regions, forming element separating regions in the compound-semiconductor thin film. The method includes removing the resist layer for exposure of surfaces of as set of compound-semiconductor thin films separated pixel-wise by the element separating regions. A transparent electrode layer is formed in a planarizing manner over a whole area of element regions.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: July 16, 2013
    Assignee: Rohm Co., Ltd.
    Inventors: Osamu Matsushima, Kenichi Miyazaki
  • Patent number: 8481372
    Abstract: In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a transistor including a semiconductor substrate having a source and a drain. The transistor also includes a doped channel formed in the semiconductor substrate between the source and the drain, the channel configured to pass current between the source and the drain. Additionally, the transistor has a gate comprising a semiconductor material formed over the channel and dielectric spacers on each side of the gate. The source and the drain are spatially separated from the gate so that the gate is not over the drain and source.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: July 9, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Publication number: 20130130471
    Abstract: A vertical channel transistor array has an active region formed by a plurality of semiconductor pillars. A plurality of embedded bit lines are arranged in parallel in a semiconductor substrate and extended along a column direction. A plurality of bit line contacts are respectively disposed on a side of one of the embedded bit lines. A plurality of embedded word lines are arranged in parallel above the embedded bit lines and extended along a row direction. Besides, the embedded word lines connect the semiconductor pillars in the same row with a gate dielectric layer sandwiched between the embedded word lines and the semiconductor pillars. The current leakage isolation structure is disposed at terminals of the embedded bit lines to prevent current leakage between the adjacent bit line contacts.
    Type: Application
    Filed: January 21, 2013
    Publication date: May 23, 2013
    Applicant: POWERCHIP TECHNOLOGY CORPORATION
    Inventor: POWERCHIP TECHNOLOGY CORPORATION
  • Publication number: 20130087889
    Abstract: A method of forming a device is presented. The method includes providing a structure having first and second regions. A diffusion barrier is formed between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions.
    Type: Application
    Filed: November 29, 2012
    Publication date: April 11, 2013
    Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventor: GLOBALFOUNDRIES Singapore Pte. Ltd.
  • Publication number: 20130062708
    Abstract: A semiconductor device structure, a method for manufacturing the same, and a method for manufacturing a semiconductor fin are disclosed. In one embodiment, the method for manufacturing the semiconductor device structure comprises: forming a fin in a first direction on a semiconductor substrate; forming a gate line in a second direction, the second direction crossing the first direction on the semiconductor substrate, and the gate line intersecting the fin with a gate dielectric layer sandwiched between the gate line and the fin; forming a dielectric spacer surrounding the gate line; and performing inter-device electrical isolation at a predetermined position, wherein isolated portions of the gate line form independent gate electrodes of respective devices.
    Type: Application
    Filed: November 18, 2011
    Publication date: March 14, 2013
    Inventors: Huicai Zhong, Qingqing Liang, Jun Luo, Chao Zhao
  • Patent number: 8389377
    Abstract: The present disclosure provides methods and apparatus for sensor element isolation in a backside illuminated image sensor. In one embodiment, a method of fabricating a semiconductor device includes providing a sensor layer having a frontside surface and a backside surface, forming a plurality of frontside trenches in the frontside surface of the sensor layer, and implanting oxygen into the sensor layer through the plurality of frontside trenches. The method further includes annealing the implanted oxygen to form a plurality of first silicon oxide blocks in the sensor layer, wherein each first silicon oxide block is disposed substantially adjacent a respective frontside trench to form an isolation feature. A semiconductor device fabricated by such a method is also disclosed.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: March 5, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Shang Hsiao, Kun-Yu Tsai, Chien-Hsien Tseng, Shou-Gwo Wuu, Nai-Wen Cheng
  • Publication number: 20130037907
    Abstract: An optoelectronic integrated circuit substrate may include a first region and a second region. The first region and the second region each include at least two buried insulation layers having different thicknesses. The at least two buried insulation layers of the first region are formed at a greater depth and have a greater thickness as compared to the at least two buried insulation layers of the second region. A micro-electromechanical systems (MEMS) structure may be formed in a third region that does not include a buried insulation layer.
    Type: Application
    Filed: January 31, 2012
    Publication date: February 14, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Seong-ho Cho
  • Patent number: 8354719
    Abstract: A semiconductor device and related fabrication methods are provided. One exemplary fabrication method forms a fin arrangement overlying an oxide layer, where the fin arrangement includes one or more semiconductor fin structures. The method continues by nitriding exposed portions of the oxide layer without nitriding the one or more semiconductor fin structures, resulting in nitrided portions of the oxide layer. Thereafter, a gate structure is formed transversely overlying the fin arrangement, and overlying the exposed portions of the oxide layer. The nitrided portions of the oxide layer substantially inhibit diffusion of oxygen from the oxide layer into the gate structure.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: January 15, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Kisik Choi, Robert J. Miller
  • Patent number: 8349698
    Abstract: An integrated semiconductor device and method of manufacturing the same includes leaving one part of a semiconductor layer so that an inclined surface is formed on a trench when forming the trench on a SOI wafer. A thick silicon oxide film (second insulation film) is formed along this incline surface. This thick silicon oxide film prevents oxygen entering a boundary surface between an insulation layer and the semiconductor layer of the SOI wafer within the trench.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: January 8, 2013
    Assignee: Sanken Electric Co., Ltd.
    Inventors: Hironori Aoki, Eiichi Kikkawa
  • Publication number: 20120305990
    Abstract: The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming isolation structures in strained semiconductor bodies of non-planar transistors while maintaining strain in the semiconductor bodies.
    Type: Application
    Filed: August 17, 2012
    Publication date: December 6, 2012
    Inventors: Stephen M Cea, Martin D. Giles, Kelin Kuhn, Jack T. Kavalieros, Markus Kuhn
  • Publication number: 20120302036
    Abstract: A semiconductor device includes: a SOI substrate including a support layer, a first insulation film and a SOI layer; a first circuit; a second circuit; and a trench separation element. The SOI substrate further includes a first region and a second region. The first region has the support layer, the first insulation film and the SOI layer, which are stacked in this order, and the second region has only the support layer. The trench separation element penetrates the support layer, the first insulation film and the SOI layer. The trench separation element separates the first region and the second region. The first circuit is disposed in the SOI layer of the first region. The second circuit is disposed in the support layer of the second region.
    Type: Application
    Filed: July 11, 2012
    Publication date: November 29, 2012
    Applicant: DENSO CORPORATION
    Inventors: Masakiyo Sumitomo, Makoto Asai, Nozomu Akagi, Yasuhiro Kitamura, Hiroki Nakamura, Tetsuo Fujii
  • Patent number: 8304033
    Abstract: Disclosed are methods of operation to grow, modify, deposit, or dope a layer upon a substrate using a multi-nozzle and skimmer assembly for introducing a process gas mixture, or multiple process gases mixtures, in a gas cluster ion beam (GCIB) system. Also disclosed is a method of forming a shallow trench isolation (STI) structure on a substrate, for example, an SiO2 STI structure, using a multiple nozzle system with two separate gas supplies, for example providing a silicon-containing gas and an oxygen-containing gas.
    Type: Grant
    Filed: April 23, 2009
    Date of Patent: November 6, 2012
    Assignee: TEL Epion Inc.
    Inventors: Martin D. Tabat, Matthew C. Gwinn, Robert K. Becker, Avrum Freytsis, Michael Graf
  • Patent number: 8293659
    Abstract: A method for fabricating a dielectric layer with improved insulating properties is provided, including: providing a dielectric layer having a first resistivity; performing a hydrogen plasma doping process to the dielectric layer; and annealing the dielectric layer, wherein the dielectric layer has a second resistivity greater than that of the first resistivity after annealing thereof.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: October 23, 2012
    Assignee: Nanya Technology Corporation
    Inventor: Shu Qin
  • Publication number: 20120214289
    Abstract: The present invention provides a method for forming a semiconductor substrate isolation, comprising: providing a semiconductor substrate; forming a first oxide layer and a nitride layer sequentially on the semiconductor substrate; forming openings in the nitride layer and in the first oxide layer to expose parts of the semiconductor substrate; implanting oxygen ions into the semiconductor substrate from the openings; performing annealing to form a second oxide layer on at least top portions of the exposed parts of the semiconductor substrate; and removing the nitride layer and the first oxide layer. Compared to the conventional STI process, said method enables a more simply and easy process flow and is applicable to common semiconductor substrates and SOI substrates.
    Type: Application
    Filed: April 8, 2011
    Publication date: August 23, 2012
    Applicant: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Haizhou Yin, Zhijiong Luo, Huilong Zhu