STRESSED TRANSISTOR WITH IMPROVED METASTABILITY
An embedded, strained epitaxial semiconductor material, i.e., an embedded stressor element, is formed at the footprint of at least one pre-fabricated field effect transistor that includes at least a patterned gate stack, a source region and a drain region. As a result, the metastability of the embedded, strained epitaxial semiconductor material is preserved and implant and anneal based relaxation mechanisms are avoided since the implants and anneals are performed prior to forming the embedded, strained epitaxial semiconductor material.
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This application is a divisional of U.S. patent application Ser. No. 12/942,289, filed Nov. 9, 2010 the entire content and disclosure of which is incorporated herein by reference.
BACKGROUNDThe present disclosure relates to a semiconductor structure and a method of fabricating the same. More particularly, the present disclosure relates to a semiconductor structure including at least one field effect transistor (FET) having a stressed channel and a metastable embedded, strained epitaxial semiconductor material located at the footprint of the at least one FET.
One trend in modern integrated circuit manufacture is to produce semiconductor devices, such as FETs, which are as small as possible. In a typical FET, a source and a drain are formed in an active region of a semiconductor substrate by implanting n-type or p-type impurities in the semiconductor material. Disposed between the source and the drain is a channel (or body) region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer.
In order to maintain FET device performance with continued scaling, it has been necessary to use mobility enhancement techniques. One of the most effective and widely used mobility enhancement techniques is referred to as “strained Si”. In such a mobility enhancement technique, an embedded SiGe layer (also referred to as eSiGe) is grown with selective epitaxy in the source/drain regions of the device.
Since the introduction of eSiGe, various process and device integration techniques have been introduced to increase the channel strain of the device. The most obvious of these enhancements is to increase the Ge content of the epitaxially grown SiGe layer. Although an eSiGe layer having an increased Ge content can provide enhanced mobility for CMOS devices, increasing the Ge content of an epitaxial grown SiGe layer is filled with difficulty in that any subsequently performed implant or anneal may result in defect formation and strain relaxation within the epitaxially grown SiGe layer.
SUMMARYIn the present disclosure, an embedded, strained epitaxial semiconductor material, i.e., an embedded stressor element, is formed at the footprint of at least one pre-fabricated FET; the pre-fabricated FET includes at least a patterned gate stack, a source region and a drain region. As a result, the metastability of the embedded, strained epitaxial semiconductor material is preserved and implant and anneal based relaxation mechanisms are avoided since the implants and anneals are performed prior to forming the embedded, strained epitaxial semiconductor material.
The terms “metastability” and “metastable” are used throughout the present application to denote a film or films that exist(s) with non-equilibrium strain value, i.e., the strain value of the film is greater than the equilibrium strain value. In some embodiments, the metastable film can be free of defects as well.
In one aspect of the present application, a method of fabricating a semiconductor structure such as a stressed FET is provided. The method includes forming at least one field effect transistor within an active device region of a semiconductor substrate. The at least one field effect transistor that is formed includes a patterned gate stack, a source region and a drain region. A dielectric material is formed on exposed surfaces of the semiconductor substrate and surrounding the at least one field effect transistor. The dielectric material that is formed has at least one set of contact openings that exposes an upper surface of the source region and the drain region. At least a portion of the exposed source region and drain region is removed forming a trench in each of the source region and the drain region. At least each trench in the source region and the drain region is filled with a strained epitaxial semiconductor material.
In another aspect of the present application, a method of fabricating a complementary metal oxide semiconductor (CMOS) structure having stressed FETs of different polarities is provided. The method of forming the (CMOS) structure includes forming a first polarity field effect transistor within a first active device region of a semiconductor substrate and forming a second polarity field effect transistor within a second active device region of the semiconductor substrate, each of the first and second polarity field effect transistors includes a patterned gate stack, a source region and a drain region. A dielectric material is formed on exposed surfaces of the semiconductor substrate and surrounding each of first and second polarity field effect transistors. The dielectric material has at least one first set of contact openings that exposes an upper surface of the source region and the drain region in one of the device regions. At least a portion of the exposed source region and drain region in the one device region is removed forming trenches therein. At least the trenches within the source region and the drain region of the one device region are filled with a first strained epitaxial semiconductor material. A blocking layer is formed on an upper surface of the dielectric material and within the first set of contact openings. A second set of contact openings is formed in the other device region not including the first set of contact openings, wherein the second set of contact openings exposes an upper surface of the source region and the drain region in the other device region. At least a portion of the exposed source region and drain region is removed in the other device region forming trenches therein. At least the trenches in the source region and the drain region of the other device region are filled with a second strained epitaxial semiconductor material.
In yet another aspect of the present disclosure, a semiconductor structure is provided. The semiconductor structure includes at least one field effect transistor located within an active device region of a semiconductor substrate. The at least one field effect transistor includes a patterned gate stack, a source region and a drain region, wherein the source region and the drain region are filled with a metastable strained epitaxial semiconductor material. A dielectric material is located on exposed surfaces of the semiconductor substrate and surrounding the at least one field effect transistor. The dielectric material has contact openings that expose an upper surface of said metastable strained epitaxial semiconductor material. A conductive contact material is located within the contact openings and directly on an upper surface of the metastable strained epitaxial semiconductor material.
The present disclosure, which provides a semiconductor structure including at least one field effect transistor (FET) having a stressed channel and a metastable embedded strained epitaxial semiconductor material located at the footprint of the at least one FET and a method of fabricating the same, will now be described in greater detail by referring to the following discussion and drawings that accompany the present application. It is noted that the drawings of the present application are provided for illustrative purposes only and, as such, the drawings are not drawn to scale.
In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of the various embodiment of the present disclosure. However, it will be appreciated by one of ordinary skill in the art that the various embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the present disclosure.
It will be understood that when an element as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
Referring first to
The semiconductor substrate 12 illustrated in
The semiconductor substrate 12 may also include a first doped (n- or p-) region, and a second doped (n- or p-) region. For clarity, the doped regions are not specifically shown in any of the drawings of the present application. The first doped region and the second doped region may be the same, or they may have different conductivities and/or doping concentrations. These doped regions are known as “wells” and they are formed utilizing conventional ion implantation processes.
At least one isolation region 15 can be typically formed into the semiconductor substrate 12. The at least one isolation region 15 may be a trench isolation region or a field oxide isolation region. The trench isolation region is formed utilizing a conventional trench isolation process well known to those skilled in the art. For example, lithography, etching and filling of the trench with a trench dielectric may be used in forming the trench isolation region. Optionally, a liner may be formed in the trench prior to trench fill, a densification step may be performed after the trench fill and a planarization process may follow the trench fill as well. The field oxide may be formed utilizing a so-called local oxidation of silicon process. Note that the at least one isolation region provides isolation between neighboring gate regions, typically required when the neighboring gates have opposite conductivities, i.e., nFETs and pFETs. The portion of the semiconductor substrate between the at least one isolation region 15 defines an active device region 14 of the semiconductor substrate 12.
After processing the semiconductor substrate 12, the at least one FET 16 is formed within the active device region 14 of the semiconductor substrate 12. The at least one FET 16 can be formed utilizing any conventional process. In one embodiment, the at least one FET 16 can be formed by deposition, lithography and etching. In another embodiment, a replacement gate process can be used in forming that least one FET 16.
As stated above, the at least one FET 16 includes a patterned gate stack including at least a gate dielectric 18 and a gate conductor 20. The gate dielectric 18 of the at least one FET 16 can comprise a dielectric oxide, dielectric nitride, dielectric oxynitride or multilayers thereof. In one embodiment, the gate dielectric 18 includes a semiconductor oxide, a semiconductor nitride or a semiconductor oxynitride. In another embodiment of the present disclosure, the gate dielectric 18 is a high k gate dielectric material having a dielectric constant that is greater than the dielectric constant of silicon oxide, e.g., 3.9. Typically, the high k gate dielectric material that can be employed as gate dielectric 18 has a dielectric constant greater than 4.0, with a dielectric constant of greater than 8.0 being even more typical. Exemplary high k dielectric materials include, but are not limited to, HfO2, ZrO2, La2O3, Al2O3, TiO2, SrTiO3, LaAlO3, Y2O3, HfOxNy, ZrOxNy, La2OxNy, Al2OxNy, TiOxNy, SrTiOxy, LaAlOxNy, Y2OxNy, a silicate thereof, and an alloy thereof. Multilayered stacks of these high k materials can also be employed as the high k gate dielectric 14. Each value of x is independently from 0.5 to 3 and each value of y is independently from 0 to 2.
The thickness of the gate dielectric 18 may vary depending on the technique used to form the same. Typically, however, the gate dielectric 18 has a thickness from 0.5 nm to 10 nm, with a thickness from 1.0 nm to 5 nm being even more typical. In some embodiments, the gate dielectric 18 employed may have an effective oxide thickness on the order of, or less than, 1 nm.
The gate dielectric 18 can be formed by methods well known in the art. In one embodiment, gate dielectric 18 can be formed utilizing a thermal oxidation and/or nitridation process. In another embodiment the gate dielectric 18 can be formed be a deposition method including, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source misted chemical deposition (LSMCD), atomic layer deposition (ALD), and other like deposition processes. In some embodiments in which different polarity FETs, e.g., nFETs and pFETs, are formed, the gate dielectric in the different active device regions can be the same or different. Different gate dielectric materials can be formed using block mask technology.
The gate conductor 20 of the patterned gate stack of the at least one FET 16 is located above the gate dielectric 18. The gate conductor 20 that can be employed may comprise any conductive material including, but not limited to, polycrystalline silicon, polycrystalline silicon germanium, an elemental metal (e.g., tungsten, titanium, tantalum, aluminum, nickel, ruthenium, palladium and platinum), an alloy of at least one elemental metal, an elemental metal nitride (e.g., tungsten nitride, aluminum nitride, and titanium nitride), an elemental metal silicide (e.g., tungsten silicide, nickel silicide, and titanium silicide) and multilayers thereof. In one embodiment, the gate conductor 20 can be comprised of a p-type gate metal. In another embodiment, the gate conductor 20 can be comprised of an n-type gate metal. In some instances, a single layer of gate conductor 20 is formed. In another instances, a first layer of conductive material and a second layer of conductive material are formed. In one embodiment, gate conductor 20 may include a stack, from bottom to top, of a conductive metal layer and an upper conductive Si-containing material layer; the conductive metal layer has a higher conductivity than the conductive Si-containing material layer.
The gate conductor 20 can be formed utilizing a conventional deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), evaporation, physical vapor deposition (PVD), sputtering, chemical solution deposition, atomic layer deposition (ALD) and other liked deposition processes. When Si-containing materials are used as the gate conductor 20, the Si-containing materials can be doped within an appropriate impurity by utilizing either an in-situ doping deposition process or by utilizing deposition, followed by a step such as ion implantation in which the appropriate impurity is introduced into the Si-containing material. When a metal silicide is formed, a conventional silicidation process can be employed.
The as deposited gate conductor 20 typically has a thickness from 5 nm to 200 nm, with a thickness from 20 nm to 100 nm being more typical. In some embodiments in which different polarity FETs are formed, the gate conductor material in the different active device regions can be the same or different. Different gate conductive materials can be formed using block mask technology.
In some embodiments, an optional hard mask material (not shown) can be located atop the gate conductor 20. The optional hard mask material includes an oxide, a nitride, an oxynitride or any combination thereof including multilayered stacks. When present, the optional hard mask material is formed utilizing a conventional deposition process well known to those skilled in the art including, for example, CVD and PECVD. Alternatively, the optional hard mask material can be formed by a thermal process such as, for example, oxidation and/or nitridation. The thickness of the optional hard mask material may vary depending on the exact hard mask material employed as well as the process that is used in forming the same. Typically, the hard mask material has a thickness from 5 nm to 200 nm, with a thickness from 10 nm to 50 nm being more typical. The hard mask material is typically employed when the conductive material is a Si-containing material such as polysilicon or SiGe.
Source/drain extension regions (not shown) can be formed utilizing any known extension ion implantation process. After the extension ion implantation, an anneal can be used to activate the implanted extension ions. At least one sidewall spacer 22 can optionally be formed utilizing any known process including deposition of a spacer material, followed by etching. Typical spacer materials include an oxide and/or a nitride. After formation of the spacer, source/drain regions 24 can be formed into the active device region 14 of the semiconductor substrate 12 and at the footprint of the at least one FET 16. In instances in which a replacement gate process is formed, the source/drain regions 24 can be formed prior to forming the patterned gate stack of the at least one FET 16. The source/drain regions 24 can be formed utilizing a source/drain ion implantation process followed by annealing. It is noted that in the drawings of the present disclosure, source/drain regions 24 also include the source/drain extension regions therein.
Referring now to
The structure shown in
The dielectric material 28 can be formed utilizing any conventional deposition process including, but not limited to, spin-on coating, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), evaporation, and chemical solution deposition.
The dielectric material 28 typically has a dielectric constant of 4.0 or less, with a dielectric constant of 2.8 or less being even more typical. All dielectric constants mentioned in this disclosure are relative to a vacuum, unless otherwise stated. The thickness of the dielectric material 28 is not restrictive so long as the dielectric material 28 covers an upper surface of the patterned gate stack of the at least one FET 16. Typically, the dielectric material 28 has a thickness from 200 nm to 450 nm.
The set of contact openings 30 that is present within the dielectric material 28 can be formed by lithography and etching. The lithographic process includes forming a photoresist (not shown) atop the dielectric material 28, exposing the photoresist to a desired pattern of radiation and developing the exposed photoresist utilizing a conventional resist developer to thereby provide a patterned resist (also not shown) atop the dielectric material 28. The etching process includes a dry etching process (such as, for example, reactive ion etching, ion beam etching, plasma etching or laser ablation), or a wet chemical etching process that selectively removes the exposed portions of dielectric material 28 that are not protected by the patterned resist. Typically, reactive ion etching is used in providing the set of contact openings 30. After etching, the patterned resist is typically removed utilizing a conventional resist stripping process such as, for example, ashing. As shown, each contact opening 30 has sidewalls. The sidewalls within each contact opening 30 may be substantially vertical, as shown, or some tapering may be evident. The set of contact openings 30 can have an aspect ratio that is 1:1 or greater.
Referring to
The etching that can be used in forming each of the trenches 34 includes wet etching, dry etching or a combination of wet and dry etching. In one embodiment, an anisotropic etch can be employed in forming each of the trenches 34. In another embodiment, an isotropic etch can be employed in forming each of the trenches 34. In a further embodiment, a combination of anisotropic etching and isotropic etching can be employed in forming each of the trenches 34. When a dry etch is employed in forming each of the trenches 34, the dry etch can include one of reactive ion etching (RIE), plasma etching, ion beam etching and laser ablation. When a wet etch is employed in forming each of the trenches 34, the wet etch includes any chemical etchant, such as, for example, ammonium hydroxide that selectively etches the exposed portions of the source/drain regions 24. In some embodiments, a crystallographic etching process can be used in forming each of the trenches 34.
In the embodiment illustrated in
Referring now to
The strained epitaxial semiconductor material 36 that is formed has a different lattice constant than the lattice constant of the semiconductor substrate 12 and therefore it is capable of enhancing the electron mobility in the device channel by inducing strain to the channel. In one embodiment, and when the semiconductor substrate 12 is composed of silicon and when a pFET gate stack is present, the strained epitaxial semiconductor material 36 can be composed of SiGe or carbon doped silicon germanium (SiGe:C). In another embodiment, and when the semiconductor substrate 12 is composed of silicon and when an nFET gate stack is present, the strained epitaxial semiconductor material 36 can be composed of carbon doped silicon (Si:C).
The strained epitaxial semiconductor material 36 can be formed by any epitaxial growth process that is well known to those skilled in the art. The epitaxial growth ensures that the strained epitaxial semiconductor material 36 has a same crystallographic structure as that of the surface of the semiconductor substrate 12 in which the strained epitaxial semiconductor material 36 is formed. The epitaxial growth process typically employs at least one precursor-containing gas. The types of precursors used in forming the strained epitaxial semiconductor material 36 are well known to those skilled in the art. For example, SiH4 (silane), SiH2Cl2 (dichlorosilane), SiHCl3 (trichlorosilane), SiCl4 (tetrachlorosilane), Si2H6 (disilane), Si3H8 (trisilane), GeH4 (germane), and SiCH6 (monomethylsilane) can be used as precursors of the strained epitaxial semiconductor material 36.
The strained epitaxial semiconductor material 36 that is formed can have a higher concentration of Ge and C than prior art embedded, strained epitaxial semiconductor material that are formed prior to formation of the FET including the source region and drain region. For example, and in one embodiment of the present disclosure in which the strained epitaxial semiconductor material 36 is composed of SiGe, the Ge content can be from 15 atomic % to 60 atomic %. In another embodiment of the present disclosure in which the strained epitaxial semiconductor material 36 is composed of SiGe:C or Si:C, the C content can be from 0.5 atomic % to 3.0 atomic %.
Because the strained epitaxial semiconductor material 36 is formed after formation of the at least one FET 16, the metastability of the strained epitaxial semiconductor material 36 is maintained. Also, because the strained epitaxial semiconductor material 36 is formed after formation of the at least one FET 16, implant and anneal based relaxation are avoided.
The remaining portions of each of the contact openings within dielectric material 28 can be filled with any conductive contact material 38 including, for example, a conductive metal, a conductive metal alloy, a conductive metal nitride, a metal semiconductor alloy, and multilayers thereof. In one embodiment, a metal semiconductor alloy is formed directly on an upper surface of the strained epitaxial semiconductor material 36 and a conductive metal or metal alloy is formed on the metal semiconductor alloy. The filling of the remaining portion of each of the contact openings may include formation of the conductive contact material and planarization. The formation of the conductive contact material 38 may include one of the techniques mentioned above for forming gate conductor 20. The resultant structure including conductive contact material 38 is also shown, for example, in
Reference is now made to
The initial structure 10′ also includes a first polarity FET 104 within the first active device region 100 and a second polarity FET 106 within the second active device 102. The first polarity FET 104 may be an nFET or a pFET, while the second polarity FET 106 may be the other of the nFET or pFET not used as the first polarity FET 104.
The first polarity FET 104 and the second polarity FET 106 each includes a patterned gate stack including at least a gate dielectric 18 and a gate conductor 20. The FETs including the gate dielectric and gate conductor employed in this example are formed and/or are composed of the same materials as described above for the initial structure 10 shown in
The first and second FETs shown in
Referring now to
After forming the first set of contact openings 30′, portions of the exposed source/drain regions in the specific active device region are removed providing a first set of trenches (not specifically shown 5B). The removal of portions of the exposed source/drain regions 24 utilizes one of the etching techniques mentioned above for forming trenches 34.
Referring now to
Referring now to
A second set of trenches (not specifically shown) is formed within the exposed source/drain regions 24 within the active device region including the second set of contact openings 30″ and a second strained epitaxial semiconductor material 36″ as shown in
Referring now to
Reference is now made to
The sacrificial embedded, epitaxial semiconductor material 152 can be formed by utilizing any conventional epitaxial growth process and the sacrificial embedded, epitaxial semiconductor material 152 is composed of one of the epitaxial semiconductor materials mentioned above for strained epitaxial semiconductor material 36. For example, the sacrificial embedded, epitaxial semiconductor material 152 can be comprised of SiGe, SiGe:C, or Si:C.
Referring now to
Referring now to
Referring now to
Although the second embodiment illustrated in
While the present disclosure has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present disclosure. It is therefore intended that the present disclosure not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.
Claims
1. A semiconductor structure comprising:
- at least one field effect transistor located within an active device region of a semiconductor substrate, said at least one field effect transistor comprising a patterned gate stack, a source region and a drain region, wherein at least a portion of said source region and a portion of said drain region include a metastable strained epitaxial semiconductor material disposed therein;
- a dielectric material located on exposed surfaces of the semiconductor substrate and surrounding the at least one field effect transistor, said dielectric material having contact openings that expose an upper surface of said metastable strained epitaxial semiconductor material; and
- a conductive contact material located within said contact openings and directly on an upper surface of said metastable strained epitaxial semiconductor material.
2. The semiconductor structure of claim 1 wherein said at least one field effect transistor is a pFET and said strained epitaxial semiconductor material consists essentially of SiGe.
3. The semiconductor structure of claim 2 wherein said SiGe contains a Ge content of from 15 atomic % to 60 atomic %.
4. The semiconductor structure of claim 1 wherein said at least one field effect transistor is a pFET and said strained epitaxial semiconductor material consists essentially of SiGe:C.
5. The semiconductor structure of claim 4 wherein said SiGe:C contains a C content from 0.5 atomic % to 3.0 atomic %.
6. The semiconductor structure of claim 1 wherein said at least one field effect transistor is an nFET and said second strained epitaxial semiconductor material consists essentially of Si:C.
7. The semiconductor structure of claim 6 wherein said Si:C contains a C content from 0.5 atomic % to 3.0 atomic %.
8. The semiconductor structure of claim 1 wherein a portion of said metastable strained semiconductor material extends above a planar upper surface of said semiconductor substrate.
9. The semiconductor structure of claim 1 wherein said metastable strained epitaxial semiconductor material has a same crystallographic orientation as that of the semiconductor substrate.
10. The semiconductor structure of claim 1 wherein said metastable strained epitaxial semiconductor material imparts a strain to a channel region which is located in the semiconductor substrate, beneath the patterned gate stack and between the source region and the drain region.
11. The semiconductor structure of claim 1 wherein said metastable strained epitaxial semiconductor material is spaced apart from a spacer that is located on vertical sidewalls of the patterned gate stack.
12. The semiconductor structure of claim 1 wherein said metastable strained epitaxial semiconductor material is located within a trench having vertical sidewalls, and said vertical sidewalls of said trench are in contact with a different semiconductor material within the source region and drain region.
13. The semiconductor structure of claim 1 wherein said at least one field effect transistor comprises an nFET within an nFET device region and a PFET within a pFET device region, and wherein said metastable strained epitaxial semiconductor material is located within only one of nFET region or pFET region.
14. The semiconductor structure of claim 1 wherein said at least one field effect transistor comprises an nFET within an nFET device region and aPFET within a pFET device region, and wherein said metastable strained epitaxial semiconductor material is located within both said nFET region and said pFET region.
15. The semiconductor structure of claim 1 wherein said metastable strained epitaxial semiconductor material is located within the entirety of said source region and said drain region.
16. The semiconductor structure of claim 15 wherein said metastable strained epitaxial semiconductor material has a sidewall edge that is aligned with and located beneath a vertical edge of said patterned gate stack.
17. The semiconductor structure of claim 16 wherein said metastable strained epitaxial semiconductor material has a portion that extends above a planar upper surface of said semiconductor substrate.
18. The semiconductor structure of claim 16 wherein said at least one field effect transistor comprises an nFET within an nFET device region and aPFET within a pFET device region, and wherein said metastable strained epitaxial semiconductor material is located within only one of nFET region or pFET region.
19. The semiconductor structure of claim 16 wherein said at least one field effect transistor comprises an nFET within an nFET device region and aPFET within a pFET device region, and wherein said metastable strained epitaxial semiconductor material is located within both said nFET region and said pFET region.
20. The semiconductor structure of claim 19 wherein said metastable strained epitaxial semiconductor material within the nFET device region is different from said metastable strained epitaxial semiconductor material within said pFET device region.
Type: Application
Filed: Jan 28, 2013
Publication Date: May 30, 2013
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION (Armonk, NY)
Inventor: INTERNATIONAL BUSINESS MACHINES CORPORATION (Armonk, NY)
Application Number: 13/751,778
International Classification: H01L 29/78 (20060101);