CMOS TRANSISTORS HAVING DIFFERENTIALLY STRESSED SPACERS

Abstract

CMOS transistors are formed incorporating a gate electrode having tensely stressed spacers on the gate sidewalls of an n channel field effect transistor and having compressively stressed spacers on the gate sidewalls of a p channel field effect transistor to provide differentially stressed channels in respective transistors to increase carrier mobility in the respective channels.

Description

This application is a divisional application of co-pending application Ser. No. 13/013,801 filed Jan. 25, 2011 of which the benefit of the earlier filing date is claimed.

BACKGROUND

The present invention relates to CMOS transistors, and more specifically, to n and p channel metal oxide semiconductor (MOS) field effect transistors (FET's) having differentially stressed spacers and differentially stressed channels.

Stressor layers have been one of the techniques used to increase device performance. However, due to the location of the spacers for short channel effect control, the stressor layers are typically located a few hundred angstroms away from the channel over a spacer thereby limiting the extent of performance improvement in carrier mobility in the channel.

BRIEF SUMMARY OF THE INVENTION

In accordance with the present invention, an n type field effect transistor comprising a substrate having a p region, a first gate dielectric, a first poly silicon gate electrode there over having sidewalls, a tensely stressed spacer on the sidewalls of the first poly silicon gate electrode, a n type halo region in the p region on opposite sides of the first poly silicon gate electrode, a n type source and drain extension overlapping the n type halo regions on opposite sides of the first poly silicon gate electrode, and electrical contacts to the source extension, drain extension and gate electrode.

The invention further provides a p type field effect transistor comprising a substrate having a n region, a first gate dielectric, a first poly silicon gate electrode there over having sidewalls, a compressively stressed spacer on the sidewalls of the first poly silicon gate electrode, a p type halo region in the n region on opposite sides of the first poly silicon gate electrode, a p type source and drain extension overlapping the p type halo regions on opposite sides of the first poly silicon gate electrode, and electrical contacts to the source extension, drain extension and gate electrode.

The invention further provides an n type and p type field effect transistor is described comprising a substrate having p and n regions for forming n and p type field effect transistors respectively therein, a first gate dielectric and a first poly silicon gate electrode having sidewalls there over on at least one p region, a second gate dielectric and a second poly silicon gate electrode having sidewalls there over on at least one n region, a tensely stressed spacer on the sidewalls of the first poly silicon gate electrode, an n type halo region in the p region on opposite sides of the first poly silicon gate electrode, an n type source and drain extension in the p region overlapping the n type halo regions on opposite sides of the first poly silicon gate electrode, a compressively stressed spacer on the sidewalls of the second poly silicon gate electrode, a p type halo region in the n region on opposite sides of the second poly silicon gate electrode, and a p type source and drain extension in the n region overlapping the p type halo regions on opposite sides of the second poly silicon gate electrode.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

These and other features, objects, and advantages of the present invention will become apparent upon consideration of the following detailed description of the invention when read in conjunction with the drawing in which:

FIG. 1 is a cross-section view illustrating a process step of the invention showing a substrate having p and n regions with a respective gate dielectric and a poly silicon gate electrode thereon.

FIG. 2 is a cross-section view illustrating a process step of the invention showing a tensely stressed film on a poly silicon gate electrode on a p region.

FIG. 3 is a cross-section view illustrating a process step of the invention showing a tensely stressed spacer on the sidewalls of a poly silicon gate electrode of a NMOS FET.

FIG. 4 is a cross-section view illustrating an alternate process of the invention showing an oxide layer formed between a tensely stressed spacer and a first poly silicon gate electrode of a NMOS FET.

FIG. 5 is a cross-section view illustrating a process step of the invention showing an oxide layer and a compressively stressed spacer on the sidewalls of a gate electrode of a PMOS FET.

FIG. 6 is a cross-section view showing a completed NMOS FET and a PMOS FET after removal of a mask shown in FIG. 5.

FIG. 7 is a cross-section view showing electrical contacts to the source and drain of the completed NMOS FET and PMOS FET shown in FIG. 6.

DETAILED DESCRIPTION

Referring now to the drawing, FIG. 1 shows a cross-section view of a semiconductor substrate 12 having p regions 14 and 15 for forming a n type metal oxide semiconductor (NMOS) field effect transistor (FET) and n regions 16 and 17 for forming a p type metal oxide semiconductor (PMOS) FET respectively therein. N region 16 and p region 14 are electrically isolated from each other by an isolation trench 20 of dielectric such as an oxide. P region 14 and n region 17 are electrically isolated from each other by an isolation trench 22 of dielectric such as an oxide. N region 17 and p region 15 are electrically isolated from each other by an isolation trench 24 of dielectric such as an oxide. P regions 14 and 15 and n regions 16 and 17 may be single crystal Si, SiGe, SiC, Ge, GaAs and combinations thereof and typically with respect to a top view, regions 14-17 have a square or rectangular shape.

A first gate dielectric 25 and first poly silicon gate electrode 26 are formed on p region 14. A second gate dielectric 27 and second poly silicon gate electrode 28 is formed on n region 17. First poly silicon gate electrode 26 and second poly silicon gate 28 may be doped n or p type up to 5×10²¹ atoms/cm³. For p type doping, BF₂ or BF₃ may be used. For n type doping, an As containing gas may be used.

A first hard mask 30 which may be for example an oxide, a nitride such as a silicon nitride or an oxide nitride is formed over n region 17, over second gate dielectric 27 and second poly silicon gate electrode 28. First hard mask 30 functions to protect n region 17, second gate dielectric 27 and second poly silicon gate electrode 28 from damage during processing in p region 14. As shown in FIG. 1, first hard mask 30 completely covers n region 17 and overlaps isolation trenches 22 and 24 which together surround and electrically isolate p region 17. A mask comprising photo resist may be used in certain situations in place of first hard mask 30.

FIG. 2 shows a cross section view of tensely stressed film 34 formed over n region 16, isolation trench 20, p region 14, first gate dielectric 25, first poly silicon gate electrode 26, isolation trench 22, mask 30, isolation trench 24 and p region 15. Tensely stressed film 34 may be a conformal coating having a thickness in the range from 2 nm to 15 nm formed of oxide nitride, nitride oxide and under conditions to provide a tensile stress on sidewalls 29 and 31 of first poly silicon gate electrode 26 which in turn provides a tensile stress in channel 39 in p region 14 underneath first gate dielectric 25 and first poly silicon gate electrode 26. Channel 39 will function as the channel of NMOS FET 86 shown in FIG. 6.

FIG. 3 is a cross-section view of FIG. 2 after etching tensely stressed film 34 to form tensely stressed spacers 36 and 38 on sidewalls 29 and 31 of first poly silicon gate electrode 26. Tensely stressed spacers 36 and 38 may be formed directly on sidewalls of first poly silicon gate electrode 26 and function to tensely stress poly silicon gate electrode 26 in the out of plane direction with respect to the major surface of substrate 12. In turn, tensely stressed poly silicon gate electrode 26 provides tensile stress to channel 39 directly below gate electrode 26. Tensely stressing channel 39 improves electron carrier mobility in channel 39. Tensely stressed spacers 40 and 42 are also formed on the sidewalls of mask 30 at the same time spacers 36 and 38 are formed. Tensely stressed film 34 is preferably etched by Reactive Ion Etching (REI) which etches horizontal surfaces (i.e. parallel with respect to the major surface of substrate 12) and the top edges of vertical layers. It is noted that tensely stressed film 34 is completely etched on the horizontal surfaces of mask 30 which facilitates the removal of mask 30 during later processing.

After tensely stressed spacers 36 and 38 are formed; n type halo regions 44 and 46 are formed on opposite sides of first poly silicon gate electrode 26. Halo regions 44 and 46 are positioned with respect to tensely stressed spacers 36 and 38. Next, n type source and drain extensions 48 and 50 are formed in p region 14 overlapping the halo regions on opposite sides of first poly silicon gate electrode 26. Next, hard mask 30 is removed by a chemical etch for example by a timed chemical etch. Tensely stressed spacers 40 and 42 on either side of mask 30 are removed when mask 30 is removed.

FIG. 4 is a cross-section view similar to FIG. 3 except oxide layers 50 and 52 are formed first on sidewalls 29 and 31 of first poly silicon gate electrode 26 prior to forming tensely stressed film 34. Oxide layers 50 and 52 may be formed by oxidizing the exposed surface of first poly silicon gate electrode 26. Oxide layers 50 and 52 have a thickness in the range from 0.5 nm to 5 nm and are preferably in the range from 1 nm to 3 nm. Oxide layers 50 and 52 results from processing other areas on substrate 12 without a protective mask over sidewalls 29 and 31 or is formed to promote adhesion to sidewalls 29 and 31 of first poly silicon gate electrode 26 of subsequently formed tensely stressed spacers 36 and 38.

FIG. 5 is a cross-section view of FIG. 4 after removal of mask 30 to expose region 17 and second poly silicon gate electrode 28 to further processing. A mask 56 is formed over p region 14, source and drain extensions 48 and 50, halo regions 44 and 46, spacers 36 and 38, oxide layers 50 and 52, and first poly silicon gate electrode 26 to protect them from damage during processing in n region 17 to form PMOS FET 88 shown in FIG. 6.

FIG. 5 shows oxide layers 58 and 60 formed on sidewalls 57 and 59 of second poly silicon gate electrode 28. Oxide layers 58 and 60 may be formed by oxidizing the exposed surface of second poly silicon gate electrode 28. Oxide layers 58 and 60 may have a thickness in the range from 0.5 nm to 5 nm and preferably in the range from 1 nm to 3 nm. A compressively stressed film (not shown) is formed over mask 56, region 17, oxide layers 58 and 60 and second poly silicon gate electrode 28. The compressively stressed film (not shown) is etched by RIE to form compressively stressed spacers 64 and 66 on oxide layers 58 and 60 on sidewalls 57 and 59 respectively of second poly silicon gate electrode 28.

Compressively stressed spacers 68 and 70 are also formed on mask 56 at the same time compressively stressed spacers 64 and 66 are formed. Compressively stressed spacers 64 and 66 function to compress sidewalls 57 and 59 of second poly silicon gate electrode 28 and channel 72 below which improves the carrier mobility of channel 72 below shown in FIG. 5 with respect to hole carriers. Compressively stressed spacers 64 and 66 also function to position during ion implantation halo regions 74 and 76 and source/drain extensions 78 and 80 with respect to second poly silicon gate electrode 28.

After compressively stressed spacers 64 and 66 are formed, p type halo regions 74 and 76 are formed on opposite sides of second poly silicon gate electrode 28. Next, p type source and drain extensions 78 and 80 are formed overlapping halo regions 74 and 76 on opposite sides of second poly silicon gate electrode 28.

FIG. 6 is a cross-section view of completed NMOS FET 86 and PMOS FET 88 after mask 56 is removed. Hard mask 56 may be removed by a chemical etch for example by a timed chemical etch. Compressively stressed spacers 68 and 70 on either side of mask 56 are removed at the same time mask 56 is removed.

A self aligned silicide process may be used to form silicide regions 82-85 in source extension 48/halo region 44, drain extension 50/halo region 46, source extension 78/halo region 74 and drain extension 80/halo region 76, respectively, shown in FIG. 7. In the silicide process a layer of metal (not shown) is formed over substrate 12 and exposed silicon regions 14 and 17 shown in FIG. 6. The layer of metal which may be, for example, Ni (not shown) is heated and reacted with the exposed Si regions to form nickel silicide. The unreacted metal is removed by a selective etch. Nickel silicate forms an ohmic contact to source extensions 48, 50, 78 and 80 and halo regions 44, 46, 74 and 76. The metal may react with the upper surface of first and second poly silicon gate electrodes 26 and 28 to form silicide regions which are not shown in FIG. 7. The upper surface may be lowered and silicide regions removed (if present) on poly silicon gate electrodes 26 and 28 during chemical mechanical processing (CMP).

FIG. 7 is a cross-section view showing electrical contacts to source extension 48 and drain extension 50 of NMOS FET 86 and to source extension 78 and drain extension 80 of PMOS FET 88. Dielectric layer 89 may be formed over NMOS FET 86 and PMOS FET 88 which may be planarized by CMP to expose upper surface 81 and 87 respectively of first and second poly silicon gate electrodes 26 and 28 for making electrical contact thereto or for removal of first and second poly silicon gate electrodes 26 and 28 such as by chemical etching in a replacement gate process to replace the material of the respective gate dielectric and gate electrode or just the gate electrode which may be replaced with poly silicon or metal. The gate dielectric may be replaced with a gate dielectric known in the art. If silicide regions are formed on upper surface 81 and 87 respectively of first and second poly silicon gate electrodes 26 and 28, the silicide regions may be removed by CMP or remain after CMP by discontinuing CMP at the proper time before removal of the silicide regions.

Openings 90, 92, 94 and 96 may be formed in dielectric layer 89 to source extension 48, drain extension 50, source extension 78, and drain extension 80, respectively. Openings 90, 92, 94 and 96 may be filled with a conductor such as W to form contacts 98 and 100 to source extension 48 and drain extension 50 respectively of NMOS FET 86 and form contacts 102 and 104 to source extension 78 and drain extension 80 respectively of PMOS FET 88.

In FIGS. 2-7, like references are used for similar structure or apparatus shown in an earlier figure.

While there has been described and illustrated n and p channel MOS FETs having differentially stressed spacers and transistor channels, it will be apparent to those skilled in the art that modifications and variations are possible without deviating from the broad scope of the invention which shall be limited solely by the scope of the claims appended hereto.

Claims

1. An n type field effect transistor comprising:

a substrate having a p region,

a first gate dielectric,

a first poly silicon gate electrode having sidewalls over said first gate dielectric,

a tensely stressed spacer on said sidewalls of said first poly silicon gate electrode,

an n type halo region in said p region on opposite sides of said first poly silicon gate electrode,

an n type source and drain extension overlapping said n type halo regions on opposite sides of said first poly silicon gate electrode, and

electrical contacts to said source extension, drain extension and gate electrode.

2. The n type field effect transistor of claim 1 wherein said tensely stressed spacer is in direct contact to said sidewalls of said first poly silicon gate electrode.

3. The n type field effect transistor of claim 1 wherein said tensely stressed spacer on said first poly silicon gate electrode is at an interface of said first gate dielectric.

4. The n type field effect transistor of claim 1 wherein said tensely stressed spacer abuts said halo region.

5. The n type field effect transistor of claim 1 wherein said tensely stressed spacer is spaced from said sidewalls of said first poly silicon gate electrode by an oxide layer having a thickness in the range from 0.5 to 5 nm.

6. The n type field effect transistor of claim 1 wherein said first poly silicon gate electrode is selected from the group consisting of SiGe, SiC, Ge, GaAs, combinations thereof and in combination with poly silicon.

7. A p type field effect transistors comprising:

a substrate having an n region,

a first gate dielectric,

a first poly silicon gate electrode having sidewalls over said first gate dielectric,

a compressively stressed spacer on said sidewalls of said first poly silicon gate electrode,

a p type halo region in said n region on opposite sides of said first poly silicon gate electrode,

a p type source and drain extension overlapping said p type halo regions on opposite sides of said first poly silicon gate electrode, and

electrical contacts to said source extension, drain extension and gate electrode.

8. The p type field effect transistor of claim 7 wherein said compressively stressed spacer is in direct contact to said sidewalls of said first poly silicon gate electrode.

9. The p type field effect transistor of claim 7 wherein said compressively stressed spacer on said first poly silicon gate electrode is at an interface of said first gate dielectric.

10. The p type field effect transistor of claim 7 wherein said compressively stressed spacer abuts said halo region.

11. The p type field effect transistor of claim 7 wherein said compressively stressed spacer is spaced from said sidewalls of said first poly silicon gate electrode by an oxide layer having a thickness in the range from 0.5 to 5 nm.

12. The p type field effect transistor of claim 7 wherein said first poly silicon gate electrode is selected from the group consisting of SiGe, SiC, Ge, GaAs, combinations thereof and in combination with poly silicon.

13. An n type field effect transistor and a p type field effect transistor comprising:

a substrate having p and n regions for forming n and p type field effect transistors respectively therein,

a first gate dielectric and a first poly silicon gate electrode having sidewalls there over on at least one p region,

a second gate dielectric and a second poly silicon gate electrode having sidewalls there over on at least one n region,

a tensely stressed spacer on said sidewalls of said first poly silicon gate electrode, an n type halo region in said p region on opposite sides of said first poly silicon gate electrode,

an n type source and drain extension in said p region overlapping said n type halo regions on opposite sides of said first poly silicon gate electrode,

a compressively stressed spacer on said sidewalls of said second poly silicon gate electrode,

a p type halo region in said n region on opposite sides of said second poly silicon gate electrode, and

a p type source and drain extension in said n region overlapping said p type halo regions on opposite sides of said second poly silicon gate electrode.

14. The n type field effect transistor and p type field effect transistor of claim 13 wherein said tensely stressed film is positioned directly on exposed sidewalls of said first poly silicon gate electrode.

15. The n type field effect transistor and p type field effect transistor of claim 13 wherein said tensely stressed film is positioned on said first poly silicon gate electrode at an interface of said first gate dielectric.

16. The n type field effect transistor and p type field effect transistor of claim 13 wherein said tensely stressed film is positioned on said first poly silicon gate electrode and abutting said p region.

17. The n type field effect transistor and p type field effect transistor of claim 13 further includes an oxide layer having a thickness in the range from 0.5 to 5 nm on sidewalls of said first poly silicon gate electrode.

18. The n type field effect transistor and p type field effect transistor of claim 13 wherein said first poly silicon gate electrode is selected from the group consisting of SiGe, SiC, Ge, GaAs, combinations thereof and in combination with poly silicon.

19. The n type field effect transistor and p type field effect transistor of claim 13 wherein said compressively stressed film is positioned directly on exposed sidewalls of said second poly silicon gate electrode.

20. The n type field effect transistor and p type field effect transistor of claim 13 wherein said compressively stressed film is positioned on said second poly silicon gate electrode at an interface of said second gate dielectric.

21. The n type field effect transistor and p type field effect transistor of claim 13 wherein said compressively stressed film is positioned on said second poly silicon gate electrode and abutting said p region.

22. The n type field effect transistor and p type field effect transistor of claim 13 further including an oxide layer having a thickness in the range from 0.5 to 5 nm on sidewalls of said second poly silicon gate electrode.

23. The n type field effect transistor and p type field effect transistor of claim 13 wherein said second poly silicon gate electrode is selected from the group consisting of SiGe, SiC, Ge, GaAs, combinations thereof and in combination with poly silicon.

24. The n type field effect transistor and p type field effect transistor of claim 13 further including:

a dielectric layer positioned over and above said p and n regions including said first and second poly silicon gate electrodes,

said dielectric layer planarized down to said first and second poly silicon gate electrodes, and

contacts contacting said first and second gate electrodes and said source and drain extensions of said n and p type field effect transistors.