HIGH-EFFICIENCY PHOTOVOLTAIC BACK-CONTACT SOLAR CELL STRUCTURES AND MANUFACTURING METHODS USING THREE-DIMENSIONAL SEMICONDUCTOR ABSORBERS

Abstract

Back contact back junction three dimensional solar cell and methods for manufacturing are provided. The back contact back contact back junction three dimensional solar cell comprises a three-dimensional substrate. The substrate comprises a light capturing frontside surface with a passivation layer, a doped base region, and a doped backside emitter region with a polarity opposite the doped base region. A backside passivation layer is positioned on the doped backside emitter region. Backside emitter contacts and backside base contacts connected to metal interconnects and selectively formed on three-dimensional features of the backside of three-dimensional solar cell.

Description

RELATED APPLICATIONS

This application claims the benefit of provisional patent application 61/285,140 filed on Dec. 9, 2009, which is hereby incorporated by reference.

FIELD

This disclosure relates in general to the field of photovoltaics and solar cells, and more particularly to back contact back junction thin solar cells and methods for manufacturing.

BACKGROUND

Currently, crystalline silicon has the largest market share in the photovoltaics (PV) industry, accounting for over 80% of the overall PV market share. And although moving to thinner crystalline silicon solar cells is long understood to be one of the most potent and effective strategy for PV cost reduction (because of the relatively high material cost of crystalline silicon wafers used in solar cells as a fraction of the total PV module cost), utilizing thinner crystalline is fraught with the problem of mechanical breakage caused by thin and often large substrate sizes. Other problems include inadequate light trapping in the thin structure because silicon is an indirect bandgap semiconductor material. Further, it is difficult balance the requirement of high mechanical yield and reduced wafer breakage rate with high manufacturing yields in PV factories in a cost effective manner.

On a standalone crystalline silicon solar cell without support, moving even slightly thinner than the current thickness range of 140 μm-250 μm starts to severely compromise mechanical yield during manufacturing. Thin film silicon is particularly mechanically fragile causing manufacturing and processing difficulties. Thus, solutions directed to process very thin solar cell structures may utilize a cell process during which the cell is fully supported by a host carrier throughout, or a cell process which utilizes a novel self-supporting, standalone, substrate with an accompanying structural innovation.

Although, in the past, there have been attempts in solar industry to use carriers such as glass for thin substrates, these carriers have suffered from serious limitations including low maximum processing temperatures (in the case of glass) which potentially compromises the solar cell efficiency. There have also been attempts to make small area thin cells which do not have serious breakage concerns; however, large cell areas are required for commercial viability.

Achieving high cell and module efficiency with a low fabrication cost is critical in solar cell development and manufacturing. Back junction/back contacted cell architecture is capable of very high efficiency—primarily because there is no metal shading on the front side and no emitter on the front which helps result in a high blue response, and also because of the potentially low metal resistance on the backside. It is known to those versed in the field that back contacted cell demands a very high minority carrier diffusion length to substrate thickness ratio (while a good criteria to have for any solar cell architecture including front contact cells, this is especially important for back contact cells). The ratio should typically be greater than five.

Because cell thickness cannot be reduced easily without compromising mechanical yield, for current back contact back junction solar cells the emphasis is to use a very high lifetime material. And while this may result in a larger diffusion length, using a high lifetime material also increases the substrate cost. However, by using thin cells, the diffusion length does not have to be as high, resulting in an ease in the material quality requirements and thus the cost of the cell. This cost reduction is in addition to the obvious cost reduction of using less silicon. Thus, a back contact/back junction cell on a very thin crystalline silicon substrate has both a large cost and performance advantage.

SUMMARY

In accordance with the disclosed subject matter, innovative structures and methods for manufacturing very thin crystalline silicon, large area (suitable for commercial application), back contact/back junction solar cells are provided.

Back contact back junction three dimensional solar cell and methods for manufacturing are provided. The back contact back contact back junction three dimensional solar cell comprises a three-dimensional substrate. The substrate comprises a light capturing frontside surface with a passivation layer, a doped base region, and a doped backside emitter region with a polarity opposite the doped base region. A backside passivation layer is positioned on the doped backside emitter region. Backside emitter contacts and backside base contacts connected to metal interconnects and selectively formed on three-dimensional features of the backside of three-dimensional solar cell.

The disclosed subject matter, as well as additional novel features, will be apparent from the description provided herein. The intent of this summary is not to be a comprehensive description of the claimed subject matter, but rather to provide a short overview of some of the subject matter's functionality. Other systems, methods, features and advantages here provided will become apparent to one with skill in the art upon examination of the following FIGURES and detailed description. It is intended that all such additional systems, methods, features and advantages included within this description, be within the scope of the accompanying claims.

BRIEF DESCRIPTIONS OF THE DRAWINGS

For a more complete understanding of the disclosed subject matter and advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings in which like reference numbers indicate like features and wherein:

FIGS. 1A and 1B are side and top view of a reusable template;

FIGS. 2A and 2B are photographs of a silicon substrate;

FIG. 3 is a process flow showing a fabrication process of making a back contact back junction thin solar cell;

FIGS. 4A-4C are cross sectional diagrams of the making a reusable template;

FIGS. 5A through 5D are cross sectional diagrams of the making a substrate

FIGS. 6A through 6H are cross sectional diagrams of a solar cell after key cell fabrication process steps of the flow of FIG. 3;

FIG. 7 is a process flow for making an example solar cell;

FIGS. 8A through 8H are cross-sectional views of a solar cell after key processing steps of the fabrication process flow of FIG. 7;

FIG. 9 is a process flow for making another example solar cell;

FIG. 10 is a cross-sectional view of the final structure of the cell of FIG. 9;

FIG. 11 is a process flow for making another example solar cell;

FIGS. 12A-12H are cross-sectional diagrams illustrating the cell after key fabrication steps of the process flow of FIG. 11;

FIG. 13 illustrates the process flow of making another example solar cell;

FIG. 14 is a cross-sectional view of the final structure of the cell of FIG. 13;

FIG. 15 illustrates the process flow of making another example solar cell;

FIG. 16 is a cross-sectional view of the final structure of the cell of FIG. 15;

FIG. 17 illustrates the process flow of making another example solar cell;

FIGS. 18A-18F are cross-sectional views of the cell after key processing steps of the flow of FIG. 17;

FIG. 19 illustrates a process flow for making another example solar cell;

FIG. 20 is a cross-sectional view of the final structure of the cell of FIG. 19;

FIG. 21 illustrates a process flow for making another example solar cell;

FIG. 22 is a cross-sectional view of the final structure of the cell of FIG. 21;

FIG. 23 illustrates a process flow for making another example solar cell; and

FIG. 24 is a cross-sectional view of the final structure of the cell of FIG. 23.

DETAILED DESCRIPTION OF THE SPECIFIC EMBODIMENTS

The following description is not to be taken in a limiting sense, but is made for the purpose of describing the general principles of the present disclosure. The scope of the present disclosure should be determined with reference to the claims. Exemplary embodiments of the present disclosure are illustrated in the drawings, like numbers being used to refer to like and corresponding parts of the various drawings.

The present disclosure provides structural solutions and fabrication process solutions for back contact back junction thin semiconductor solar cells. And although described with reference to silicon such thin film silicon substrates (TFSS), other semiconductor materials such as germanium or gallium arsenide may also be used without departing from the scope of the disclosed structures and methods. Heterojunctions and multijunction solar cells using silicon or other semiconductor materials are also within the scope of the disclosed subject matter. Further, the three-dimensional back contact back junction solar cells and fabrication methods are applicable to any three-dimensional shapes/structures or microstructures on a substrate but are shown and described as inverted pyramidal structures for explanatory purposes. The term “PyCell” herein refers to an inverted pyramidal structure contact back junction solar cell.

In operation, large area (in the range of 156 mm×156 mm), thin solar cell substrates with a general thickness of less than 100 um (more specifically in 15 um to 50 um range) are first manufactured using epitaxial growth on top of a reusable template, and are subsequently dislodged. The reusable template may have a three dimensional structure, or in another embodiment be substantially planar. It is reused several times for epi growth, which amortizes template cost. The TFSS is released from the template using a sacrificial layer which not only is able to transfer the crystallinity from template to the TFSS, but is also easily removed selectively compared to the TFSS and the reusable template. One example of the sacrificial layer is porous silicon, whose porosity can be modulated or graded to achieve both the aforementioned critical functions. After the thin solar cell substrates are manufactured using above means, a key challenge is to handle these TFSS during fabrication of the solar cell without breakage and cracking. From a cost-to-ownership point of view, it is advisable to deposit very thin layers of silicon. As the layers get thinner, it can become advisable to add reinforcement to the thin layer substrate, in order to ensure high mechanical yield through the process flow—for example a large (156 mm×156 mm pseudo-square) 3-D TFSS with an ultra-thin (1 m to 30 m) silicon layer. The following structures and methods address TFSS handling problems as well as provide increased overall efficiency.

FIGS. 1A and 1B are cross-sectional and top views (respectively) of a PyCell reusable silicon template. FIG. 1A illustrates the partial cross-section of the re-usable inverted pyramid template. The pyramid template cross-section as shown consists of large pyramid cavities and small pyramid cavities. Since the pyramid-shape cavities are chemically etched by anisotropic silicon etching, the angle between the sidewall and the top lateral plane is about 54.7°, which is angle between the (111) and (100) silicon crystallographic planes. FIG. 1B illustrates the top view of a fabricated template of the present invention. The structured silicon template consists of anisotropically etched large pyramid cavity and small pyramid cavity. The top opening size of the large cavities is in the range of 10 μm to 1 mm and the top opening size of the small cavities is partial the size of the large cavities. As an example, the large cavity opening is about 200 μm and small cavity opening is about 100 μm. In this case, the depth of the large cavities is about 140 μm and the depth of the small cavities is about 70 μm.

FIGS. 2A and 2B are photographs of the backside and frontside views of a PyCell silicon substrate. FIG. 2A illustrates the substrate backside, on where all the base and emitter contacts, junctions, metal fingers and busbars are made. Since the backside surface is not planar, the contacts and metal fingers are preferred to be placed on top surfaces, such as the top of the ridges. FIG. 2B illustrates the substrate front side, which is also the sunny side of the solar cell. The regular pyramidal structures provide effective light trapping effects.

FIG. 3 is a process flow showing a fabrication process of making a back contact back junction thin solar cell, PyCell-1. The process flow consists of three columns: Template, Substrate and Cell—which correspond to the template, substrate, and cell processing steps. FIGS. 4A through 4C are cross sectional diagrams of the making a reusable template after key fabrication process steps as it is manufactured according to the Template fabrication process of FIG. 3.

As shown in FIG. 4A, the template making process starts with using a mono-crystalline (100) silicon wafer. The starting wafer could be in circular, square, or pseudo-square shapes. This step involves forming a thin hard masking layer on the exposed wafer surfaces. The hard masking layer is used to masking the silicon surface areas that are not to be etched in the later steps. A proper hard masking layer includes, but is not limited to, thermally grown silicon oxide and low-pressure vapor phase deposited (LPCVD) silicon nitride. The next step involves a photolithography step, which consists of photoresist coating, baking, UV light exposure over a photomask, post baking, photoresist developing, wafer cleaning and drying. With these steps, the pattern on the photomask, such as staggered square openings, is transferred to the photoresist layer. The patterned photoresist layer is used as a soft masking layer for the hard masking layer etching in the subsequent step. The next step involves further transferring the photoresist pattern to the hard masking layer underneath by chemical etching, such as etching a thin silicon oxide layer with buffered HF solution. Other wet etching methods and dry etching methods as known in semiconductor and MEMS wafer processing could also be used. In the next step, the remaining soft masking layer, i.e. the photoresist layer is removed and the wafer is cleaned. Examples of photoresist removal process include wet methods, such as using acetone or piranha solution (a mixture of sulfuric acid and hydrogen peroxide), or dry methods, such as oxygen plasma ashing. In the next step, the wafers are batch loaded in an anisotropic silicon wet etchant, such as KOH solution. The typical etch temperature is in the range of 50° C. to 80° C. and etch rate is about 0.2 μm/min to 1 μm/min. In one embodiment, the etched depth of the large pyramidal cavity is in the range of 50 μm to 200 μm. TMAH (tetramethylammonium hydroxide) is another alternative anisotropic silicon etching chemical. The KOH or TMAH silicon etch rate depends upon the orientations to crystalline silicon planes. The (111) family of crystallographic planes are etched at a very slow rate and they are normally the “stop” planes for anisotropic etching of a (100) silicon wafer with patterned hard mask. As a result, the intersections of (111) planes produce the pyramidal cavities with sharp tip cavity bottoms and four sidewalls of (111) planes as shown in FIG. 4B. In the last step of the template making, the hard etching mask is removed as shown in FIG. 4C.

FIGS. 5A through 5D are cross sectional diagrams of the making a substrate after key fabrication process steps according to the substrate fabrication process of FIG. 3. The structural features depicted in the cross sectional diagrams of FIGS. 5A through 5D are consistent unless otherwise noted.

The first step starts with the pre-structured template on which a porous silicon layer is formed by electrochemical anodic HF etching of silicon on both the front and back sides of the template surfaces. During the porous silicon forming in an HF/IPA (or HF/acetic acid) solution, the electrical current polarity is periodically switched between positive and negative currents so that each template side/surface is consecutively etched in order to form the bilayer or multi-layer porous silicon structure on both template sides. In addition to the periodical current polarity switching, the current intensity is also changed in a controlled manner to form a porous silicon layer that preferably consists of two thin layers with different (low and high) porosities. The first thin porous silicon layer is on the top and is first formed from the bulk silicon wafer. The first thin layer preferably has a lower porosity of 15% to 30%. The second thin porous silicon layer is directly etched into the bulk silicon and is underneath the first thin layer of porous silicon. The 2^nd thin porous silicon layer preferably has a higher porosity in the range of 40%˜80%. The top lower porosity layer is used as a crystalline seed layer for high quality epitaxial silicon growth and the underneath higher porosity porous silicon layer is used for facilitating TFSS releasing due to its lower density of physical connections (between the epitaxial and bulk silicon interfaces) and its weak mechanical strength. Alternatively, a single porosity release layer with a progressively increased porosity from top to bottom can also be used. In this case, the top portion of the porous silicon layer has a low porosity of 15% to 30% and the lower portion of the porous silicon layer has a high porosity of 40% to 80%. In the next step, before the epitaxial silicon growth, the wafer is baked in a high temperature (at 950° C. to 1200° C., and preferably in the range of 1050° C. to 1150° C.) hydrogen environment within the epitaxial silicon deposition reactor in order to form coalesced structures (with relatively large voids) within the higher-porosity buried porous silicon layer while forming a continuous surface seed layer of crystalline silicon on the top of the lower-porosity porous silicon layer. Next, a mono-crystalline epitaxial silicon layer is deposited on the template, preferably in a high-throughput large-batch epitaxial furnace. The epitaxial layer may be in-situ doped. In this process flow the bulk base of the epitaxial layer is n (phosphorous) type doped, the inside layer may be n- (phosphorous) type doped with a doping level higher than the n-type base, such as to form the Front-Surface-Field (FSF), and the outer layer may be p (boron) doped to form the emitter region of the solar cell. The epitaxial layer is thin, preferably 100 μm. More specifically, the base doping may be achieved using phosphine (phosphorous imparting) gas in addition to silicon imparting (trichlorosilane—TCS) and other necessary gases, and when emitter growth is done toward the end of the epitaxial process the reactor may be programmed to switch to diborane (boron imparting) instead of phosphine. The thicknesses of the base and the emitter region should be optimized to give the best solar cell performance. In one embodiment, a base thickness less than 100 μm with doping between 5e14 and 1e17 cm-3 and an emitter thickness of less than 3 μm with doping between 1e18 and 3e20 cm-3 are preferred. The emitter may also be multi-step with each step resulting in different concentration. This epitaxial structure can facilitate a high open circuit voltage (Voc) of the solar cell and thus a higher efficiency. In the next step, a thin oxide layer is thermally grown on the epitaxial surface. The thin oxide layer is used for solar cell surface passivation and a masking layer for subsequent selective surface openings. FIG. 5A illustrates the cross-sectional view after the thin oxidation step.

In the next step, a reinforcement layer is applied to fill the cavities and cover the entire top surfaces. The material of the reinforcement layer is required to withstand high temperatures, such as 200° C. to 300° C. for the subsequent front surface PECVD silicon nitride passivation process. As an example, Polyimide can be used for the said reinforcement purpose. The reinforcement layer may be applied by spray coating followed by curing or by a thin film vacuum lamination process. Alternatively, the reinforcement can be achieved by clamping carrier plate. The clamping can be done using vacuum forces or assisted or accomplished by means of an electrostatic chuck (ESC) or a mobile electrostatic carrier (MESC). FIG. 5B shows the cross-sectional view after the backside reinforcement. In the next step as shown in FIG. 3, the template edge top surface and bevel surface are mechanically polished so that the epitaxial silicon layer is physically disconnected from the template at its edges. The border of the PyCell TFSS may be further defined on template by shallow laser cutting partially through the epitaxial layer without damaging the underneath template surfaces. In the next step, the reinforced epitaxial layer of silicon is released/separated from the template. In one of the disclosed methods, the TFSS is released in an ultrasonic DI-water bath. Yet in another disclosed method, the TFSS is released by direct pulling with wafer backside and top epitaxial vacuum chucked. The released 3-D TFSS has a thickness in the range of in the range of 50 μm to 200 μm (depending on the inverted pyramidal cavity depth on the re-usable template) without taking into account of the reinforcement layers. A reinforced 3-D TFSS has a thickness in the range of 0.2 mm to 1 mm. In the next step, the released TFSS backside surface is cleaned by short silicon etching using KOH or TMAH solutions to remove the silicon debris and fully or partially remove the quasi-mono-crystalline silicon (QMS) layer. In the meantime and after removal of the edge epitaxial silicon layer from the template, the template is cleaned by using diluted HF and diluted wet silicon etch solution, such as TMAH and/or KOH to remove the remaining porous silicon layers and silicon particles. Then the template is further cleaned by conventional silicon wafer cleaning methods, such as SC1 and SC2 wet cleaning (or the so-called RCA cleaning process) to removal possible organic and metallic contaminations. Finally, after proper rinsing with DI water and drying, the template is ready for another re-use cycle. As shown in FIG. 5C, the reinforced PyCell substrate, referred to as 3-D TFSS, is made and ready for the subsequent cell fabrication processes.

FIGS. 6A through 6H are cross sectional diagrams of the solar cell PyCell-1 after key cell fabrication process steps as it is manufactured according to the fabrication process of FIG. 3. The structural features depicted in the cross sectional diagrams of FIGS. 6A through 4H are consistent unless otherwise noted. In FIGS. 6A through 6H the cross-sectional diagrams of the solar cell show the cell with the frontside (sunnyside) facing downwards and backside (non-sunny/contact side) facing upwards to better illustrate processing steps.

As shown in FIG. 6A, a PECVD silicon nitride layer of preferably 60 nm to 100 nm thickness is deposited on the front side, which is the pyramid side (sunny side) of the PyCell substrate. The PECVD silicon nitride layer is used as a surface passivation layer and an anti-reflection coating (ARC) layer. Reduction of the carrier recombination at the surface defects is an important requirement in achieving high-efficiencies for crystalline silicon solar cells and it is even more critical for thin and large silicon substrates because of larger surface to volume ratio. Surface passivation with dielectric layers is an effective method to reduce the carrier recombination rate at surfaces, because good surface passivation layers not only provide reduction of the surface state density and the presence of the fixed insulator charges in the dielectric layers also provides an active field that repels the minority carriers from the surface therefore further reducing the rates of surface carrier recombination. The silicon nitride layer also serves as an anti-reflection coating (ARC) layer at front surface as well as an enhanced internal optical reflection layer for better light trapping at front surface. In the next step, as shown in FIG. 6B, the front side of the PyCell substrate is reinforced by applying a layer of supporting material, such as PV-grade EVA, Z68 or silicone. Application methods include, but are not limited to, thermal spraying and vacuum lamination. After the front side reinforcement, the backside reinforcement layer may be fully removed, such as by de-clamping the MESC or MOVAC carrier plate, or removal of the deposited layer, such as the shown Polyimide layer. In another embodiment, the backside reinforcement layer (such as the Polyimide layer) may be partially removed to partially expose the substrate backside surfaces so that junction, contacts, and metallization can be made.

In the next step, aligned laser ablation is used to open the emitter contact openings from the ridges on the backside. The laser ablation wavelength, pulse width and energy dose are required to selectively remove the dielectric layer (thin oxide layer in this case) without or with minimum damage to the silicon surface underneath. The cross-sectional view after the partial removal of the backside reinforcement layer and after the emitter contact opening is shown in FIG. 6C.

In the next step, phosphorous liquid dopant is deposited on the surface by either blanket spraying or aligned printing. After curing the phosphorous liquid dopant, an aligned laser beam is directed to the base contact regions. The controlled laser beam opens the base contact by ablating the dielectric layers on top of the base contact regions as well as driving-in the phosphorous dopant to form n⁺⁺ base junctions. The cross-sectional view during the laser processing step is shown in FIG. 6D. In the next step, the remaining phosphorous dopant is removed in a wet etching process, such as using a diluted HF etchant. FIG. 6E illustrates the formed emitter contact opening, base contact opening, and the n++ base junction. It is to be noted that the emitter and base contact openings in the PyCell-1 flow are discrete, which means they are not connected to form continuous interdigitated line openings. In the next step, inkjet printing of metal, such as nickel (Ni) nanoparticle ink is conducted on the ridge surfaces to connect the contact openings into interdigitated emitter and base finger patterns. After sintering, the printed Ni thin pattern also serves as the seed layer for subsequent thicker metal electroplating process. The Ni printed cross-sectional view is shown in FIG. 6F and the electroplated thick Ni+Cu+Sn cross-sectional view is shown in FIG. 6G.

At this stage, solar cell (PyCell-1) is completed and it may proceed to subsequent testing and module assembly steps. However, in an alternative embodiment, to further increase the cell efficiency by implementing an improved passivation layer stack and a back reflection mirror the backside reinforcement layer may be fully removed and a thin aluminum oxide passivation layer and a thin PVD aluminum mirror layer selectively deposited sequentially on the backside surfaces that do not have metal contacts. The PECVD deposited Al₂O₃ layer improves the backside surface passivation effects due to the existence of fixed charge within the PECVD Al₂O₃ layer that may effectively reduce the minority carrier surface recombination rates. The PVD Al thin layer is used as the back mirror to reflect the light back into silicon. The deposition of PECVD Al₂O₃ and PVD Al may be conducted with shadow masks that are properly aligned to cover the electroplated emitter and base busbar contact regions to prevent Al₂O₃ and Al layers coverage. The full removal of the backside reinforcement layer may also be conducted right after the implementation of the front side reinforcement layer. FIG. 6H shows the cross-sectional view of the PyCell-1 solar cell with improved backside surface passivation and added PVD Al back mirror.

FIG. 7 is a process flow of making another example of the PyCell solar cells (PyCell-2) according to the present invention. The reusable template and PyCell substrate making processes of PyCell-2 may be the same as PyCell-1. The cell process steps may also be same before the emitter contact opening step. Then, instead of making discrete emitter and base contact openings, the PyCell-2 design comprises continuous interdigitated line opening for both emitter and base contacts. As a result, the step of inkjet printing of metal nanoparticle ink is eliminated because the purpose of this Ni inkjet printing in PyCell-1 is to create continuous interdigitated line base and emitter patterns from the discrete contact openings.

FIGS. 8A through 8H are cross-sectional views of a solar cell after key fabrication steps of the PyCell-2 cell process flow. FIGS. 8A through 8C are same as FIG. 6A through 6C with the same processing steps and structure designs. However, the aligned laser beam shown in FIG. 8D scans continuous interdigitated lines to make continuous interdigitated line base and emitter contact openings (shown in FIG. 8E). The base junctions as shown also have a continuous interdigitated line shape. After the contact opening and base junction forming, electroless plating of Ni followed by electroplating of Cu and Sn is conducted on the exposed silicon surfaces for form the emitter and base metal fingers and busbars, as shown in FIG. 8G. As in FIG. 6H, FIG. 8H illustrates the alternative embodiment of PyCell-2 that involves PECVD Al₂O₃ passivation layer and PVD Al back mirror layer. The PECVD Al₂O₃ passivation layer and PVD Al back mirror layer do not cover the emitter and base busbar contact areas, which are not shown in FIG. 8(h).

FIG. 9 is a process flow for making another example of PyCell solar cells, PyCell-3A. Compared to PyCell-1, one difference of PyCell-3A is that the backside reinforcement layer also serves as a backside diffuse mirror. The backside diffuse mirror reflects the pass-through light back into the silicon material in various directions. For example, thermally sprayed PTFE backside reinforcement layer may also be used as a diffuse mirror layer simultaneously. FIG. 10 is a cross-sectional view of the final structure of the PyCell-3A cell process flow of FIG. 9—with backside reinforcement and diffuse mirror layers shown.

FIG. 11 is a process flow for making another example of PyCell solar cells, PyCell-3B. The reusable template and PyCell substrate making processes of PyCell-3B may be the same as PyCell-1. Key embodiments of the PyCell-3B are that it has selective emitters and the backside reinforcement layer also serves as the back diffuse mirror layer. The base and emitter contact openings are discrete; therefore the step of inkjet printing of Ni nanoparticle ink is needed to create continuous interdigitated line base and emitter patterns from the discrete contact openings.

FIGS. 12A-12H are cross-sectional diagrams illustrating the cell after key fabrication steps of the PyCell-3B cell process flow of FIG. 11. The structural features depicted in the cross sectional diagrams of FIGS. 12A-12H are consistent unless otherwise noted.

The cell process of PyCell-3B starts from the backside reinforced substrate and backside reinforcement layer also is used as a back mirror. As shown in FIG. 12A, a PECVD silicon nitride layer of 60 nm to 100 nm thick is deposited on the cell frontside, which is the pyramid side of the PyCell substrate. The PECVD silicon nitride layer is used as a surface passivation layer and an anti-reflection coating (ARC) layer. In the next step, as shown in FIG. 12B, the front side of the PyCell substrate is reinforced by depositing of a layer of supporting material, such as PV-grade EVA, Z68 or silicone. The depositing methods includes but not limited to thermal spraying and vacuum lamination. After the front side reinforcement, the backside reinforcement layer, such as the PTFE layer, may be partially or locally removed to expose partially the substrate backside surfaces that junction, contacts and metallization can be made. The partial removal of the backside reinforcement layer may be achieved by selective laser ablation. As shown in FIG. 12C, in the next step, boron liquid dopant is deposited on the surface by either blanket spraying or aligned printing. After curing the boron liquid dopant, an aligned laser beam is directed to the emitter contact regions. The controlled laser beam opens the emitter contact by ablating the dielectric layer (thin silicon oxide) on top of the emitter regions as well as driving-in the boron dopant for forming the p⁺⁺ selective emitter junctions in the same time. In the next step, the remaining boron dopant is removed in a wet etching process, such as using a diluted HF etchant, and the selective emitter junction is fabricated—shown in FIG. 12D. The selective emitter p⁺⁺ junctions have higher doping concentration than the p⁺ epitaxial emitter layer and the depth of the selective emitter junction may be deeper than the epitaxial emitter layer.

Next, as shown in FIG. 12E, a similar process is conducted to form the selective base junction. This process starts with phosphorous liquid dopant deposited on the surface by either blanket spraying or aligned printing. After curing the phosphorous liquid dopant, an aligned laser beam is directed to the base contact regions. The controlled laser beam opens the base contact by ablating the dielectric layer (thin silicon oxide) on top of the base emitter regions as well as driving-in the phosphorous dopant for forming n⁺⁺ selective emitter junctions at the same time. In the next step, the remaining boron dopant is removed in a wet etching process, such as using a diluted HF etchant, and the selective base junction is fabricated—shown in FIG. 12F. The selective base n⁺⁺ junction is formed by counter doping the epitaxial p⁺ emitter layer and the base junction depth is deeper than the epitaxial emitter layer. FIG. 12F illustrates the formed emitter contact opening, base contact opening, the p⁺⁺ selective emitter junction, and the n⁺⁺ base junction. It is to be noted that the emitter and base contact openings in the PyCell-3B flow are also discrete, which means they are not connected to form continuous interdigitated line openings.

In the next step, inkjet printing of nickel (Ni) nanoparticle ink is conducted on the ridge surfaces to connect the contact openings into interdigitated emitter and base finger patterns. After sintering, the printed Ni thin pattern also serves as the seed layer for subsequent thicker metal electroplating process. The Ni printed cross-sectional view is shown in FIG. 12G and the electroplated thick Ni+Cu+Sn cross-sectional view is shown in FIG. 12H. At this stage, the PyCell-3B solar cell is complete (shown in FIG. 12H) and it may proceed to subsequent testing and module assembly steps.

FIG. 13 illustrates the process flow of making another example of PyCell solar cell, PyCell-4A. The reusable template and PyCell substrate making processes of PyCell-4A may be substantially similar as PyCell-1. An exception is that the backside reinforcement layer also serves as a backside diffuse mirror purpose in PyCell-4A. The backside diffuse mirror reflects the pass-through light back into the silicon material in various directions. For example, thermal sprayed PTFE backside reinforcement layer may also be used as a diffuse mirror layer simultaneously. The cell process steps may also be the same before the emitter contact opening step. However, instead of making discrete emitter and base contact openings, the PyCell-4A design makes continuous interdigitated line opening for both emitter and base contacts. As a result, the step of inkjet printing of Ni nanoparticle ink is eliminated because the purpose of this Ni inkjet printing in PyCell-1 is to create continuous interdigitated line base and emitter patterns from the discrete contact openings. In other words, the cell process flow of PyCell-4A may be the same as described for FIGS. 7 and 8, except the contact openings are continuous interdigitated line patterns and the inkjet printing of Ni nanoparticle step is eliminated. Also, because the back mirror effects provided by the backside reinforcement layer, the need of applying PECVD Al₂O₃ passivation layer and PCD Al layer on the backside is eliminated in PyCell-4A design.

FIG. 14 is a cross-sectional view of the final structure of the PyCell-4A cell process flow according to the present invention. The backside reinforcement and diffuse mirror layer are shown and the emitter and base contact openings and the base junction are continuous interdigitated line patterns.

FIG. 15 illustrates the process flow of making another example of PyCell solar cells, PyCell-4B. The reusable template and PyCell substrate making processes of PyCell-4B are mostly same as PyCell-1. An exception is that the backside reinforcement layer also serves as a backside diffuse mirror purpose. The backside diffuse mirror reflects the pass-through light back into the silicon material in various directions. For example, thermal sprayed PTFE backside reinforcement layer can also be used as a diffuse mirror layer simultaneously. The cell process flow of PyCell-4B is mostly same as the PyCell-3B cell process flow except the emitter and base contact openings and junctions are in continuous interdigitated line patterns. PyCell-4B also has selective emitter (p⁺⁺) junctions made in the same method as the PyCell-3B cell process, except the selective emitter design of the PyCell-4B is in continuous interdigitated line pattern.

FIG. 16 is a cross-sectional view of the final structure of the PyCell-4B cell process flow of FIG. 15. The PyCell-4B cell has formed selective emitters. The backside reinforcement layer is also served as the diffuse mirror layer. The emitter and base contact openings and the base junction are continuous interdigitated line patterns.

FIG. 17 illustrates the process flow of making another example of PyCell solar cells, PyCell-4C. The reusable template and PyCell substrate making processes of PyCell-4C are mostly same as PyCell-1. An exception is that the backside reinforcement layer also serves as a backside diffuse mirror purpose. The backside diffuse mirror reflects the pass-through light back into the silicon material in various directions. For example, thermal sprayed PTFE backside reinforcement layer can also be used as a diffuse mirror layer simultaneously. The cell process flow of PyCell-4C is mostly same as the PyCell-4B cell process flow except the emitter and base contact openings and junctions are formed within a single laser ablation and doping process. PyCell-4C also has selective emitter (p⁺⁺) junctions made in the same method as the PyCell-4B cell process.

FIGS. 18A-18F are cross-sectional views after key processing steps of the PyCell-4C cell process flow according to the present invention. The cell process of PyCell-4C starts from the backside reinforced substrate and backside reinforcement layer also is used as a back mirror. As shown in FIG. 18A, a PECVD silicon nitride layer of 60 nm to 100 nm thick is deposited on the front side, which is the pyramid side of the PyCell substrate. The PECVD silicon nitride layer is used as a surface passivation layer and an anti-reflection coating (ARC) layer. In the next step, as shown in FIG. 18B, the front side of the PyCell substrate is reinforced by depositing of a layer of supporting material, such as PV-grade EVA, Z68 or silicone. Depositing methods include, but are not limited to, thermal spraying and vacuum lamination. After the front side reinforcement, the backside reinforcement layer, such as the PTFE layer, may be partially or locally removed to expose partially the substrate backside surfaces where junction, contacts, and metallization are formed. The partial removal of the backside reinforcement layer may be achieved by selective laser ablation. As shown in FIG. 18C, in the next step, boron liquid dopant and phosphorous liquid dopant are deposited on the cell surface by an inkjet process. The printed of phosphorous and boron liquids may be conducted within a single print load, in which the said two types of liquid are dispensed from two separated printing nozzles. Alternatively, they may be printed in two subsequent printing loads with optional drying step in between. Next, both the printed phosphorous and boron dopant are fully dried and cured, such as in a convection oven.

In the next step, as shown in FIG. 18D, an aligned laser beam is directed to the emitter contact regions. The controlled laser beam opens the contacts by ablating the dielectric layer (thin silicon oxide) on top of the contact regions as well as driving-in the dopants for forming the p⁺⁺ selective emitter junctions and n⁺⁺ base junctions in the same time. In the next step, the remaining boron and phosphorous dopants are removed in a wet etching process, such as using a diluted HF etchant, and the selective emitter junction and base junction are formed—shown in FIG. 18E. The junctions and contact openings are in continuous interdigitated line pattern. The selective emitter p⁺⁺ junction has higher doping concentration than the p⁺ epitaxial emitter layer and the depth of the selective emitter junction may be deeper than the epitaxial emitter layer. Next, as shown in FIG. 18F, electroplating of thick Ni+Cu+Sb metal layers is conducted and plated metal fingers form interdigitated metal lines and base and emitter busbars. At this stage, the PyCell-4C solar cell is complete, shown in FIG. 18F, and it may proceed to the subsequent testing and module assembly steps.

FIG. 19 illustrates a process flow for making another example of PyCell solar cell, PyCell-5A. The reusable template and PyCell substrate making processes of PyCell-5A are mostly same as PyCell-1. An exception is that the backside reinforcement layer also serves as a backside diffuse mirror purpose. The backside diffuse mirror reflects the pass-through light back into the silicon material in various directions. For example, thermal sprayed PTFE backside reinforcement layer may also simultaneously be used as a diffuse mirror layer. The cell process flow of PyCell-5A is mostly same as the PyCell-4A cell process flow. However to further improve the back diffuse mirror effects; an additional diffuse mirror stack is applied on the cell backside. After making the cell as described for PyCell-4A, a low density PTFE layer is spray coated and covers the backside surface except the emitter and base busbar contact areas, which are covered by a shadow mask. Next, a thin PVD Al layer is deposited on the backside and on top of the added PTFE layer, and the PVD Al serves as the back reflection mirror. The emitter and base busbar contact areas are also covered by a shadow mask during the PVD Al deposition process so that the emitter and base metals are not shunted by the PVD Al.

FIG. 20 is a cross-sectional view of the final structure of the PyCell-5A cell process flow described in FIG. 19. The PyCell-5A cell has continuous interdigitated emitter and base contact line openings, enhanced back diffuse mirror with additional Low-density PTFE layer, and PVD Al layer on the backside. The PTFE and PVD Al layers do not cover the emitter and base busbar contact areas, which are not shown in FIG. 20. PyCell-5A cell does not have selective emitters.

FIG. 21 is the process flow for making another example of PyCell solar cells, PyCell-5B. The reusable template and PyCell substrate making processes of PyCell-5B are mostly same as PyCell-1. An exception is that the backside reinforcement layer also serves as a backside diffuse mirror. The backside diffuse mirror reflects the pass-through light back into the silicon material in various directions. For example, a thermal sprayed PTFE backside reinforcement layer may also be used as a diffuse mirror layer simultaneously. The cell process flow of PyCell-5B is mostly same as the PyCell-4B cell process flow. However, to further improve the back diffuse mirror effects an additional diffuse mirror stack is applied on the cell backside. After making the cell as described for PyCell-4B, a low density PTFE layer is spray coated and covers the backside surface except the emitter and base busbar contact areas, which are covered by a shadow mask. Next, a thin PVD Al layer is deposited on the backside and on top the added PTFE layer, and the PVD Al serves as the back reflection mirror. The emitter and base busbar contact areas are also covered by a shadow mask during the PVD Al deposition process so that the emitter and base metals are not shunted by the PVD Al.

FIG. 22 is a cross-sectional view of the final structure of the PyCell-5B cell process flow of FIG. 21. Shown, PyCell-5B cell has continuous interdigitated line emitter and base junction and contact openings, enhanced back diffuse mirror with additional Low-density PTFE layer, and PVD Al layer on the backside. The PTFE and PVD Al layers do not cover the emitter and base busbar contact areas, which are not shown in FIG. 22. PyCell-5B cell has selective emitters.

FIG. 23 is a process flow for making another example of PyCell solar cell, PyCell-5C. The reusable template and PyCell substrate making processes of PyCell-5C are mostly same as PyCell-1. An exception is that the backside reinforcement layer also serves as a backside diffuse mirror. The backside diffuse mirror reflects the pass-through light back into the silicon material in various directions. For example, thermal sprayed PTFE backside reinforcement layer may also simultaneously be used as a diffuse mirror layer. The cell process flow of PyCell-5C is mostly same as the PyCell-4C cell process flow. However to further improve the back diffuse mirror effects; an additional diffuse mirror stack is applied on the cell backside. After making the cell as described for PyCell-4C, a low density PTFE layer is spray coated and covers the backside surface except the emitter and base busbar contact areas, which are covered by a shadow mask. Next, a thin PVD Al layer is deposited on the backside and on top the added PTFE layer, and the PVD Al serves as the back reflection mirror. The emitter and base busbar contact areas are also covered by a shadow mask during the PVD Al deposition process, so that the emitter and base metals are not shunted by the PVD Al.

FIG. 24 illustrates the cross-sectional view of the final structure of the PyCell-5C cell process flow in FIG. 23. Shown, PyCell-5C cell has continuous interdigitated line emitter and base junction and contact openings, enhanced back diffuse mirror with additional Low-density PTFE layer, and PVD Al layer on the backside. The PTFE and PVD Al layers do not cover the emitter and base busbar contact areas, which are not shown in FIG. 24. PyCell-5C cell has selective emitters.

In operation, this disclosure describes the structure of back junction back contact crystalline three-dimensional solar cells deposited on a three dimensional structured re-usable template which acts as a high temperature capable carrier to enable on-template processes and the subsequent separation of the three dimensional crystalline solar cells from the template by use of a release layer. Further, reinforcement structures for the three dimensional cells and methods to apply them are described, which enable the use of an ultra-thin semiconductor layer for the three dimensional cell, thus reducing the overall cost and reducing the bulk lifetime requirement of the layer. Also, the use of short laser pulses with sub-nanosecond pulse duration is described to accomplish the contact opening for at least one, preferably both polarities of the contacts to the above described three dimensional back junction back contact solar cell. Also, the use of laser pulses is described to accomplish the doping of the contact areas for at least one, preferably both polarities of the contacts regions to the above described three dimensional back junction back contact solar cell. Several process flows are described as suggestions on how to achieve reinforcement, dielectric layer formation for isolation, passivation, mirror formation, release and metallization. From the suggested example methods, other methods can be derived by those with a skill in the art and are thus also considered within the scope of the disclosed subject matter.

In one embodiment, fabrication methods of making various types PyCell solar cells using an epitaxial silicon layer are provided. The term “ultra-thin” is referred to as a grown material thickness in the range of 1 μm to 50 μm. Two advantages of PyCell compared to a substantially planar solar cell that is made of same ultra-thin silicon layer: (1) given a thickness of a specific range, a PyCell substrate is mechanically more robust than a substantially planar silicon substrate of the same thickness; (2) PyCell microstructures provide natural light trapping effects, so that the need of conducting a front surface texturing process is eliminated. In fact, to make an effective surface texturing (such as average of 5 μm average pyramid height), on a planar silicon surface, consumes some silicon thickness of a planar silicon substrate. Therefore an ultra-thin PyCell substrate saves epitaxial silicon material compared to a substantially planar ultra-thin epitaxial silicon solar cell.

Fabrication method and structural descriptions various types PyCell solar cells with back contact and back junctions are provided. More specifically, the pyramid-shaped side of the PyCell is used as the sunny side, which is referred to as the front side; while the ridge-shaped side of the PyCell is used as the contact, junction, and metallization side, which is referred to as the backside. Furthermore, all the base and emitter contacts, junctions, metal fingers, metal busbars are made on the backside of the PyCell solar cell.

Additional aspects of the present disclosure include in-situ doping steps during epitaxial silicon growth are conducted to form in-situ doped Front Surface Field (FSF) and Emitter doping layer. The in-situ doing concentration profiles may be in steps or in gradient. Short pulsed (such as sub-nanosecond) laser ablation used to create discrete or continuous dielectric contact openings. Laser surface treatment used to perform the doping of the contact areas for at least one, preferably both polarities of the contacts regions to the above described three dimensional back junction back contact solar cell. The backside and the reinforcement layer serving as a diffused back mirror. The formation of selective emitters (higher emitter doping inside emitter contact areas) to increase the cell efficiency. The use of inkjet liquid dopant printing and direct-write laser doping processes are used to make selective emitters and base contacts. In addition to above combinations, novel manufacturing methods using pulsed laser approach are provided. Several process flows are described as suggestions on how to achieve reinforcement, dielectric layer formation for isolation, passivation, mirror formation, release and metallization.

The foregoing description of the preferred embodiments is provided to enable any person skilled in the art to make or use the claimed subject matter. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without the use of the innovative faculty. Thus, the claimed subject matter is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A back contact back junction three-dimensional thin solar cell, comprising:

a three-dimensional deposited semiconductor layer having a frontside and a backside, comprising: a light capturing frontside surface with a passivation layer, a doped base region, and a doped backside emitter region with a polarity opposite said doped base region;

a backside passivation layer on said doped backside emitter region;

backside emitter contacts and backside base contacts connected to metal interconnects and selectively formed on three-dimensional features of the backside of said three-dimensional deposited semiconductor layer; and

a transparent frontside permanent support reinforcement on the frontside of said back contact back junction three-dimensional thin solar cell.

2. The back contact back junction three-dimensional thin solar cell of claim 1, wherein said deposited semiconductor layer is an epitaxial silicon layer with a thickness in the range of 1 to 30 microns.

3. The back contact back junction three-dimensional thin solar cell of claim 1, wherein said doped backside emitter region is an epitaxial in-situ doped emitter region.

4. The back contact back junction three-dimensional thin solar cell of claim 1, wherein said backside emitter contacts and backside base contacts are discretely positioned on three-dimensional features of the backside of said three-dimensional deposited semiconductor layer.

5. The back contact back junction three-dimensional thin solar cell of claim 1, wherein said backside emitter contacts and backside base contacts are formed in a continuous interdigitated pattern on three-dimensional features of the backside of said three-dimensional deposited semiconductor layer.

7. The back contact back junction three-dimensional thin solar cell of claim 1, wherein said light capturing frontside surface with a passivation layer serves as an anti-reflection coating.

8. The back contact back junction three-dimensional thin solar cell of claim 1, wherein said light capturing frontside surface with a passivation layer provides field assisted passivation.

9. The back contact back junction three-dimensional thin solar cell of claim 1, further comprising a backside reinforcement layer filling cavities of the three-dimensional features on the backside of said three-dimensional thin deposited semiconductor layer.

10. A back contact back junction three-dimensional thin solar cell, comprising:

a three-dimensional deposited semiconductor layer having a frontside and a backside, said deposited semiconductor layer having an inverted pyramidal structure wherein backside surface ridges define the openings of inverted pyramidal cavities, comprising: a light capturing frontside surface with a passivation layer, a doped base region, and a doped backside emitter region with a polarity opposite said doped base region;

a backside passivation layer on said doped backside emitter region; and

backside emitter contacts and backside base contacts selectively formed on the backside surface ridges of said three-dimensional deposited semiconductor layer and connected to metal interconnects.

11. The back contact back junction three-dimensional thin solar cell of claim 10, a transparent permanent frontside support reinforcement on the frontside of said back contact back junction three-dimensional thin solar cell.

12. The back contact back junction three-dimensional thin solar cell of claim 10, wherein said deposited semiconductor layer is an epitaxial silicon layer with a thickness in the range of 1 to 30 microns.

13. The back contact back junction three-dimensional thin solar cell of claim 10, wherein said doped backside emitter region is an epitaxial in-situ doped emitter region.

14. The back contact back junction three-dimensional thin solar cell of claim 10, wherein said inverted pyramidal cavities comprise a plurality of differently sized inverted pyramidal cavities.

15. The back contact back junction three-dimensional thin solar cell of claim 10, wherein said inverted pyramidal cavities comprise a set of larger inverted pyramidal cavities and a set of smaller inverted pyramidal cavities.

16. The back contact back junction three-dimensional thin solar cell of claim 10, wherein said backside emitter contacts and backside base contacts are discretely positioned on the backside surface ridges of the inverted pyramidal cavities on the backside of said three-dimensional thin deposited semiconductor layer.

17. The back contact back junction three-dimensional thin solar cell of claim 10, wherein said backside emitter contacts and backside base contacts are formed on the ridges of the inverted pyramidal cavities on the backside of said three-dimensional thin deposited semiconductor layer in a continuous line pattern.

18. The back contact back junction three-dimensional thin solar cell of claim 10, further comprising a backside reinforcement layer at least partially filling cavities of the inverted pyramidal cavities on the backside of said three-dimensional thin deposited semiconductor layer.

19. A method for the manufacture of a three-dimensional back contact back junction thin solar cell from a crystalline semiconductor layer, the method providing continuous structural support to said crystalline semiconductor layer, the method comprising:

forming a conformal porous semiconductor layer on a three-dimensional template, said three-dimensional template having an inverted pyramidal structure with backside surface ridges defining openings of inverted pyramidal cavities, wherein said template provides structural support and acts as a high temperature temporary carrier for back contact back junction solar cell backside processing steps, said backside processing steps comprising:

depositing a conformal doped base crystalline semiconductor layer on said porous semiconductor layer;

forming a conformal doped emitter layer on said doped base crystalline semiconductor layer;

separating said doped base crystalline semiconductor layer from said template along said porous semiconductor layer, wherein a cell backside reinforcement layer is attached to said solar cell backside prior to release to provide support for cell frontside processing steps, said frontside processing step comprising forming a light capturing frontside surface with a passivation and anti-reflection layer on the frontside of said crystalline semiconductor layer;

attaching a transparent permanent frontside reinforcement support to the cell frontside;

depositing a backside passivation dielectric layer on said doped emitter layer;

forming selective backside base and emitter contact openings through said dielectric layer on the ridges of said inverted pyramidal cavities;

doping exposed regions to form emitter regions and base regions; and

metalizing the cell backside to form backside base and emitter contacts on the ridges of said inverted pyramidal cavities.

20. The method of claim 19, wherein said cell backside reinforcement layer serves as a backside diffuse mirror for said three-dimensional back contact back junction thin solar cell.

21. The method of claim 19, wherein the step of depositing a doped base crystalline semiconductor layer comprises depositing a doped base epitaxial silicon layer with a thickness in the range of 1 to 30 microns.

22. The method of claim 19, wherein the step of forming a doped emitter layer on said doped base crystalline semiconductor layer comprises forming an in-situ doped emitter epitaxial layer.

23. The method of claim 19, wherein pulsed duration laser ablation is used to form selective backside base and emitter contact openings through said dielectric layer on the ridges of said inverted pyramidal cavities.

24. The method of claim 19, wherein sub-nanosecond pulsed duration laser ablation is used to form selective backside base and emitter contact openings through said dielectric layer on the ridges of said inverted pyramidal cavities.