Specific Surface Topography (e.g., Textured Surface, Etc.) Patents (Class 438/71)
  • Patent number: 11319624
    Abstract: A vapor deposition method and a vapor deposition apparatus that, when a vapor deposition material is deposited on a substrate, make it possible to form deposition layer pattern precisely so that the deposition layer pattern is formed uniformly without a gap formed between a deposition mask and the substrate. A deposition mask is disposed with its periphery held by a frame. A substrate on which a vapor deposition layer is to be formed is mounted over an upper surface of the deposition mask. A vapor deposition source is disposed facing the deposition mask and evaporates a vapor deposition material. The vapor deposition is performed while the substrate is pressed vertically at a position of a center of deflection of the deposition mask and on an upper surface of the substrate until that a length of the substrate substantially becomes identical to a length of the deposition mask being bowed down and expanded.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: May 3, 2022
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Koshi Nishida, Kozo Yano, Katsuhiko Kishimoto, Susumu Sakio
  • Patent number: 11189498
    Abstract: There is provided a method of etching a silicon-containing film formed on a substrate, the method including: etching the silicon-containing film by using both a first fluorine-containing gas and a second fluorine-containing gas, the first fluorine-containing gas including at least an F2 gas and the second fluorine-containing gas including at least a ClF3 gas, an IF7 gas, an IF5 gas or an SF6 gas.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: November 30, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takehiko Orii, Yasuo Asada, Jun Lin, Ayano Hagiwara, Shinji Irie, Kenji Tanouchi, Kakeru Wada
  • Patent number: 11164981
    Abstract: A method includes depositing a first layer including amorphous silicon on a surface of a substrate; depositing a second layer including metal on the first layer; and performing an annealing process at a temperature within a range of 70° C. to 200° C., thereby inducing a silicidation reaction between the first layer and the second layer and forming a third layer comprising a metal silicide in electrical contact with the substrate, resulting in a remaining part of the first layer being between the substrate and the third layer.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: November 2, 2021
    Assignees: IMEC VZW, KATHOLIEKE UNIVERSITEIT, KU LEUVEN R&D
    Inventors: Jinyoun Cho, Maria Jesus Recaman Payo, Maarten Debucquoy, Jef Poortmans
  • Patent number: 11004991
    Abstract: Provided is a method of manufacturing a photovoltaic solar cell, including: forming a first conductivity type region that contains a first conductivity dopant, on one surface of a semiconductor substrate and an opposite surface that is opposite to the one surface; removing the first conductivity type region formed on the opposite surface of the semiconductor substrate by performing dry etching; and forming a second conductivity type region that contains a second conductivity type dopant, on the opposite surface of the semiconductor substrate.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: May 11, 2021
    Assignee: LG ELECTRONICS INC.
    Inventors: Younggu Do, Sungjin Kim, Hyungwook Choi
  • Patent number: 10892333
    Abstract: A method of making a GaN device includes: forming a GaN substrate; forming a plurality of spaced-apart first metal contacts directly on the GaN substrate; forming a layer of insulating GaN on the exposed portions of the upper surface; forming a stressor layer on the contacts and the layer of insulating GaN; forming a handle substrate on the first surface of the stressor layer; spalling the GaN substrate that is located beneath the stressor layer to separate a layer of GaN and removing the handle substrate; bonding the stressor layer to a thermally conductive substrate; forming a plurality of vertical channels through the GaN to define a plurality of device structures; removing the exposed portions of the layer of insulating GaN to electrically isolate the device structures; forming an ohmic contact layer on the second surface; and forming second metal contacts on the ohmic contact layer.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: January 12, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Devendra K. Sadana
  • Patent number: 10593602
    Abstract: Implementations of a method for healing a crack in a semiconductor substrate may include identifying a crack in a semiconductor substrate and heating an area of the semiconductor substrate including the crack until the crack is healed.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: March 17, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • Patent number: 10424644
    Abstract: A method of making a GaN device includes: forming a GaN substrate; forming a plurality of spaced-apart first metal contacts directly on the GaN substrate; forming a layer of insulating GaN on the exposed portions of the upper surface; forming a stressor layer on the contacts and the layer of insulating GaN; forming a handle substrate on the first surface of the stressor layer; spalling the GaN substrate that is located beneath the stressor layer to separate a layer of GaN and removing the handle substrate; bonding the stressor layer to a thermally conductive substrate; forming a plurality of vertical channels through the GaN to define a plurality of device structures; removing the exposed portions of the layer of insulating GaN to electrically isolate the device structures; forming an ohmic contact layer on the second surface; and forming second metal contacts on the ohmic contact layer.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: September 24, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Devendra K. Sadana
  • Patent number: 10411145
    Abstract: A method for producing a textured structure of a crystalline silicon solar cell is provided, including the following steps: (1) forming a porous layer structure on a surface of a silicon wafer; (2) then cleaning with a first alkaline chemical solution; (3) removing residual metal particles with a cleaning solution; (4) and then etching the surface with a first chemical etching solution to obtain the textured structure of the crystalline silicon solar cell. The method greatly prolongs the lifetime of the mixed solution of hydrofluoric acid and nitric acid and ensures the stability and uniformity of the textured structure.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: September 10, 2019
    Assignee: CSI CELLS CO., LTD.
    Inventors: Shuai Zou, Xusheng Wang, Guoqiang Xing
  • Patent number: 10388821
    Abstract: A method for manufacturing a crystalline silicon-based solar cell includes forming a first intrinsic silicon-based thin-film on a first principal surface and a lateral surface of an n-type crystalline silicon substrate, forming a p-type silicon-based thin-film on the first intrinsic silicon-based thin-film, forming a first transparent electrode layer on an entire region of the first principal surface except for a peripheral portion, forming a second intrinsic silicon-based thin-film on a second principal surface and the lateral surface of the n-type crystalline silicon substrate, forming an n-type silicon-based thin-film on the second intrinsic silicon-based thin-film, forming a second transparent electrode layer on an entire region of the second principal surface and the lateral surface of the n-type crystalline silicon substrate, forming a patterned collecting electrode on the first transparent electrode layer, and forming a plated metal electrode on the second transparent electrode layer by an electroplati
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: August 20, 2019
    Assignee: KANEKA CORPORATION
    Inventors: Daisuke Adachi, Toru Terashita, Toshihiko Uto
  • Patent number: 9887313
    Abstract: The present invention relates to a liquid-phase method for doping a semiconductor substrate, characterized in that a first composition containing at least one first dopant is applied to one or more regions of the surface of the semiconductor substrate, in order to create one or more region(s) of the surface of the semiconductor substrate coated with the first composition; a second composition containing at least one second dopant is applied to one or more regions of the surface of the semiconductor substrate, in order to create one or more region(s) of the surface of the semiconductor substrate coated with the second composition, where the one or more region(s) coated with the first composition and the one or more region(s) coated with the second composition are different and do not overlap significantly and where the first dopant is an n-type dopant and the second dopant is a p-type dopant or vice versa; the regions of the surface of the semiconductor substrate coated with the first composition and with the
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: February 6, 2018
    Assignee: Evonik Degussa GmbH
    Inventors: Christoph Mader, Christian Guenther, Joachim Erz, Susanne Christine Martens, Jasmin Lehmkuhl, Stephan Traut, Odo Wunnicke
  • Patent number: 9865670
    Abstract: A flexible display device includes: a flexible substrate including a bending area; an insulating layer formed on the flexible substrate and including at least one cutout formed to correspond to the bending area; and a plurality of wires formed along a surface shape of the insulating layer in the bending area. The at least one cutout may include an inclined lateral wall, and a width of the inclined lateral wall may be equal to or greater than a depth of the cutout.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: January 9, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hye Kyung Park, Young Su Kim
  • Patent number: 9570576
    Abstract: A method for forming a semiconductor device includes forming an electrical structure at a main surface of a semiconductor substrate and carrying out an anodic oxidation of a back side surface region of a back side surface of the semiconductor substrate to form an oxide layer at the back side surface of the semiconductor substrate.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: February 14, 2017
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Anton Mauder, Markus Zundel, Hans-Joachim Schulze, Franz Hirler, Hans Weber
  • Patent number: 9570315
    Abstract: A method of an interfacial oxide layer formation comprises a plurality of steps. The step (S1) is to remove a native oxide layer from a surface of a substrate; the step (S2) is to form an oxide layer on a surface of a substrate by piranha solution (SPM); the step (S3) is to cleaning a surface of the oxide layer by standard clean 1 (SC1), and the step (S4) is to etch he oxide layer by a solution comprising diluted hydrogen fluoride (dHF) and ozonized pure water (DIO3).
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: February 14, 2017
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Chueh-Yang Liu, Yi-Liang Ye, Ted Ming-Lang Guo, Yu-Ren Wang
  • Patent number: 9502601
    Abstract: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell can include a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed over an exposed outer portion of the first polycrystalline silicon emitter region and is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: November 22, 2016
    Assignee: SunPower Corporation
    Inventors: David D. Smith, Timothy Weidman, Scott Harrington, Venkatasubramani Balu
  • Patent number: 9397245
    Abstract: A photoelectric conversion device having a new anti-reflection structure is provided. A photoelectric conversion device includes a first-conductivity-type crystalline semiconductor region that is provided over a conductive layer; a crystalline semiconductor region that is provided over the first-conductivity-type crystalline semiconductor region and has an uneven surface by including a plurality of whiskers including a crystalline semiconductor; and a second-conductivity-type crystalline semiconductor region that covers the uneven surface of the crystalline semiconductor region having the uneven surface, the second conductivity type being opposite to the first conductivity type. In the photoelectric conversion device, a concentration gradient of an impurity element imparting the first conductivity type is formed from the first-conductivity-type crystalline semiconductor region toward the crystalline semiconductor region having the uneven surface.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: July 19, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9373734
    Abstract: A high-efficiency solar cell including an Indium, Gallium, Aluminum and Nitrogen (in a combination comprising InGaN, or InAlN, or InGaAlN) alloy which may be blended with a polyhedral oligomeric silsesquioxane (POSS) material, and which may include an absorption-enhancing layer including one of more of carbon nanotubes, quantum dots, and undulating or uneven surface topography.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: June 21, 2016
    Assignee: Lockheed Martin Corporation
    Inventors: Gregory T. Daly, Michael P. Whelan, Robert C. Bowen, Jr.
  • Patent number: 9349885
    Abstract: A multilayer transparent electroconductive film is obtained by stacking a transparent electroconductive film (II) on a transparent electroconductive film (I), and in this structure, the transparent electroconductive film (I) contains one or more added elements selected from aluminum and gallium, and the content of the added elements is in a range represented by ?2.18×[Al]+1.74?[Ga]??1.92×[Al]+6.10. The transparent electroconductive film (II) contains one or more added elements selected from aluminum and gallium, and the content of the added elements is in a range represented by ?[Al]+0.30?[Ga]??2.68×[Al]+1.74. In this case, [Al] is the aluminum content expressed as the atomic ratio (%) Al/(Zn+Al) and [Ga] is the gallium content expressed as the atomic ratio (%) Ga/(Zn+Ga).
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: May 24, 2016
    Assignee: SUMITOMO METAL MINING CO., LTD.
    Inventors: Yoshiyuki Abe, Kentaro Sogabe, Yasunori Yamanobe
  • Patent number: 9312405
    Abstract: A method of fabricating a solar cell includes forming a doped portion having a first conductive type on a semiconductor substrate, growing an oxide layer on the semiconductor substrate, forming a plurality of recess portions in the oxide layer, further growing the oxide layer on the semiconductor substrate, forming a doped portion having a second conductive type on areas of the semiconductor substrate corresponding to the recess portions, forming a first conductive electrode electrically coupled to the doped portion having the first conductive type, and forming a second conductive electrode on the semiconductor substrate and electrically coupled to the doped portion having the second conductive type, wherein a gap between the doped portions having the first and second conductive types corresponds to a width of the oxide layer formed by further growing the oxide layer.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: April 12, 2016
    Assignee: Intellectual Keystone Technology LLC
    Inventors: Sung-Chul Lee, Doo-Youl Lee, Young-Jin Kim, Young-Su Kim, Young-Soo Kim, Dong-Hun Lee
  • Patent number: 9257579
    Abstract: Provided is a method of fabricating an electronic device. The method according to the present inventive concept may include forming a lower electrode having a flat portion and protrusions on a substrate, forming an intermediate layer on the lower electrode, and forming an upper electrode on the intermediate layer. The forming of the lower electrode may include forming a conductive film by depositing a first metal on the substrate, and depositing a second metal on the conductive film to prepare an alloy of the first metal and the second metal.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: February 9, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sun Jin Yun, Chang Bong Yeon, Yoo Jeong Lee, JungWook Lim
  • Publication number: 20150140721
    Abstract: Various laser processing schemes are disclosed for producing various types of hetero junction and homo-junction solar cells. The methods include base and emitter contact opening, selective doping, metal ablation, annealing to improve passivation, and selective emitter doping via laser heating of aluminum. Also, laser processing schemes are disclosed that are suitable for selective amorphous silicon ablation and selective doping for hetero junction solar cells. Laser ablation techniques are disclosed that leave the underlying silicon substantially undamaged. These laser processing techniques may be applied to semiconductor substrates, including crystalline silicon substrates, and further including crystalline silicon substrates which are manufactured either through wire saw wafering methods or via epitaxial deposition processes, or other cleavage techniques such as ion implantation and heating, that are either planar or textured/three-dimensional.
    Type: Application
    Filed: December 20, 2013
    Publication date: May 21, 2015
    Applicant: SOLEXEL, INC.
    Inventors: Mehrdad M. Moslehi, Virendra V. Rana, Pranav Anbalagan, Vivek Saraswat
  • Patent number: 9034684
    Abstract: Etched substrates, and particularly, light-absorbing etched substrates, and methods for making such substrates are described.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: May 19, 2015
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Jun-Ying Zhang, Terry L. Smith, Bing Hao
  • Publication number: 20150129023
    Abstract: The present invention provides a optoelectronic device having a surface periodic grating structure and a manufacturing method thereof, which includes: a substrate; a multi-layer semiconductor structure layer formed on the substrate; and a periodic grating structure layer embedded in the multi-layer semiconductor structure layer by etching based on optimized parameters. A direction of an incident light to the optoelectronic device is changed to be resonant to the multi-layer semiconductor structure layer to enhance optoelectricity of the optoelectronic device. The method includes: (1) providing a substrate; (2) forming a multi-layer semiconductor structure layer on the substrate; (3) selecting parameters to perform a design for a periodic grating structure layer on a surface of the multi-layer semiconductor structure layer; and (4) forming the periodic grating structure layer embedded in the multi-layer semiconductor structure layer by etching.
    Type: Application
    Filed: November 10, 2014
    Publication date: May 14, 2015
    Inventors: Chieh-Hsiung Kuan, Ming-Lun Lee
  • Publication number: 20150129752
    Abstract: A silicon photonic photodetector structure, a method for fabricating the silicon photonic photodetector structure and a method for operating a silicon photonic photodetector device that results from the photonic photodetector structure each use a strip waveguide optically coupled with a polysilicon material photodetector layer that may be contiguous with a semiconductor material slab to which is located and formed a pair of electrical contacts separated by the polysilicon material photodetector layer. Alternatively, the pair of electrical contacts may be located and formed upon separated locations of the polysilicon photodetector layer.
    Type: Application
    Filed: October 13, 2014
    Publication date: May 14, 2015
    Applicant: CORNELL UNIVERSITY
    Inventors: Michal Lipson, Kyle Preston
  • Patent number: 9029185
    Abstract: A method for manufacturing a solar cell according to an embodiment of the present invention includes preparing a semiconductor substrate having a first conductivity type dopant; ion-implanting a pre-amorphization elements into a front surface of the semiconductor substrate to form an amorphous layer; and forming an emitter layer by ion-implanting second conductivity type dopant into the front surface of the semiconductor substrate. The method then further includes heat-treating the layers to activate the second conductivity type dopant. The method further includes forming a back surface field layer at a back surface of the semiconductor substrate by ion-implanting a first conductivity type dopant.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: May 12, 2015
    Assignee: LG Electronics Inc.
    Inventors: Kyoungsoo Lee, Seongeun Lee
  • Publication number: 20150122329
    Abstract: A photovoltaic device including a single junction solar cell provided by an absorption layer of a type IV semiconductor material having a first conductivity, and an emitter layer of a type III-V semiconductor material having a second conductivity, wherein the type III-V semiconductor material is non-crystalline and has a thickness that is no greater than 50 nm.
    Type: Application
    Filed: May 1, 2014
    Publication date: May 7, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Can Bayram, Bahman Hekmatshoar-Tabari
  • Publication number: 20150123227
    Abstract: There is provided an image pickup element including a non-planar layer having a non-planar light incident surface in a light receiving region, and a microlens of an inorganic material which is provided on a side of the light incident surface of the non-planar layer, and collects incident light.
    Type: Application
    Filed: May 22, 2013
    Publication date: May 7, 2015
    Inventors: Yoichi Ootsuka, Atsushi Yamamoto, Kensaku Maeda
  • Publication number: 20150125988
    Abstract: A scribing apparatus for manufacturing a solar cell, and a method of manufacturing a solar cell using the same are provided. The scribing apparatus includes a stage part configured to support a substrate having at least one thin film layer, a scribing unit configured to scribe on the at least one thin film layer, and a moving unit configured to move at least one of the stage part and the scribing unit during the scribing process. A method of manufacturing a solar cell using the scribing apparatus includes scribing a first pattern onto a reflective electrode layer using the scribing apparatus, the reflective electrode layer being on the substrate, the scribing apparatus further including a needle installation part having a first needle configured to scribe on one side of the reflective electrode layer, and a second needle configured to scribe on a side surface of the reflective electrode layer.
    Type: Application
    Filed: October 9, 2014
    Publication date: May 7, 2015
    Inventors: Dong-Ho Lee, Jung-Gyu Nam, Kwang-Soo Huh, Su-Jin Kim
  • Publication number: 20150118785
    Abstract: A method for consistently texturizing silicon wafers dating solar cell wet chemical processing. In one aspect, the invention includes submerging a batch of silicon wafers within a process chamber having an alkaline solution mixture therein. The invention utilizes a feed and bleed technique to bleed chemicals from the process chamber and introduce fresh chemicals into the process chamber to maintain chemical concentrations within a desired range and to maintain etch by-products below a threshold. The alkaline solution etches the silicon wafers to texturize the surfaces of the silicon wafers to form a pattern of pyramids (i.e., texturization pattern) on the surface of the silicon wafers. The feed and bleed technique enables the texturization pattern on the surfaces of the processed wafers and the reflectance of the processed wafers to be consistent among different batches of silicon wafers that are submerged into the alkaline mixture in the process chamber.
    Type: Application
    Filed: May 6, 2013
    Publication date: April 30, 2015
    Inventors: Ismail Kashkoush, Jennifer Rieker, Gim-Syang Chen, Dennis Nemeth
  • Publication number: 20150118786
    Abstract: A method of producing a solar cell, including: a first coating step in which a pre-wet composition is spin-coated on a surface of a semiconductor substrate; a second coating step in which a diffusing material including a solvent and a diffusing agent containing a first impurity element is spin-coated on the surface where the pre-wet composition has been spin-coated, so as to form a coating film of the diffusing agent; and a first impurity diffusion layer forming step in which the semiconductor substrate having the coating film formed thereon is heated, so as to form a first impurity diffusion layer in which the impurity element contained in the diffusing agent is diffused.
    Type: Application
    Filed: October 23, 2014
    Publication date: April 30, 2015
    Inventors: Seiji Ohishi, Katsuya Tanitsu, Shinji Goda, Takayuki Ogino, Futoshi Kato, Ayumu Imai, Yasuyuki Kano
  • Publication number: 20150104897
    Abstract: A device for wet-chemical treatment of substrates includes: an accommodation device for a substrate and a process medium, the substrate having a treatment side in operative connection with the process medium; a fluid guidance element, having a specified surface texture, housed in the accommodation device, the specified surface texture being configured to provide a guidance of the process medium along the specified surface texture, the specified surface texture being positioned lying opposite and at a predetermined fixed recess at a distance from the treatment side of the substrate; and the process medium being moved in the intervening space between the specified surface texture of the fluid guidance element and the treatment side of the substrate.
    Type: Application
    Filed: October 14, 2014
    Publication date: April 16, 2015
    Applicant: ROBERT BOSCH GMBH
    Inventors: Juergen Hackenberg, Michael Lingner, Harald Bauer
  • Publication number: 20150090328
    Abstract: A thin epitaxial silicon solar cell includes one or more layers of doped oxides on the backside. A silicon nitride layer that serves as a moisture barrier is formed on the one or more layers of doped oxides. The doped oxides provide dopants for forming doped regions in an epitaxial silicon layer. Metal contacts are electrically coupled to the doped regions through the silicon nitride layer and the one or more layers of doped oxides.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Applicant: SUNPOWER CORPORATION
    Inventor: David D. SMITH
  • Patent number: 8994135
    Abstract: A photodiode array PDA1 is provided with a substrate S wherein a plurality of photodetecting channels CH have an n-type semiconductor layer 32. The photodiode array PDA1 is provided with a p? type semiconductor layer 33 formed on the n-type semiconductor layer 32, resistors 24 provided for the respective photodetecting channels CH and each having one end portion connected to a signal conducting wire 23, and an n-type separating portion 40 formed between the plurality of photodetecting channels CH. The p? type semiconductor layer 33 forms pn junctions at an interface to the n-type semiconductor layer 32 and has a plurality of multiplication regions AM for avalanche multiplication of carriers generated with incidence of detection target light, corresponding to the respective photodetecting channels. An irregular asperity 10 is formed in a surface of the n-type semiconductor layer 32 and the surface is optically exposed.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: March 31, 2015
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Kazuhisa Yamamura, Akira Sakamoto, Terumasa Nagano, Yoshitaka Ishikawa, Satoshi Kawai
  • Patent number: 8993423
    Abstract: A method of manufacturing a solar cell is disclosed. The method includes forming a dielectric film on a semiconductor substrate doped with a first conductive type impurity, exposing a high concentration doping region of a predetermined selective emitter by partially removing the dielectric film, and ion-implanting a second conductive type impurity into a front surface of the semiconductor substrate with the dielectric film formed thereon to form a high concentration doping layer in the semiconductor substrate to correspond to the high concentration doping region and to form a low concentration doping layer in the semiconductor substrate to correspond to a region in which the dielectric film is formed.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: March 31, 2015
    Assignee: Shinshung Solar Energy Co., Ltd.
    Inventors: Ji Soo Kim, Ho Sik Kim, Ji Sun Kim, Jong Youb Lim, Yeon Hee Hwang, Hoon Joo Choi, Jeong Jae Jo
  • Publication number: 20150087105
    Abstract: Methods and apparatuses are provided for casting silicon for photovoltaic cells and other applications. With such methods and apparatuses, a cast body of geometrically ordered multi-crystalline silicon may be formed that is free or substantially free of radially-distributed impurities and defects and having at least two dimensions that are each at least about 10 cm is provided.
    Type: Application
    Filed: December 5, 2014
    Publication date: March 26, 2015
    Inventor: Nathan G. Stoddard
  • Patent number: 8987113
    Abstract: A device includes an image sensing element. The device also includes a Silicon Dioxide (SiO2) layer, located over the image sensing element, exhibiting a first index of refraction. The device further includes a first lens, located over the SiO2 layer, exhibiting a second index of refraction greater than the first index of refraction. The device still further includes a color filter located over the first lens and a second lens located over the color filter.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Hsuan Hsu, Dun-Nian Yaung, Yean-Kuen Fang
  • Patent number: 8987038
    Abstract: A method for forming a solar cell with selective emitters is disclosed, including selectively removing a portion of a barrier layer on a substrate to form an opening, performing a texture etching process to the substrate to form a second texture structure in a second region under the opening of the barrier layer, wherein the substrate surface in the first region does not change from the first texture structure. The first texture structure and the second texture structure include a plurality of protruding portions and recessing portions. The distance between neighboring protruding portions of the first texture structure is L1, the distance between neighboring protruding portions of the second texture structure is L2, and L1 is 2˜20 times that of L2. The method for forming a solar cell with selective emitters further comprises removing the barrier layer and performing a doping process.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: March 24, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Dimitre Zahariev Dimitrov, Ching-Hsi Lin, Chung-Wen Lan, Der-Chin Wu
  • Publication number: 20150068594
    Abstract: To provide a solar cell that reduces occurrence of a defect and has high photoelectric conversion efficiency. The solar cell includes a silicon substrate such as an n-type single-crystal silicon substrate single crystal with pyramid-shaped irregularities P formed thereon, and an amorphous or microcrystal semiconductor layer formed on the single-crystal silicon substrate. A flat part F is formed in a valley portion of the pyramid-shaped irregularities P provided on a surface of the single-crystal silicon substrate. With this configuration, a steep angle of 70° to 85° of a concave portion formed by a substantially (111) surface can be widened to between 115° and 135°. Accordingly, a change of atomic step morphology attributable to a rounded shape can be eliminated, thereby enabling to reduce epitaxial growth and defects in the amorphous or microcrystal semiconductor layer.
    Type: Application
    Filed: October 15, 2012
    Publication date: March 12, 2015
    Applicant: Mitsubishi Electric Corporation
    Inventors: Aya Nishiyama, Hiroyuki Fuchigami, Hidetada Tokioka
  • Patent number: 8975717
    Abstract: A solar cell includes polysilicon P-type and N-type doped regions on a backside of a substrate, such as a silicon wafer. A trench structure separates the P-type doped region from the N-type doped region. Each of the P-type and N-type doped regions may be formed over a thin dielectric layer. The trench structure may include a textured surface for increased solar radiation collection. Among other advantages, the resulting structure increases efficiency by providing isolation between adjacent P-type and N-type doped regions, thereby preventing recombination in a space charge region where the doped regions would have touched.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: March 10, 2015
    Assignee: SunPower Corporation
    Inventor: David D. Smith
  • Patent number: 8969121
    Abstract: A method for manufacturing a solar cell according to an embodiment of the present invention includes preparing a semiconductor substrate having a first conductivity type dopant; ion-implanting a pre-amorphization elements into a front surface of the semiconductor substrate to form an amorphous layer; and forming an emitter layer by ion-implanting second conductivity type dopant into the front surface of the semiconductor substrate. The method then further includes heat-treating the layers to activate the second conductivity type dopant. The method further includes forming a back surface field layer at a back surface of the semiconductor substrate by ion-implanting a first conductivity type dopant.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: March 3, 2015
    Assignee: LG Electronics Inc.
    Inventors: Kyoungsoo Lee, Seongeun Lee
  • Patent number: 8969276
    Abstract: An aqueous acidic etching solution suitable for texturing the surface of single crystal and polycrystal silicon substrates and containing, based on the complete weight of the solution, 3 to 10% by weight of hydrofluoric acid; 10 to 35% by weight of nitric acid; 5 to 40% by weight of sulfuric acid; and 55 to 82% by weight of water; a method for texturing the surface of single crystal and polycrystal silicon substrates comprising the step of (1) contacting at least one major surface of a substrate with the said aqueous acidic etching solution; (2) etching the at least one major surface of the substrate for a time and at a temperature sufficient to obtain a surface texture consisting of recesses and protrusions; and (3) removing the at least one major surface of the substrate from the contact with the aqueous acidic etching solution; and a method for manufacturing photovoltaic cells and solar cells using the said solution and the said texturing method.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: March 3, 2015
    Assignee: BASF SE
    Inventors: Simon Braun, Julian Proelss, Ihor Melnyk, Michael Michel, Stefan Mathijssen
  • Patent number: 8969125
    Abstract: A method for manufacturing a solar cell includes texturing a front surface of a semiconductor substrate having a first conductive type dopant by using a dry etching method, forming an emitter layer by ion-implanting a second conductive type dopant into the front surface of the semiconductor substrate, forming a back passivation film on a back surface of the semiconductor substrate; and forming a first electrode electrically connected to the emitter layer and a second electrode being in partial contact with the back surface of the semiconductor substrate.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: March 3, 2015
    Assignee: LG Electronics Inc.
    Inventors: Kyoungsoo Lee, Myungjun Shin, Jiweon Jeong
  • Publication number: 20150056742
    Abstract: Annealing solutions providing damage-free laser patterning utilizing auxiliary heating to anneal laser damaged ablation regions are provided herein. Ablation spots on an underlying semiconductor substrate are annealed during or after pulsed laser ablation patterning of overlying transparent passivation layers.
    Type: Application
    Filed: April 29, 2014
    Publication date: February 26, 2015
    Applicant: Solexel, Inc.
    Inventors: Virendra V. Rana, Mehrdad M. Moslehi, Pawan Kapur, Benjamin Rattle, Heather Deshazer, Solene Coutant
  • Publication number: 20150056743
    Abstract: A manufacturing method of a solar cell includes a protection-film forming step of forming a protection film on one surface side of a semiconductor substrate, a first processing step of forming a plurality of first openings having a shape close to a desired opening shape and a size smaller than a target opening size in the protection film by a method having relatively high processing efficiency, a second processing step of forming second openings in the protection film by expanding the first openings up to the target opening size by a method having relatively high processing accuracy, and an etching step of forming an asperity structure having the a concave portion in an inverted pyramid shape on the one surface side of the semiconductor substrate by performing anisotropic wet etching on the semiconductor substrate in a region under the second openings via the second openings.
    Type: Application
    Filed: March 12, 2012
    Publication date: February 26, 2015
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Shoichi Karakida
  • Patent number: 8962373
    Abstract: A method for manufacturing high efficiency solar cells is disclosed. The method comprises providing a thin dielectric layer and a doped polysilicon layer on the back side of a silicon substrate. Subsequently, a high quality oxide layer and a wide band gap doped semiconductor layer can both be formed on the back and front sides of the silicon substrate. A metallization process to plate metal fingers onto the doped polysilicon layer through contact openings can then be performed. The plated metal fingers can form a first metal gridline. A second metal gridline can be formed by directly plating metal to an emitter region on the back side of the silicon substrate, eliminating the need for contact openings for the second metal gridline. Among the advantages, the method for manufacture provides decreased thermal processes, decreased etching steps, increased efficiency and a simplified procedure for the manufacture of high efficiency solar cells.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: February 24, 2015
    Assignee: SunPower Corporation
    Inventors: Peter J. Cousins, David D. Smith, Seung Bum Rim
  • Patent number: 8963156
    Abstract: Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon formed on a substrate. Such a semiconductor device may further include at least one opening having a high aspect ratio and extending into the stack structure to a level adjacent the substrate, a first poly-silicon channel formed in a lower portion of the opening adjacent the substrate, a second poly-silicon channel formed in an upper portion of the opening, and WSiX material disposed between the first poly-silicon channel and the second poly-silicon channel in the opening. The WSiX material is adjacent to the substrate, and can be used as an etch-landing layer and a conductive contact to contact both the first poly-silicon channel and the second poly-silicon channel in the opening. Other embodiments include methods of making semiconductor devices.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Hongbin Zhu, Gordon Haller, Paul D. Long
  • Patent number: 8951825
    Abstract: Multicrystalline silicon (mc-Si) solar cells having patterned light trapping structures (e.g., pyramid or trough features) are generated by printing a liquid mask material from an array of closely-spaced parallel elongated conduits such that portions of the mc-Si wafer are exposed through openings defined between the printed mask features. Closely spaced mask pattern features are achieved using an array of conduits (e.g., micro-springs or straight polyimide cantilevers), where each conduit includes a slit-type, tube-type or ridge/valley-type liquid guiding channel that extends between a fixed base end and a tip end of the conduit such that mask material supplied from a reservoir is precisely ejected from the tip onto the mc-Si wafer. The exposed planar surface portions are then etched to form the desired patterned light trapping structures (e.g., trough structures).
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: February 10, 2015
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Scott J. H. Limb, Dirk DeBruyker, Sean Garner
  • Publication number: 20150037923
    Abstract: Processes increase light absorption into silicon wafers by selectively changing the reflective properties of the bottom portions of light trapping cavity features. Modification of light trapping features includes: deepening the bottom portion, increasing the curvature of the bottom portion, and roughening the bottom portion, all accomplished through etching. Modification may also be by the selective addition of material at the bottom of cavity features. Different types of features in the same wafers may be treated differently. Some may receive a treatment that improves light trapping while another is deliberately excluded from such treatment. Some may be deepened, some roughened, some both. No alignment is needed to achieve this selectively. The masking step achieves self-alignment to previously created light trapping features due to softening and deformation in place.
    Type: Application
    Filed: January 6, 2013
    Publication date: February 5, 2015
    Applicant: 1366 TECHNOLOGIES, INC.
    Inventors: Vladimir S. Tarasov, Ali Ersen, ERIC Stern, Jason M. Criscione, Emanuel M. Sachs
  • Publication number: 20150035102
    Abstract: According to one embodiment, the method of manufacturing a solid-state imaging device includes: forming a plurality of photoelectric conversion elements by two-dimensionally arranging semiconductor areas of a second conductivity type at a semiconductor layer of a first conductivity type in a matrix pattern; forming the photoelectric conversion elements in a rectangular shape in plan view, the photoelectric conversion elements being formed by forming a grid-like trench in plan view so as to partition the semiconductor layer; forming the photoelectric conversion element formed into the rectangular shape in plan view into a convex polygonal shape in plan view whose number of corners is larger than the number of corners of a rectangular; and forming an element isolation area including a light shielding member at a trench coated with an insulating film after coating an inner peripheral surface of the trench with the insulating film.
    Type: Application
    Filed: February 7, 2014
    Publication date: February 5, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Hiroaki ASHIDATE
  • Patent number: 8946737
    Abstract: A light emitting diode (LED) includes a substrate, a buffer layer and an epitaxial structure. The substrate has a first surface with a patterning structure formed thereon. The patterning structure includes a plurality of projections. The buffer layer is arranged on the first surface of the substrate. The epitaxial structure is arranged on the buffer layer. The epitaxial structure includes a first semiconductor layer, an active layer and a second semiconductor layer arranged on the buffer layer in sequence. The first semiconductor layer has a second surface attached to the active layer. A distance between a peak of each the projections and the second surface of the first semiconductor layer is ranged from 0.5 ?m to 2.5 ?m.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: February 3, 2015
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Ya-Wen Lin, Po-Min Tu, Shih-Cheng Huang, Chia-Hung Huang, Shun-Kuei Yang
  • Patent number: 8945972
    Abstract: The invention relates to a layered system for producing a solar cell on a metal substrate and to a method of producing the layered system.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: February 3, 2015
    Assignee: Tata Steel Nederland Technology BV
    Inventors: Joost Willem Hendrik Van Krevel, Albertus Johannes Maria Wigchert, Ganesan Palaniswamy