Apparatus and Method for Multiple Gate Transistors
An apparatus comprises a substrate having a first crystal orientation and an active region, wherein an upper portion of the active region is of a second crystal orientation and the upper portion of the active region is wrapped by a gate structure around two sides. The apparatus further comprises a trench surrounded by isolation regions, wherein the upper portion of the active region is over top surfaces of the isolation regions.
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As technologies evolve, semiconductor process nodes have been scaled down for high density integrated circuits. As a result, the form factor of integrated circuit has been improved from shrinking the semiconductor process node (e.g., shrink the process node towards the sub-20 nm node). As semiconductor devices are scaled down, new techniques are needed to maintain the electronic components' performance from one generation to the next. For example, transistors formed by high carrier mobility materials such as III-V materials, germanium and/or the like are desirable for high density and high speed integrated circuits.
Germanium and silicon are group IV elements in the periodic table. In comparison with silicon, germanium is of higher carrier and hole mobility. The higher carrier and hole mobility of germanium may lead to better device electrical properties. For example, the lattice electron mobility of silicon is 1417 cm2/V-sec. In contrast, the lattice electron mobility of germanium is 3900 cm2/V-sec. The electron mobility of germanium is about 2.75 times more than that of silicon. Such higher electron mobility of germanium leads to higher drive current and smaller gate delay. It should be noted that some group III-V materials may be used to replace silicon because some of group III_V materials may have much higher mobility than germanium and silicon.
Another advantageous feature of germanium based transistors is that germanium is of a smaller band gap. More particularly, the band gap of germanium is about 0.6 eV compared to 1.2 eV for silicon. Such a smaller band gap helps to reduce the threshold voltage of germanium based transistors.
Germanium is of various advantages in comparison with silicon. However, silicon wafers are dominant in the semiconductor industry because the cost of germanium wafers is very high. One widely accepted solution of fabricating germanium based transistor is growing germanium active regions on silicon substrates through an epitaxial growth process.
Growing a germanium layer on a silicon substrate is commonly referred to as germanium-silicon hetero-epitaxial growth. The lattice constant of germanium is about 4.2% more than the lattice constant of silicon. When a germanium layer is grown on a silicon substrate, the germanium layer is compressively strained to fit the lattice spacing of the silicon substrate. After the germanium layer is grown more than a critical thickness, the strain may be relieved by forming a variety of threading dislocations. Such threading dislocations are defects, which may degrade electrical properties of germanium based transistors.
For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.
DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTSThe making and using of the presently embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosure, and do not limit the scope of the disclosure.
The present disclosure will be described with respect to embodiments in a specific context, namely a germanium based multiple gate transistor. The embodiments of the disclosure may also be applied, however, to a variety of transistors formed of group IV elements, group III-V compounds and group II-VI compounds. Hereinafter, various embodiments will be explained in detail with reference to the accompanying drawings.
It should be noted while
As shown in
In accordance with an embodiment, the substrate 202 may be a crystalline structure. The substrate 202 may be formed of silicon, although it may also be formed of other group III, group IV, and/or group V elements, such as silicon, germanium, gallium, arsenic, and combinations thereof. In accordance with an embodiment, the substrate 202 may be formed of a first semiconductor material having a first crystal orientation. According to an embodiment, the first semiconductor material is silicon and the first crystal orientation is a <001> crystal orientation.
The active region 206 is formed in a trench over the substrate 202. The structure of the active region 206 has been described in detail above with respect to
The multiple-gate transistor 200 may comprise isolation regions 204. As shown in
As shown in
As shown in
The gate electrode 208 may comprise a conductive material selected from a group comprising of polycrystalline-silicon (poly-Si), poly-crystalline silicon-germanium (poly-SiGe), metal materials, metal silicide materials, metal nitride materials, metal oxide materials and the like. For example, metal materials may include tantalum, titanium, molybdenum, tungsten, platinum, aluminum, hafnium, ruthenium, a combination thereof and the like. Metal silicide materials include titanium silicide, cobalt silicide, nickel silicide, tantalum silicide, a combination thereof and the like. Metal nitride materials include titanium nitride, tantalum nitride, tungsten nitride, a combination thereof and the like. Metal oxide materials include ruthenium oxide, indium tin oxide, a combination thereof and the like.
It should be noted that other fabrication processes may be used to form the gate electrode 208. Other fabrication processes include but is not limited to CVD, physical vapor deposition (PVD), plasma enhanced CVD (PECVD), atmospheric pressure CVD (APCVD), high density plasma CVD (HD CVD), low-pressure chemical vapor deposition (LPCVD), atomic layer CVD (ALCVD) and the like.
In accordance with another embodiment, the semiconductor region 502 may comprise silicon germanium, which may be expressed as Sii-xGex, wherein x is the atomic percentage of germanium in silicon germanium, and may be greater than 0 and equal to or less than 1. When x is equal to 1, the semiconductor region 502 may be formed of pure germanium. In accordance with another embodiment, the semiconductor region 502 may comprise a compound semiconductor material comprising group III and group V elements, or a compound material comprising group II and group VI elements.
The process conditions for forming semiconductor region 502 are controlled so that the upper portion of the semiconductor region 502 is of a <111> crystal orientation. This may be achieved, for example, by increasing the growth temperature and reducing the pressure of the SEG process. In accordance with an embodiment, the growth temperature is between about 500° C. and about 650° C. The pressure of the SEG process may be as low as possible to allow the formation of the upper portion having a <111> crystal orientation. The pressure of the SEG process may be lower than about 0.13 tons.
The lattice constant of germanium is greater than the lattice constant of silicon. There may be a 4.2% lattice mismatch between germanium and silicon. As a result, a plurality of threading dislocations may be generated during the SEG process. However, the threading dislocations may be trapped inside the trench. More particularly, the threading dislocations are trapped in a bottom region 504. When the semiconductor region 502 is grown increasingly higher, more and more threading dislocations are blocked by sidewalls of the trench. As a result, the upper portion (e.g., the triangular portion of the semiconductor region 502) is free of threading dislocations. In addition, the upper portion may be of a <111> crystal orientation.
Although embodiments of the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims.
Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Claims
1. An apparatus comprising:
- a substrate having a first crystal orientation;
- an active region formed over the substrate, wherein: an upper portion of the active region is of a second crystal orientation; and the upper portion of the active region is wrapped by a gate structure around two sides; and
- a trench formed in the substrate and surrounded by isolation regions, wherein: the upper portion of the active region is over top surfaces of the isolation regions.
2. The apparatus of claim 1, wherein:
- the substrate is of a <001> crystal orientation; and
- the upper portion of the active region is of a <111> crystal orientation.
3. The apparatus of claim 1, wherein:
- the substrate is formed of silicon; and
- the active region is formed of germanium.
4. The apparatus of claim 1, wherein the active region comprises:
- a first portion formed of a first semiconductor material;
- a second portion formed of a second semiconductor material, wherein the second portion is formed over the first portion; and
- a third portion formed of a third semiconductor material, wherein the third portion is formed over the second portion.
5. The apparatus of claim 4, wherein:
- the first semiconductor material, the second semiconductor material and the third semiconductor materials are selected from the group consisting of group IV, group III-V and group II-VI semiconductor materials.
6. The apparatus of claim 1, wherein the upper portion of the active region is triangular in shape from a cross sectional view.
7. The apparatus of claim 1, further comprising:
- a gate dielectric layer formed between the gate structure and the upper portion of the active region.
8. A device comprising:
- a substrate having a <001> crystal orientation, wherein the substrate is formed of a first semiconductor material;
- a plurality of isolation regions formed over the substrate, wherein two adjacent isolation regions form a trench in the substrate;
- a channel region formed over the substrate and connected between a first drain/source region and a second drain/source region, wherein: the channel region is formed of a second semiconductor material; the channel region is triangular in shape from a cross sectional view; and the channel region is of a <111> crystal orientation; and
- a gate electrode wrapping the channel region around two sides.
9. The device of claim 8, wherein:
- the channel region is over top surfaces of the isolation region.
10. The device of claim 8, wherein:
- a lattice constant of the second semiconductor material is of greater than a lattice constant of the first semiconductor material.
11. The device of claim 8, further comprising:
- a semiconductor region formed in the trench, wherein the semiconductor region is coupled between the substrate and the channel region.
12. The device of claim 11, wherein the semiconductor region comprises:
- a first layer formed of a third semiconductor material; and
- a second layer formed of a fourth semiconductor material, wherein the second layer is formed over the first semiconductor.
13. The device of claim 12, wherein:
- the third semiconductor material and the fourth semiconductor materials are selected from the group consisting of group IV, group III-V and group II-VI semiconductor materials.
14. A method comprising:
- providing a substrate having a first crystal orientation, wherein the substrate is formed of a first semiconductor material;
- etching away a portion of the substrate to form a trench between two adjacent isolation regions;
- growing a semiconductor region in the trench over the substrate through an epitaxial growth process, wherein an upper portion of the semiconductor region is triangular in shape from a cross section view and has a second crystal orientation; and
- forming a gate structure on at least two sides of the semiconductor region.
15. The method of claim 14, further comprising:
- over-growing the semiconductor region so that the upper portion of the semiconductor region is above top surfaces of the isolation regions.
16. The method of claim 14, further comprising:
- etching away upper portions of the isolation regions so that the upper portion of the semiconductor region is above top surfaces of the isolation regions.
17. The method of claim 14, further comprising:
- growing a first semiconductor layer of a second semiconductor material over the substrate;
- growing a second semiconductor layer of a third semiconductor material over the first semiconductor layer; and
- growing a third semiconductor layer of a fourth semiconductor material over the second semiconductor layer.
18. The method of claim 14, further comprising:
- depositing a gate dielectric layer over the semiconductor region.
19. The method of claim 14, wherein:
- a lattice constant of the semiconductor region is greater than a lattice constant of the substrate.
20. The method of claim 14, wherein:
- the first crystal orientation is <001>; and
- the second crystal orientation is <111>.
Type: Application
Filed: Aug 24, 2012
Publication Date: Feb 27, 2014
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Hsin-Chu)
Inventor: Georgios Vellianitis (Heverlee)
Application Number: 13/594,579
International Classification: H01L 29/78 (20060101); H01L 21/20 (20060101);