Abstract: Embodiments of a substrate carrier are provided herein. In some embodiments, a substrate carrier includes a base plate, wherein the base plate is a thin, solid plate with no through holes or embedded components; and a plurality of raised portions extending from the base plate, wherein the plurality of raised portions include first raised portions and second raised portions, the first raised portions disposed radially inward from the second raised portions, wherein the base plate and the plurality of raised portions define pockets configured to retain a plurality of substrates, and wherein an upper surface of the second raised portions have a greater surface area than an upper surface of the first raised portions.

Abstract: A semiconductor device includes: a substrate including a memory cell region and a connection region; a plurality of gate lines vertically overlapping each other in the memory cell region of the substrate in a vertical direction, each gate line including a first metal; a stepped connection unit in the connection region and comprising a plurality of conductive pad regions, each conductive pad region including the first metal and integrally connected to a respective gate line of the plurality of gate lines; a plurality of contact structures vertically overlapping the stepped connection unit, each contact structure connected to a respectively corresponding conductive pad region of the plurality of conductive pad regions and including a second metal; and at least one metal silicide layer between at least one contact structure and the respectively corresponding conductive pad region.

Abstract: A method of forming a semiconductor structure comprises forming an array of vertical thin film transistors. Forming the array of vertical thin film transistors comprises forming a source region, forming a channel material comprising an oxide semiconductor material over the source region, exposing the channel material to a dry etchant comprising hydrogen bromide to pattern the channel material into channel regions of adjacent vertical thin film transistor structures, forming a gate dielectric material on sidewalls of the channel regions, forming a gate electrode material adjacent to the gate dielectric material, and forming a drain region over the channel regions. Related methods of forming semiconductor structures and an array of memory cells are also disclosed.

Abstract: The present disclosure provides a semiconductor device, a manufacturing method, and electronic equipment. The semiconductor device including: a substrate; an interface, for generating two-dimensional charge carrier gas; a first electrode and a second electrode; and a first semiconductor layer of a first type doping formed on the substrate, wherein first regions and a second region are formed in the first semiconductor layer, wherein in the first regions, the dopant atoms of the first type do not have electrical activity, and in the second region, the dopant atoms of the first type have electrical activity; and the second region includes a portion coplanar with the first regions.

Abstract: A method of forming transistor devices is described that includes forming a first transistor plane on a substrate, the first transistor plane including at least one layer of epitaxial film adaptable for forming channels of field effect transistors, depositing a first insulator layer on the first transistor plane, depositing a first layer of polycrystalline silicon on the first insulator layer, annealing the first layer of polycrystalline silicon using laser heating. The laser heating increases grain size of the first layer of polycrystalline silicon. The method further includes forming a second transistor plane on the first layer of polycrystalline silicon, the second transistor plane being adaptable for forming channels of field effect transistors, depositing a second insulator layer on the second transistor plane, depositing a second layer of polycrystalline silicon on the second insulator layer, and annealing the second layer of polycrystalline silicon using laser heating.

Abstract: An integrated circuit die includes a FinFET transistor. The FinFET transistor includes an anti-punch through region below a channel region. Undesirable dopants are removed from the anti-punch through region during formation of the source and drain regions. When source and drain recesses are formed, a layer of dielectric material is deposited in the recesses. An annealing process is then performed. Undesirable dopants diffuse from the anti-punch through region into the layer of dielectric material during the annealing process. The layer of dielectric material is then removed. The source and drain regions are then formed by depositing semiconductor material in the recesses.

Abstract: A memory device is provided. The memory device may comprise: a first electrode; a resistance change layer placed on the first electrode and containing an alkali metal and a transition metal; and a second electrode placed on the resistance change layer, wherein the content of the alkali metal in the resistance change layer ranges from 40 at % (exclusive) to 88 at % (exclusive).

Abstract: An alternating stack of first material layers and second material layers is formed over a substrate. A hard mask layer is formed over the alternating stack. Optionally, an additional hard mask layer can be formed over the hard mask layer. A photoresist layer is applied and patterned, and cavities are formed in the hard mask layer by performing a first anisotropic etch process that transfers a pattern of the openings in the photoresist layer through the hard mask layer. Via openings are formed through an upper portion of the alternating stack by performing a second anisotropic etch process. A cladding liner can be optionally formed on sidewalls of the cavities in the hard mask layer. The via openings can be vertically extend through all layers within the alternating stack by performing a third anisotropic etch process.

Abstract: A semiconductor memory device includes a third insulating pattern and a first insulating pattern on a substrate, the third insulating pattern and the first insulating pattern being spaced apart from each other in a first direction that is perpendicular to the substrate such that a bottom surface of the third insulating pattern and a top surface of the first insulating pattern face each other, a gate electrode between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and including a first side extending between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and a second insulating pattern that protrudes from the first side of the gate electrode by a second width in a second direction, the second direction being different from the first direction.

Abstract: Embodiments includes methods for forming a silicon nitride film on a substrate in a deposition chamber. In embodiments, the substrate is sequentially exposed to a sequence of processing gases, comprising: a silicon halide precursor that absorbs onto a surface of the substrate to form an absorbed layer of the silicon halide, a first reacting gas that includes N2 and one or both of Ar and He, and a second reacting gas comprising a hydrogen-containing gas and one or more of Ar, He, and N2. In embodiments, the hydrogen-containing gas includes at least one of H2 (molecular hydrogen), NH3 (ammonia), N2H2 (diazene), N2H4 (hydrazine), and HN3 (hydrogen azide). Embodiments may include repeating the sequence until a desired thickness of the silicon nitride film is obtained.

Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.

Abstract: A method used in forming a memory array, comprises forming a substrate comprising a conductive tier, an insulator etch-stop tier above the conductive tier, a select gate tier above the insulator etch-stop tier, and a stack comprising vertically-alternating insulative tiers and wordline tiers above the select gate tier. Etching is conducted through the insulative tiers, the wordline tiers, and the select gate tier to and stopping on the insulator etch-stop tier to form channel openings that have individual bottoms comprising the insulator etch-stop tier. The insulator etch-stop tier is penetrated through to extend individual of the channel openings there-through to the conductive tier. Channel material is formed in the individual channel openings elevationally along the insulative tiers, the wordline tiers, and the select gate tier and is directly electrically coupled with the conductive material in the conductive tier. Structure independent of method is disclosed.

Abstract: A described example includes: a semiconductor die including a Hall sensor arranged in a first plane that is parallel to a device side surface of the semiconductor die; a passivated magnetic concentrator including a magnetic alloy layer formed over the device side surface of the semiconductor die, the upper surface of the magnetic alloy layer covered by a layer of polymer material; a backside surface of the semiconductor die opposite the device side surface mounted to a die side surface of a die pad on a package substrate, the semiconductor die having bond pads on the device side surface spaced from the magnetic concentrator; electrical connections coupling the bond pads of the semiconductor die to leads of the package substrate; and mold compound covering the magnetic concentrator, the semiconductor die, the electrical connections, a portion of the leads, and the die side surface of the die pad.

Abstract: A method for etching a surface including obtaining a structure comprising a plurality of nanowires on or above a substrate and a dielectric layer on or above the nanowires, wherein the dielectric layer comprises protrusions formed by the underlying nanowires; reacting a surface of the dielectric layer with a reactant, comprising a gas or a plasma, to form a reactive layer on the dielectric layer, wherein the reactive layer comprises a chemical compound including the reactant and elements of the dielectric layer and the reactive layer comprises sidewalls defined by the protrusions; and selectively etching the reactive layer, wherein the etching etches the protrusions laterally through the sidewalls so as to planarize the surface and remove or shrink the protrusions.

Abstract: Methods, systems, and devices for transistor configurations for multi-deck memory devices are described. A memory device may include a first set of transistors formed in part by doping portions of a first semiconductor substrate of the memory device. The memory device may include a set of memory cells arranged in a stack of decks of memory cells above the first semiconductor substrate and a second semiconductor substrate bonded above the stack of decks. The memory device may include a second set of transistors formed in part by doping portions of the second semiconductor substrate. The stack of decks may include a lower set of one or more decks that is coupled with the first set of transistors and an upper set of one or more decks that is coupled with the second set of transistors.

Abstract: A thin-film-deposition machine includes a chamber, a carrier, an extraction ring and a dispensing unit. The chamber includes a containing space and an extraction channel disposed around the containing space. The extraction channel is partitioned into a first, a second and a third channel areas. The carrier is disposed within the containing space. The first channel area is connected to the third channel area via the second channel area. The third channel area is formed with a height greater than that of the first channel area. The extraction ring includes a plurality of extraction holes and a ring channel. The extraction holes are disposed around the carrier for extracting gas from the containing space to the extraction channel, sequentially via the extraction holes, the ring channel. Thereby an even and steady flow field can be formed above the carrier and the thickness uniformity of film deposition can be improved.

Abstract: A semiconductor device includes: a gate structure including conductive layers and insulating layers, which are alternately stacked; a channel layer penetrating the gate structure; memory patterns respectively located between the channel layer and the conductive layers; a blocking layer including first parts located between the memory patterns and the conductive layers, and second parts extending between the memory patterns and protruding toward the insulating layers to the inside of the gate structure; and air gaps including a first region located in the second parts and a second region located between the memory patterns.

Abstract: A semiconductor device may include semiconductor patterns, a gate structure, a first spacer, a first semiconductor layer and a second semiconductor layer. The semiconductor patterns may be formed on a substrate, and may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and may overlap in the vertical direction. The gate structure may be formed on the substrate and the semiconductor patterns. At least portion of the gate structure may be formed vertically between the semiconductor patterns. The first spacer may cover opposite sidewalls of the gate structure, the sidewalls opposite to each other in a first direction. The first semiconductor layer may cover the sidewalls of the semiconductor patterns in the first direction, and surfaces of the first spacer and the substrate. The first semiconductor layer may have a first concentration of impurities.

Abstract: A manufacturing method of a semiconductor structure includes covering first and second semiconductor dies with an insulating encapsulant. The first semiconductor die includes an active surface accessibly exposed by the insulating encapsulant and a first conductive terminal distributed at the active surface. The second semiconductor die includes an active surface accessibly exposed by the insulating encapsulant and a second conductive terminal distributed at the active surface. A redistribution circuit layer is formed on the insulating encapsulant and the active surfaces of the first and second semiconductor dies. A conductive trace of the redistribution circuit layer is electrically connected from the first semiconductor die and meanderingly extends to the second semiconductor die, and a ratio of a total length of the conductive trace to a top width of the insulating encapsulant between the first and second semiconductor dies ranges from about 3 to about 10.

Abstract: In an embodiment, a first recess and a second recess, designed to reach a first semiconductor layer, are formed in the portions of a first threading dislocation and a second threading dislocation having reached the surface. Further, the first semiconductor layer is oxidized through the first recess and the second recess to form an insulating film configured to cover the lower surface of a second semiconductor layer.

Abstract: In some embodiments, the present disclosure relates to a method for forming a memory device, including forming a plurality of word line stacks respectively including a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate, forming a data storage layer along opposing sidewalls of the word line stacks, forming a channel layer along opposing sidewalls of the data storage layer, forming an inner insulating layer between inner sidewalls of the channel layer and including a first dielectric material, performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening, forming an isolation structure filling the isolation opening and including a second dielectric material, performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings, and forming source/drain contacts in the source/drain

Abstract: Multiple wide bandgap semiconductor wafers, each having active circuitry and an epitaxially formed backside drain contact layer, may be constructed from a single bulk semiconductor substrate by: forming foundational layers on the top of the bulk substrate via epitaxy; forming active circuitry atop the foundational layers; laser treating the backside of the bulk substrate to create a cleave line in one of the foundational layers; and exfoliating a semiconductor wafer from the bulk substrate, where the exfoliated semiconductor wafer contains the active circuits and at least a portion of the foundational layers. Wafers containing the foundational layers without complete active devices may be produced in a similar manner. The foundational layers may comprise a drain contact layer and a drift layer, and may additionally include a buffer layer between the drain contact layer and the drift layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a source/drain structure adjacent to the gate stack. The semiconductor device structure also includes a cap element over the source/drain structure. The cap element has a first top plane, and the source/drain structure has a second top plane. The first top plane of the cap element is wider than the second top plane of the source/drain structure. A surface orientation of the first top plane of the cap element and a surface orientation of a side surface of the cap element are different from each other. The surface orientation of the first top plane of the cap element is {311}.

Abstract: A three dimension memory device including a plurality of word lines, a plurality of first switches, a plurality of second switches and N conductive wire layers is provided, where N is a positive integer larger than 1. The word lines are divided into a plurality of word line groups. The first switches receive a common word line voltage. The second switches receive a reference ground voltage. A first word line group is connected to a first conductive wire layer through a second conductive wire layer. An ith word line group is connected to the first conductive wire layer through an (i+1)th to the second conductive wire layer in sequence.

Abstract: A memory apparatus includes an interconnect in a first dielectric above a substrate and a structure above the interconnect, where the structure includes a diffusion barrier material and covers the interconnect. The memory apparatus further includes a resistive random-access memory (RRAM) device coupled to the interconnect. The RRAM device includes a first electrode on a portion of the structure, a stoichiometric layer having a metal and oxygen on the first electrode, a non-stoichiometric layer including the metal and oxygen on the stoichiometric layer. A second electrode including a barrier material is on the non-stoichiometric layer. In some embodiments, the RRAM device further includes a third electrode on the second electrode. To prevent uncontrolled oxidation during a fabrication process a spacer may be directly adjacent to the RRAM device, where the spacer includes a second dielectric.

Abstract: A photodetector comprising an optical waveguide structure comprising at least three stripes spaced from one another such that a slot is present between each two adjacent stripes of the at least three stripes. A graphene absorption layer is provided over or underneath the at least three stripes. There is an electrode for each stripe, over or underneath the graphene absorption layer. The photodetector is configured such that two adjacent electrodes are biased using opposite polarities to create a p-n junction effect in a portion of the graphene absorption layer. In particular the portion of the graphene absorption layer is located over or underneath each respective slot between said each two adjacent stripes.

Abstract: A three-dimensional semiconductor device includes a first channel pattern on and spaced apart from a substrate, the first channel pattern having a first end and a second end that are spaced apart from each other in a first direction parallel to a top surface of the substrate, and a first sidewall and a second sidewall connecting between the first end and the second end, the first and second sidewalls being spaced apart from each other in a second direction parallel to the top surface of the substrate, the second direction intersecting the first direction, a bit line in contact with the first end of the first channel pattern, the bit line extending in a third direction perpendicular to the top surface of the substrate, and a first gate electrode adjacent to the first sidewall of the first channel pattern.

Abstract: A programmable charge-storage transistor comprises channel material, insulative charge-passage material, charge-storage material, a control gate, and charge-blocking material between the charge-storage material and the control gate. The charge-blocking material comprises a non-ferroelectric insulator material and a ferroelectric insulator material. Arrays of elevationally-extending strings of memory cells of memory cells are disclosed, including methods of forming such. Other embodiments, including method, are disclosed.

Abstract: In a step of calculating formation conditions for the second silicon carbide layer, a formation time of the second silicon carbide layer is calculated as a value obtained by multiplying a value obtained by dividing the second thickness by the first thickness, by the first formation time, and a flow rate of a second ammonia gas in a step of forming the second silicon carbide layer by epitaxial growth is calculated as a value obtained by multiplying a value obtained by dividing the second concentration by the first concentration, by the first flow rate.

Abstract: After a dummy control gate electrode and a memory gate electrode are formed and an interlayer insulating film is formed so as to cover the gate electrodes, the interlayer insulating film is polished to expose the dummy control gate electrode and the memory gate electrode. Thereafter, the dummy control gate electrode is removed by etching, and then a control gate electrode is formed in a trench which is a region from which the dummy control gate electrode has been removed. The dummy control gate electrode is made of a non-doped or n type silicon film, and the memory gate electrode is made of a p type silicon film. In the process of removing the dummy control gate electrode, the dummy control gate electrode is removed by performing etching under the condition that the memory gate electrode is less likely to be etched compared with the dummy control gate electrode, in the state where the dummy control gate electrode and the memory gate electrode are exposed.

Abstract: An electro-optical package. In some embodiments, the electro-optical package includes a first electro-optical chip coupled to an array of optical fibers, and a first physical medium dependent integrated circuit coupled to the first electro-optical chip.

Abstract: An electro-optical package. In some embodiments, the electro-optical package includes a first electro-optical chip coupled to an array of optical fibers, and a first physical medium dependent integrated circuit coupled to the first electro-optical chip.

Abstract: A single chip including an optoelectronic device on the semiconductor layer in a first region, the optoelectronic device comprises a bottom cladding layer, an active region, and a top cladding layer, wherein the bottom cladding layer is above and in direct contact with the semiconductor layer, the active region is above and in direct contact with the bottom cladding layer, and the top cladding layer is above and in direct contact with the active region, a silicon device on the substrate extension layer in a second region, a device insulator layer substantially covering both the optoelectronic device in the first region and the silicon device in the second region, and a waveguide embedded within the device insulator layer in direct contact with a sidewall of the active region of the optoelectronic device.

Abstract: A method of evaluating localized degradation of a III-V compound semiconductor. The method includes preparing first and second III-V compound semiconductors. The second III-V compound semiconductor that is similar to the first III-V compound semiconductor and further comprises a shield layer that is configured to alter exposed portions of channels of the second III-V compound semiconductor. The first and second III-V compound semiconductors and irradiated and then electrically tested. Results of the electrical testing of the first and second III-V compound semiconductors are compared.

Abstract: The present invention provides a method which can significantly increase the signal-to-noise ratio of an ultrasound-modulated optical signal by overcoming the shallow depth problem of in vivo optical imaging in existing optical imaging by use of a quantum optical phenomenon based on ultraslow light and nondegenerate phase conjugation and which can be applied directly not only to medical optical imaging, but also to medical photodynamic therapy, through slow light amplification of phase conjugate waves.

Abstract: A method of forming a fin field effect transistor circuit is provided. The method includes forming a plurality of vertical fins on a substrate, and forming a protective liner having a varying thickness on the substrate and plurality of vertical fins. The method further includes removing thinner portions of the protective liner from the substrate to form protective liner segments on the plurality of vertical fins. The method further includes removing portions of the substrate exposed by removing the thinner portions of the protective liner to form trenches adjacent to at least one pair of vertical fins and two substrate mesas. The method further includes laterally etching the substrate mesa to widen the trench, reduce the width of the substrate mesa to form a supporting pillar, and undercut the at least one pair of vertical fins, and forming a first bottom source/drain layer in the widened trench.

Abstract: A method for forming a semiconductor device is provided. The method includes forming a gate stack to partially cover a semiconductor structure. The method also includes forming a first semiconductor material over the semiconductor structure. The method further includes forming a second semiconductor material over the first semiconductor material. In addition, the method includes forming a third semiconductor material over the second semiconductor material. The first semiconductor material and the third semiconductor material together surround the second semiconductor material. The second semiconductor material has a greater dopant concentration than that of the first semiconductor material or that of the third semiconductor material.

Abstract: A device structure includes: a core structure formed on a support, and a shell material formed on the core structure and surrounding at least part of the core structure. The shell material is associated with a first bandgap; the core structure is associated with a second bandgap; and the first bandgap is smaller than the second bandgap. The shell material and the core structure are configured to form a quantum-well channel in the shell material.

Abstract: A method of forming a merged source/drain region is disclosed that includes forming first and second VOCS structures above a semiconductor substrate, forming a recess in the substrate between the first and second VOCS structures and forming a P-type-doped semiconductor material in the recess.

Abstract: The present disclosure provides a display substrate, its manufacturing method, and a display device. The method includes a step of forming a plurality of TFTs. The method further includes steps of: forming a lattice matching layer on a substrate so as to deposit AlN thereon; depositing an AlN layer on the lattice matching layer by low-temperature pulse magnetron sputtering; and forming on the AlN layer GaN LEDs each including an n-type GaN layer, a multilayered quantum well structure and a p-type GaN layer and corresponding to one of the TFTs.

Abstract: A single chip including an optoelectronic device on the semiconductor layer in a first region, the optoelectronic device comprises a bottom cladding layer, an active region, and a top cladding layer, wherein the bottom cladding layer is above and in direct contact with the semiconductor layer, the active region is above and in direct contact with the bottom cladding layer, and the top cladding layer is above and in direct contact with the active region, a silicon device on the substrate extension layer in a second region, a device insulator layer substantially covering both the optoelectronic device in the first region and the silicon device in the second region, and a waveguide embedded within the device insulator layer in direct contact with a sidewall of the active region of the optoelectronic device.

Abstract: There is provided a method of manufacturing a semiconductor device, which includes: forming a first seed layer containing silicon and germanium on a substrate by performing, a predetermined number of times, a cycle which includes supplying a first process gas containing silicon or germanium and containing a halogen element to the substrate, supplying a second process gas containing silicon and not containing a halogen element to the substrate, and supplying a third process gas containing germanium and not containing a halogen element to the substrate; and forming a germanium-containing film on the first seed layer by supplying a fourth process gas containing germanium and not containing a halogen element to the substrate.

Abstract: An object is to provide a semiconductor device having stable electric characteristics in which an oxide semiconductor is used. An oxide semiconductor layer is subjected to heat treatment for dehydration or dehydrogenation treatment in a nitrogen gas or an inert gas atmosphere such as a rare gas (e.g., argon or helium) or under reduced pressure and to a cooling step for treatment for supplying oxygen in an atmosphere of oxygen, an atmosphere of oxygen and nitrogen, or the air (having a dew point of preferably lower than or equal to ?40° C., still preferably lower than or equal to ?50° C.) atmosphere. The oxide semiconductor layer is thus highly purified, whereby an i-type oxide semiconductor layer is formed. A semiconductor device including a thin film transistor having the oxide semiconductor layer is manufactured.

Abstract: The invention relates to a surface treatment method for treating the inner walls of a microchannel made from a polymeric material that is at least partially photocured or thermoset. Said treatment is carried out via irradiation in the air at a wavelength of less than or equal to 300 nm. The invention also relates to a method for manufacturing a microfluidic device including such a surface treatment step.

Abstract: A semiconductor structure is provided by a process in which two aspect ratio trapping processes are employed. The structure includes a semiconductor substrate portion of a first semiconductor material having a first lattice constant. A plurality of first semiconductor-containing pillar structures of a second semiconductor material having a second lattice constant that is greater than the first lattice constant extend upwards from a surface of the semiconductor substrate portion. A plurality of second semiconductor-containing pillar structures of a third semiconductor material having a third lattice constant that is greater than the first lattice constant extend upwards from another surface of the semiconductor substrate portion. A spacer separates each first semiconductor-containing pillar structure from each second semiconductor-containing pillar structure. Each second semiconductor-containing pillar structure has a width that is different from a width of each first semiconductor-containing pillar structure.

Abstract: The presence of a facet or a void in an epitaxially grown crystal indicates that crystal growth has been interrupted by defects or by certain material boundaries. Faceting can be suppressed during epitaxial growth of silicon compounds that form source and drain regions of strained silicon transistors. It has been observed that faceting can occur when epitaxial layers of certain silicon compounds are grown adjacent to an oxide boundary, but faceting does not occur when the epitaxial layer is grown adjacent to a silicon boundary or adjacent to a nitride boundary. Because epitaxial growth of silicon compounds is often necessary in the vicinity of isolation trenches that are filled with oxide, techniques for suppression of faceting in these areas are of particular interest. One such technique, presented herein, is to line the isolation trenches with SiN to provide a barrier between the oxide and the region in which epitaxial growth is intended.

Abstract: Forming an SRAM cell that includes first and second inverters cross-coupled for data storage, each inverter including at least one pull-up device and at least one pull-down devices; and at least two pass-gate devices configured with the two cross-coupled inverters, the pull-up devices, the pull-down devices and the pass-gate devices include a tunnel field effect transistor (TFET) that further includes a semiconductor mesa formed on a semiconductor substrate and having a bottom portion, a middle portion and a top portion; a drain of a first conductivity type formed in the bottom portion and extended into the semiconductor substrate; a source of a second conductivity type formed in the top portion, the second conductivity type being opposite to the first conductivity type; a channel in a middle portion and interposed between the source and drain; and a gate formed on sidewall of the semiconductor mesa and contacting the channel.

Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. A structure includes a relaxed substrate including a bulk material, a strained layer directly on the relaxed substrate, where a strain of the strained layer is not induced by the relaxed substrate, and a transistor formed on the strained layer.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a gate dielectric layer, a work function layer, and a conductive filling over the work function layer. The semiconductor device structure also includes a dielectric layer covering the fin structure. The dielectric layer is in direct contact with the conductive filling.

Abstract: A silicon-based quantum dot device (1) is disclosed. The device comprises a substrate (8) and a layer (7) of silicon or silicon-germanium supported on the substrate which is configured to provide at least one quantum dot (51, 52: FIG. 5). The layer of silicon or silicon-germanium has a thickness of no more than ten monolayers. The layer of silicon or silicon-germanium may have a thickness of no more than eight or five monolayers.