Deposition Of Semiconductor Material On Substrate, E.g., Epitaxial Growth, Solid Phase Epitaxy (epo) Patents (Class 257/E21.09)

  • Patent number: 11864471
    Abstract: A described example includes: a semiconductor die including a Hall sensor arranged in a first plane that is parallel to a device side surface of the semiconductor die; a passivated magnetic concentrator including a magnetic alloy layer formed over the device side surface of the semiconductor die, the upper surface of the magnetic alloy layer covered by a layer of polymer material; a backside surface of the semiconductor die opposite the device side surface mounted to a die side surface of a die pad on a package substrate, the semiconductor die having bond pads on the device side surface spaced from the magnetic concentrator; electrical connections coupling the bond pads of the semiconductor die to leads of the package substrate; and mold compound covering the magnetic concentrator, the semiconductor die, the electrical connections, a portion of the leads, and the die side surface of the die pad.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: January 2, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Rafael Jose Lizares Guevara, Dok Won Lee, Kashyap Mohan
  • Patent number: 11864472
    Abstract: A method for etching a surface including obtaining a structure comprising a plurality of nanowires on or above a substrate and a dielectric layer on or above the nanowires, wherein the dielectric layer comprises protrusions formed by the underlying nanowires; reacting a surface of the dielectric layer with a reactant, comprising a gas or a plasma, to form a reactive layer on the dielectric layer, wherein the reactive layer comprises a chemical compound including the reactant and elements of the dielectric layer and the reactive layer comprises sidewalls defined by the protrusions; and selectively etching the reactive layer, wherein the etching etches the protrusions laterally through the sidewalls so as to planarize the surface and remove or shrink the protrusions.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: January 2, 2024
    Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Harold Frank Greer, Andrew D. Beyer, Matthew D. Shaw, Daniel P. Cunnane
  • Patent number: 11862628
    Abstract: Methods, systems, and devices for transistor configurations for multi-deck memory devices are described. A memory device may include a first set of transistors formed in part by doping portions of a first semiconductor substrate of the memory device. The memory device may include a set of memory cells arranged in a stack of decks of memory cells above the first semiconductor substrate and a second semiconductor substrate bonded above the stack of decks. The memory device may include a second set of transistors formed in part by doping portions of the second semiconductor substrate. The stack of decks may include a lower set of one or more decks that is coupled with the first set of transistors and an upper set of one or more decks that is coupled with the second set of transistors.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: January 2, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Fatma Arzum Simsek-Ege
  • Patent number: 11846022
    Abstract: A thin-film-deposition machine includes a chamber, a carrier, an extraction ring and a dispensing unit. The chamber includes a containing space and an extraction channel disposed around the containing space. The extraction channel is partitioned into a first, a second and a third channel areas. The carrier is disposed within the containing space. The first channel area is connected to the third channel area via the second channel area. The third channel area is formed with a height greater than that of the first channel area. The extraction ring includes a plurality of extraction holes and a ring channel. The extraction holes are disposed around the carrier for extracting gas from the containing space to the extraction channel, sequentially via the extraction holes, the ring channel. Thereby an even and steady flow field can be formed above the carrier and the thickness uniformity of film deposition can be improved.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: December 19, 2023
    Assignee: SKY TECH INC.
    Inventors: Jing-Cheng Lin, Ta-Hao Kuo
  • Patent number: 11800713
    Abstract: A semiconductor device includes: a gate structure including conductive layers and insulating layers, which are alternately stacked; a channel layer penetrating the gate structure; memory patterns respectively located between the channel layer and the conductive layers; a blocking layer including first parts located between the memory patterns and the conductive layers, and second parts extending between the memory patterns and protruding toward the insulating layers to the inside of the gate structure; and air gaps including a first region located in the second parts and a second region located between the memory patterns.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: October 24, 2023
    Assignee: SK hynix Inc.
    Inventors: In Ku Kang, Changhan Kim
  • Patent number: 11777032
    Abstract: A semiconductor device may include semiconductor patterns, a gate structure, a first spacer, a first semiconductor layer and a second semiconductor layer. The semiconductor patterns may be formed on a substrate, and may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and may overlap in the vertical direction. The gate structure may be formed on the substrate and the semiconductor patterns. At least portion of the gate structure may be formed vertically between the semiconductor patterns. The first spacer may cover opposite sidewalls of the gate structure, the sidewalls opposite to each other in a first direction. The first semiconductor layer may cover the sidewalls of the semiconductor patterns in the first direction, and surfaces of the first spacer and the substrate. The first semiconductor layer may have a first concentration of impurities.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: October 3, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youngdae Cho, Sunguk Jang, Sujin Jung, Jungtaek Kim, Sihyung Lee
  • Patent number: 11735555
    Abstract: A manufacturing method of a semiconductor structure includes covering first and second semiconductor dies with an insulating encapsulant. The first semiconductor die includes an active surface accessibly exposed by the insulating encapsulant and a first conductive terminal distributed at the active surface. The second semiconductor die includes an active surface accessibly exposed by the insulating encapsulant and a second conductive terminal distributed at the active surface. A redistribution circuit layer is formed on the insulating encapsulant and the active surfaces of the first and second semiconductor dies. A conductive trace of the redistribution circuit layer is electrically connected from the first semiconductor die and meanderingly extends to the second semiconductor die, and a ratio of a total length of the conductive trace to a top width of the insulating encapsulant between the first and second semiconductor dies ranges from about 3 to about 10.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: August 22, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen, Ying-Ju Chen
  • Patent number: 11721548
    Abstract: In an embodiment, a first recess and a second recess, designed to reach a first semiconductor layer, are formed in the portions of a first threading dislocation and a second threading dislocation having reached the surface. Further, the first semiconductor layer is oxidized through the first recess and the second recess to form an insulating film configured to cover the lower surface of a second semiconductor layer.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: August 8, 2023
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Ryo Nakao, Tomonari Sato
  • Patent number: 11723210
    Abstract: In some embodiments, the present disclosure relates to a method for forming a memory device, including forming a plurality of word line stacks respectively including a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate, forming a data storage layer along opposing sidewalls of the word line stacks, forming a channel layer along opposing sidewalls of the data storage layer, forming an inner insulating layer between inner sidewalls of the channel layer and including a first dielectric material, performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening, forming an isolation structure filling the isolation opening and including a second dielectric material, performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings, and forming source/drain contacts in the source/drain
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: August 8, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsu Ching Yang, Feng-Cheng Yang, Sheng-Chih Lai, Yu-Wei Jiang, Kuo-Chang Chiang, Hung-Chang Sun, Chen-Jun Wu, Chung-Te Lin
  • Patent number: 11710662
    Abstract: Multiple wide bandgap semiconductor wafers, each having active circuitry and an epitaxially formed backside drain contact layer, may be constructed from a single bulk semiconductor substrate by: forming foundational layers on the top of the bulk substrate via epitaxy; forming active circuitry atop the foundational layers; laser treating the backside of the bulk substrate to create a cleave line in one of the foundational layers; and exfoliating a semiconductor wafer from the bulk substrate, where the exfoliated semiconductor wafer contains the active circuits and at least a portion of the foundational layers. Wafers containing the foundational layers without complete active devices may be produced in a similar manner. The foundational layers may comprise a drain contact layer and a drift layer, and may additionally include a buffer layer between the drain contact layer and the drift layer.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: July 25, 2023
    Assignee: United Silicon Carbide, Inc.
    Inventors: Anup Bhalla, Leonid Fursin
  • Patent number: 11688769
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a source/drain structure adjacent to the gate stack. The semiconductor device structure also includes a cap element over the source/drain structure. The cap element has a first top plane, and the source/drain structure has a second top plane. The first top plane of the cap element is wider than the second top plane of the source/drain structure. A surface orientation of the first top plane of the cap element and a surface orientation of a side surface of the cap element are different from each other. The surface orientation of the first top plane of the cap element is {311}.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: June 27, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shing-Huang Wu, Jian-Shian Chen
  • Patent number: 11631461
    Abstract: A three dimension memory device including a plurality of word lines, a plurality of first switches, a plurality of second switches and N conductive wire layers is provided, where N is a positive integer larger than 1. The word lines are divided into a plurality of word line groups. The first switches receive a common word line voltage. The second switches receive a reference ground voltage. A first word line group is connected to a first conductive wire layer through a second conductive wire layer. An ith word line group is connected to the first conductive wire layer through an (i+1)th to the second conductive wire layer in sequence.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: April 18, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Teng-Hao Yeh
  • Patent number: 11621395
    Abstract: A memory apparatus includes an interconnect in a first dielectric above a substrate and a structure above the interconnect, where the structure includes a diffusion barrier material and covers the interconnect. The memory apparatus further includes a resistive random-access memory (RRAM) device coupled to the interconnect. The RRAM device includes a first electrode on a portion of the structure, a stoichiometric layer having a metal and oxygen on the first electrode, a non-stoichiometric layer including the metal and oxygen on the stoichiometric layer. A second electrode including a barrier material is on the non-stoichiometric layer. In some embodiments, the RRAM device further includes a third electrode on the second electrode. To prevent uncontrolled oxidation during a fabrication process a spacer may be directly adjacent to the RRAM device, where the spacer includes a second dielectric.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: April 4, 2023
    Assignee: Intel Corporation
    Inventors: Nathan Strutt, Albert Chen, Pedro Quintero, Oleg Golonzka
  • Patent number: 11616161
    Abstract: A photodetector comprising an optical waveguide structure comprising at least three stripes spaced from one another such that a slot is present between each two adjacent stripes of the at least three stripes. A graphene absorption layer is provided over or underneath the at least three stripes. There is an electrode for each stripe, over or underneath the graphene absorption layer. The photodetector is configured such that two adjacent electrodes are biased using opposite polarities to create a p-n junction effect in a portion of the graphene absorption layer. In particular the portion of the graphene absorption layer is located over or underneath each respective slot between said each two adjacent stripes.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: March 28, 2023
    Assignee: CAMBRIDGE ENTERPRISE LIMITED
    Inventors: Andrea Carlo Ferrari, Luigi Occhipinti, Alfonso Ruocco
  • Patent number: 11563005
    Abstract: A three-dimensional semiconductor device includes a first channel pattern on and spaced apart from a substrate, the first channel pattern having a first end and a second end that are spaced apart from each other in a first direction parallel to a top surface of the substrate, and a first sidewall and a second sidewall connecting between the first end and the second end, the first and second sidewalls being spaced apart from each other in a second direction parallel to the top surface of the substrate, the second direction intersecting the first direction, a bit line in contact with the first end of the first channel pattern, the bit line extending in a third direction perpendicular to the top surface of the substrate, and a first gate electrode adjacent to the first sidewall of the first channel pattern.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: January 24, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Minsu Lee, Kiseok Lee, Minwoo Song, Hyun-Sil Oh, Min Hee Cho
  • Patent number: 11424363
    Abstract: A programmable charge-storage transistor comprises channel material, insulative charge-passage material, charge-storage material, a control gate, and charge-blocking material between the charge-storage material and the control gate. The charge-blocking material comprises a non-ferroelectric insulator material and a ferroelectric insulator material. Arrays of elevationally-extending strings of memory cells of memory cells are disclosed, including methods of forming such. Other embodiments, including method, are disclosed.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: August 23, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Haitao Liu, Kamal M. Karda, Albert Fayrushin
  • Patent number: 11373868
    Abstract: In a step of calculating formation conditions for the second silicon carbide layer, a formation time of the second silicon carbide layer is calculated as a value obtained by multiplying a value obtained by dividing the second thickness by the first thickness, by the first formation time, and a flow rate of a second ammonia gas in a step of forming the second silicon carbide layer by epitaxial growth is calculated as a value obtained by multiplying a value obtained by dividing the second concentration by the first concentration, by the first flow rate.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: June 28, 2022
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Hironori Itoh
  • Patent number: 11183510
    Abstract: After a dummy control gate electrode and a memory gate electrode are formed and an interlayer insulating film is formed so as to cover the gate electrodes, the interlayer insulating film is polished to expose the dummy control gate electrode and the memory gate electrode. Thereafter, the dummy control gate electrode is removed by etching, and then a control gate electrode is formed in a trench which is a region from which the dummy control gate electrode has been removed. The dummy control gate electrode is made of a non-doped or n type silicon film, and the memory gate electrode is made of a p type silicon film. In the process of removing the dummy control gate electrode, the dummy control gate electrode is removed by performing etching under the condition that the memory gate electrode is less likely to be etched compared with the dummy control gate electrode, in the state where the dummy control gate electrode and the memory gate electrode are exposed.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: November 23, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tatsuyoshi Mihara
  • Patent number: 11054597
    Abstract: An electro-optical package. In some embodiments, the electro-optical package includes a first electro-optical chip coupled to an array of optical fibers, and a first physical medium dependent integrated circuit coupled to the first electro-optical chip.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: July 6, 2021
    Assignee: Rockley Photonics Limited
    Inventors: Vivek Raghunathan, Vivek Raghuraman, Karlheinz Muth, David Arlo Nelson, Chia-Te Chou, Brett Sawyer, SeungJae Lee
  • Patent number: 10921538
    Abstract: An electro-optical package. In some embodiments, the electro-optical package includes a first electro-optical chip coupled to an array of optical fibers, and a first physical medium dependent integrated circuit coupled to the first electro-optical chip.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: February 16, 2021
    Assignee: Rockley Photonics Limited
    Inventors: Vivek Raghunathan, Vivek Raghuraman, Karlheinz Muth, David Arlo Nelson, Chia-Te Chou, Brett Sawyer, SeungJae Lee
  • Patent number: 10784292
    Abstract: A single chip including an optoelectronic device on the semiconductor layer in a first region, the optoelectronic device comprises a bottom cladding layer, an active region, and a top cladding layer, wherein the bottom cladding layer is above and in direct contact with the semiconductor layer, the active region is above and in direct contact with the bottom cladding layer, and the top cladding layer is above and in direct contact with the active region, a silicon device on the substrate extension layer in a second region, a device insulator layer substantially covering both the optoelectronic device in the first region and the silicon device in the second region, and a waveguide embedded within the device insulator layer in direct contact with a sidewall of the active region of the optoelectronic device.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: September 22, 2020
    Assignee: International Business Machines Corporation
    Inventors: Effendi Leobandung, Ning Li, Devendra K. Sadana
  • Patent number: 10784173
    Abstract: A method of evaluating localized degradation of a III-V compound semiconductor. The method includes preparing first and second III-V compound semiconductors. The second III-V compound semiconductor that is similar to the first III-V compound semiconductor and further comprises a shield layer that is configured to alter exposed portions of channels of the second III-V compound semiconductor. The first and second III-V compound semiconductors and irradiated and then electrically tested. Results of the electrical testing of the first and second III-V compound semiconductors are compared.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: September 22, 2020
    Assignee: United States of America as represented by the Secretary of the Air Force
    Inventor: Eric Heller
  • Patent number: 10750948
    Abstract: The present invention provides a method which can significantly increase the signal-to-noise ratio of an ultrasound-modulated optical signal by overcoming the shallow depth problem of in vivo optical imaging in existing optical imaging by use of a quantum optical phenomenon based on ultraslow light and nondegenerate phase conjugation and which can be applied directly not only to medical optical imaging, but also to medical photodynamic therapy, through slow light amplification of phase conjugate waves.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: August 25, 2020
    Assignee: GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventor: Byoung Seung Ham
  • Patent number: 10720364
    Abstract: A method of forming a fin field effect transistor circuit is provided. The method includes forming a plurality of vertical fins on a substrate, and forming a protective liner having a varying thickness on the substrate and plurality of vertical fins. The method further includes removing thinner portions of the protective liner from the substrate to form protective liner segments on the plurality of vertical fins. The method further includes removing portions of the substrate exposed by removing the thinner portions of the protective liner to form trenches adjacent to at least one pair of vertical fins and two substrate mesas. The method further includes laterally etching the substrate mesa to widen the trench, reduce the width of the substrate mesa to form a supporting pillar, and undercut the at least one pair of vertical fins, and forming a first bottom source/drain layer in the widened trench.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: July 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Choonghyun Lee
  • Patent number: 10636909
    Abstract: A method for forming a semiconductor device is provided. The method includes forming a gate stack to partially cover a semiconductor structure. The method also includes forming a first semiconductor material over the semiconductor structure. The method further includes forming a second semiconductor material over the first semiconductor material. In addition, the method includes forming a third semiconductor material over the second semiconductor material. The first semiconductor material and the third semiconductor material together surround the second semiconductor material. The second semiconductor material has a greater dopant concentration than that of the first semiconductor material or that of the third semiconductor material.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: April 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Zheng-Yang Pan, Chun-Chieh Wang, Cheng-Han Lee, Shih-Chieh Chang
  • Patent number: 10553718
    Abstract: A device structure includes: a core structure formed on a support, and a shell material formed on the core structure and surrounding at least part of the core structure. The shell material is associated with a first bandgap; the core structure is associated with a second bandgap; and the first bandgap is smaller than the second bandgap. The shell material and the core structure are configured to form a quantum-well channel in the shell material.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: February 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Carlos H. Diaz, Chun-Hsiung Lin, Huicheng Chang, Syun-Ming Jang, Chien-Hsun Wang, Mao-Lin Huang
  • Patent number: 10475904
    Abstract: A method of forming a merged source/drain region is disclosed that includes forming first and second VOCS structures above a semiconductor substrate, forming a recess in the substrate between the first and second VOCS structures and forming a P-type-doped semiconductor material in the recess.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: November 12, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hiroaki Niimi, Steven Bentley, Romain Lallement, Brent A. Anderson, Junli Wang, Muthumanickam Sankarapandian
  • Patent number: 10319781
    Abstract: The present disclosure provides a display substrate, its manufacturing method, and a display device. The method includes a step of forming a plurality of TFTs. The method further includes steps of: forming a lattice matching layer on a substrate so as to deposit AlN thereon; depositing an AlN layer on the lattice matching layer by low-temperature pulse magnetron sputtering; and forming on the AlN layer GaN LEDs each including an n-type GaN layer, a multilayered quantum well structure and a p-type GaN layer and corresponding to one of the TFTs.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: June 11, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Feng Jiang, Li Zhou, Long Wang, Xingdong Liu, Chungchun Lee
  • Patent number: 10283537
    Abstract: A single chip including an optoelectronic device on the semiconductor layer in a first region, the optoelectronic device comprises a bottom cladding layer, an active region, and a top cladding layer, wherein the bottom cladding layer is above and in direct contact with the semiconductor layer, the active region is above and in direct contact with the bottom cladding layer, and the top cladding layer is above and in direct contact with the active region, a silicon device on the substrate extension layer in a second region, a device insulator layer substantially covering both the optoelectronic device in the first region and the silicon device in the second region, and a waveguide embedded within the device insulator layer in direct contact with a sidewall of the active region of the optoelectronic device.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: May 7, 2019
    Assignee: International Business Machines Corporation
    Inventors: Effendi Leobandung, Ning Li, Devendra K. Sadana
  • Patent number: 10199219
    Abstract: There is provided a method of manufacturing a semiconductor device, which includes: forming a first seed layer containing silicon and germanium on a substrate by performing, a predetermined number of times, a cycle which includes supplying a first process gas containing silicon or germanium and containing a halogen element to the substrate, supplying a second process gas containing silicon and not containing a halogen element to the substrate, and supplying a third process gas containing germanium and not containing a halogen element to the substrate; and forming a germanium-containing film on the first seed layer by supplying a fourth process gas containing germanium and not containing a halogen element to the substrate.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: February 5, 2019
    Assignee: Hitachi Kokusai Electric, Inc.
    Inventors: Satoshi Shimamoto, Yoshiro Hirose, Hajime Karasawa, Ryota Horiike, Naoharu Nakaiso, Yoshitomo Hashimoto
  • Patent number: 10186619
    Abstract: An object is to provide a semiconductor device having stable electric characteristics in which an oxide semiconductor is used. An oxide semiconductor layer is subjected to heat treatment for dehydration or dehydrogenation treatment in a nitrogen gas or an inert gas atmosphere such as a rare gas (e.g., argon or helium) or under reduced pressure and to a cooling step for treatment for supplying oxygen in an atmosphere of oxygen, an atmosphere of oxygen and nitrogen, or the air (having a dew point of preferably lower than or equal to ?40° C., still preferably lower than or equal to ?50° C.) atmosphere. The oxide semiconductor layer is thus highly purified, whereby an i-type oxide semiconductor layer is formed. A semiconductor device including a thin film transistor having the oxide semiconductor layer is manufactured.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: January 22, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Miyuki Hosoba, Junichiro Sakata, Hiroki Ohara, Shunpei Yamazaki
  • Patent number: 10159974
    Abstract: The invention relates to a surface treatment method for treating the inner walls of a microchannel made from a polymeric material that is at least partially photocured or thermoset. Said treatment is carried out via irradiation in the air at a wavelength of less than or equal to 300 nm. The invention also relates to a method for manufacturing a microfluidic device including such a surface treatment step.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: December 25, 2018
    Assignees: TOTAL PETROCHEMICALS, ECOLE SUPERIEURE DE PHYSIQUE ET CHIMIE INDUSTRIELLES DE LA VILLE DE PARIS, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE-CNRS
    Inventors: Ammar Azioune, Denis Bartolo, Bertrand Levache, Vincent Studer
  • Patent number: 10147602
    Abstract: A semiconductor structure is provided by a process in which two aspect ratio trapping processes are employed. The structure includes a semiconductor substrate portion of a first semiconductor material having a first lattice constant. A plurality of first semiconductor-containing pillar structures of a second semiconductor material having a second lattice constant that is greater than the first lattice constant extend upwards from a surface of the semiconductor substrate portion. A plurality of second semiconductor-containing pillar structures of a third semiconductor material having a third lattice constant that is greater than the first lattice constant extend upwards from another surface of the semiconductor substrate portion. A spacer separates each first semiconductor-containing pillar structure from each second semiconductor-containing pillar structure. Each second semiconductor-containing pillar structure has a width that is different from a width of each first semiconductor-containing pillar structure.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: December 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 10134743
    Abstract: Forming an SRAM cell that includes first and second inverters cross-coupled for data storage, each inverter including at least one pull-up device and at least one pull-down devices; and at least two pass-gate devices configured with the two cross-coupled inverters, the pull-up devices, the pull-down devices and the pass-gate devices include a tunnel field effect transistor (TFET) that further includes a semiconductor mesa formed on a semiconductor substrate and having a bottom portion, a middle portion and a top portion; a drain of a first conductivity type formed in the bottom portion and extended into the semiconductor substrate; a source of a second conductivity type formed in the top portion, the second conductivity type being opposite to the first conductivity type; a channel in a middle portion and interposed between the source and drain; and a gate formed on sidewall of the semiconductor mesa and contacting the channel.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: November 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Harry-Hak-Lay Chuang, Bao-Ru Young, Ming Zhu, Wei Cheng Wu, Yi-Ren Chen
  • Patent number: 10134895
    Abstract: The presence of a facet or a void in an epitaxially grown crystal indicates that crystal growth has been interrupted by defects or by certain material boundaries. Faceting can be suppressed during epitaxial growth of silicon compounds that form source and drain regions of strained silicon transistors. It has been observed that faceting can occur when epitaxial layers of certain silicon compounds are grown adjacent to an oxide boundary, but faceting does not occur when the epitaxial layer is grown adjacent to a silicon boundary or adjacent to a nitride boundary. Because epitaxial growth of silicon compounds is often necessary in the vicinity of isolation trenches that are filled with oxide, techniques for suppression of faceting in these areas are of particular interest. One such technique, presented herein, is to line the isolation trenches with SiN to provide a barrier between the oxide and the region in which epitaxial growth is intended.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: November 20, 2018
    Assignee: STMicroelectronics, Inc.
    Inventors: Nicolas Loubet, Prasanna Khare, Qing Liu
  • Patent number: 10050145
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. A structure includes a relaxed substrate including a bulk material, a strained layer directly on the relaxed substrate, where a strain of the strained layer is not induced by the relaxed substrate, and a transistor formed on the strained layer.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Anthony J. Lochtefeld, Thomas A. Langdo, Richard Hammond, Matthew T. Currie, Eugene A. Fitzgerald
  • Patent number: 10037917
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a gate dielectric layer, a work function layer, and a conductive filling over the work function layer. The semiconductor device structure also includes a dielectric layer covering the fin structure. The dielectric layer is in direct contact with the conductive filling.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: July 31, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 9941430
    Abstract: A silicon-based quantum dot device (1) is disclosed. The device comprises a substrate (8) and a layer (7) of silicon or silicon-germanium supported on the substrate which is configured to provide at least one quantum dot (51, 52: FIG. 5). The layer of silicon or silicon-germanium has a thickness of no more than ten monolayers. The layer of silicon or silicon-germanium may have a thickness of no more than eight or five monolayers.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: April 10, 2018
    Assignee: HITACHI, LTD.
    Inventors: Aleksey Andreev, David Williams, Ryuta Tsuchiya, Yuji Suwa
  • Patent number: 9855549
    Abstract: A metal oxide nanorod array structure according to embodiments disclosed herein includes a monolithic substrate having a surface and multiple channels, an interface layer bonded to the surface of the substrate, and a metal oxide nanorod array coupled to the substrate surface via the interface layer. The metal oxide can include ceria, zinc oxide, tin oxide, alumina, zirconia, cobalt oxide, and gallium oxide. The substrate can include a glass substrate, a plastic substrate, a silicon substrate, a ceramic monolith, and a stainless steel monolith. The ceramic can include cordierite, alumina, tin oxide, and titania. The nanorod array structure can include a perovskite shell, such as a lanthanum-based transition metal oxide, or a metal oxide shell, such as ceria, zinc oxide, tin oxide, alumina, zirconia, cobalt oxide, and gallium oxide, or a coating of metal particles, such as platinum, gold, palladium, rhodium, and ruthenium, over each metal oxide nanorod.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: January 2, 2018
    Assignee: UNIVERSITY OF CONNECTICUT
    Inventors: Pu-Xian Gao, Yanbing Guo, Zheng Ren
  • Patent number: 9842964
    Abstract: A method for producing a semiconductor layer sequence is disclosed. In an embodiment the includes growing a first nitridic semiconductor layer at the growth side of a growth substrate, growing a second nitridic semiconductor layer having at least one opening on the first nitridic semiconductor layer, removing at least pail of the first nitridic semiconductor layer through the at least one opening in the second nitridic semiconductor layer, growing a third nitridic semiconductor layer on the second nitridic semiconductor layer, wherein the third nitridic semiconductor layer covers the at least one opening at least in places in such a way that at least one cavity free of a semiconductor material is present between the growth substrate and a subsequent semiconductor layers and removing the growth substrate.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: December 12, 2017
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Joachim Hertkorn, Werner Bergbauer
  • Patent number: 9786548
    Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: October 10, 2017
    Assignee: Micron Technology, Inc.
    Inventor: David H. Wells
  • Patent number: 9761717
    Abstract: A method for forming strained fins includes etching trenches in a bulk substrate to form fins, filling the trenches with a dielectric fill and recessing the dielectric fill into the trenches to form shallow trench isolation regions. The fins are etched above the shallow trench isolation regions to form a staircase fin structure with narrow top portions of the fins. Gate structures are formed over the top portions of the fins. Raised source ad drain regions are epitaxially grown on opposite sides of the gate structure. A pre-morphization implant is performed to generate defects in the substrate to couple strain into the top portions of the fins.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: September 12, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Chun-Chen Yeh
  • Patent number: 9761661
    Abstract: A method for forming nanowires includes forming a plurality of epitaxial layers on a substrate, the layers including alternating material layers with high and low Ge concentration and patterning the plurality of layers to form fins. The fins are etched to form recesses in low Ge concentration layers to form pillars between high Ge concentration layers. The pillars are converted to dielectric pillars. A conformal material is formed in the recesses and on the dielectric pillars. The high Ge concentration layers are condensed to form hexagonal Ge wires with (111) facets. The (111) facets are exposed to form nanowires.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: September 12, 2017
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Pouya Hashemi, John A. Ott, Alexander Reznicek
  • Patent number: 9755104
    Abstract: A method of forming a rough surface includes: providing an article having a top surface, forming a plurality of agglomerated grains on the top surface by a deposition process, and patterning the top surface to form a rough surface by using the plurality of agglomerated grains as a mask.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: September 5, 2017
    Assignee: EPISTAR CORPORATION
    Inventors: Wei Jung Chung, Chi Hao Huang
  • Patent number: 9740082
    Abstract: A method of poling an organic polymeric electro-optic material. The method includes doping the organic polymeric electro-optic material with nanoparticles. The method also includes heating the organic polymeric electro-optic material to a poling temperature. The method also includes poling the organic polymeric electro-optic material by applying an electric field across the organic polymeric electro-optic material.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: August 22, 2017
    Assignee: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM
    Inventors: Benjamin R. Lund, Samsuddin Faisal Mahmood, Naixin Yang
  • Patent number: 9721950
    Abstract: A semiconductor device including fin type patterns is provided. The semiconductor device includes a first fin type pattern, a field insulation layer disposed in vicinity of the first fin type pattern and having a first part and a second part, the first part protruding from the second part, a first dummy gate stack formed on the first part of the field insulation layer and including a first dummy gate insulation layer having a first thickness, and a first gate stack formed on the second part of the field insulation layer to intersect the first fin type pattern and including a first gate insulation layer having a second thickness different from the first thickness.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: August 1, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Gun You, Jae-Chul Kim
  • Patent number: 9721951
    Abstract: According to one embodiment, a semiconductor device includes a first complementary semiconductor device provided on a semiconductor substrate, and including a CMOS circuit, a metal electrode provided above the first complementary semiconductor device, a semiconductor layer provided above the metal electrode, including an nMOS region and a pMOS region separated from each other, and containing Ge; and a second complementary semiconductor device including an nMOSFET provided on the first portion of the semiconductor layer and a pMOSFET provided on the second portion of the semiconductor layer.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: August 1, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiji Ikeda, Tsutomu Tezuka, Yuuichi Kamimuta, Kiyoe Furuse
  • Patent number: 9679966
    Abstract: The electronic device comprises a substrate (1), at least one semiconductor nanowire (2) and a buffer layer (3) interposed between the substrate (1) and said nanowire (2). The buffer layer (3) is at least partly formed by a transition metal nitride layer (9) from which extends the nanowire (2), said transition metal nitride being chosen from: vanadium nitride, chromium nitride, zirconium nitride, niobium nitride, molybdenum nitride, hafnium nitride or tantalum nitride.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: June 13, 2017
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Berangere Hyot, Benoit Amstatt, Marie-Francoise Armand
  • Patent number: 9627266
    Abstract: A method of forming an active device on a semiconductor wafer includes the steps of: forming a plurality of semiconductor fins on at least a portion of a semiconductor substrate; forming a dielectric layer on at least a portion of the semiconductor substrate, the dielectric layer filling gaps between adjacent fins; forming a plurality of gate structures on an upper surface of the dielectric layer; forming a channel region on the dielectric layer and under at least a portion of the gate structures, the channel region comprising a first crystalline semiconductor material; forming source and drain epitaxy regions on an upper surface of the dielectric layer and between adjacent gate structures, the source and rain regions being spaced laterally from one another; and replacing the channel region with a second crystalline semiconductor material after high-temperature processing used in fabricating the active device has been completed.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: April 18, 2017
    Assignee: International Business Machines Corporation
    Inventors: Sanghoon Lee, Effendi Leobandung, Renee T. Mo, Yanning Sun
  • Patent number: 9601565
    Abstract: A semiconductor structure including: trench-defining layer; an epitaxial layer; and a set of defect-blocking member(s). The trench-defining layer includes a trench surface which defines an elongated interior space called the “trench.” The epitaxial layer is grown epitaxially in the interior space of the trench. Each defect blocking member of the set of defect blocking members: (i) extends from a portion of trench surface into the interior space of the trench; and (ii) is located below a top surface of the epitaxial layer. The defect blocking member(s) are designed to arrest the propagation of generally-longitudinal defects in the epitaxial layer, as it is grown, where the generally-longitudinal defects are defects that propagate at least generally in the elongation direction of the trench.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: March 21, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Judson R. Holt, Shogo Mochizuki, Alexander Reznicek, Melissa A. Smith