Deposition Of Semiconductor Material On Substrate, E.g., Epitaxial Growth, Solid Phase Epitaxy (epo) Patents (Class 257/E21.09)

  • Patent number: 10720364
    Abstract: A method of forming a fin field effect transistor circuit is provided. The method includes forming a plurality of vertical fins on a substrate, and forming a protective liner having a varying thickness on the substrate and plurality of vertical fins. The method further includes removing thinner portions of the protective liner from the substrate to form protective liner segments on the plurality of vertical fins. The method further includes removing portions of the substrate exposed by removing the thinner portions of the protective liner to form trenches adjacent to at least one pair of vertical fins and two substrate mesas. The method further includes laterally etching the substrate mesa to widen the trench, reduce the width of the substrate mesa to form a supporting pillar, and undercut the at least one pair of vertical fins, and forming a first bottom source/drain layer in the widened trench.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: July 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Choonghyun Lee
  • Patent number: 10636909
    Abstract: A method for forming a semiconductor device is provided. The method includes forming a gate stack to partially cover a semiconductor structure. The method also includes forming a first semiconductor material over the semiconductor structure. The method further includes forming a second semiconductor material over the first semiconductor material. In addition, the method includes forming a third semiconductor material over the second semiconductor material. The first semiconductor material and the third semiconductor material together surround the second semiconductor material. The second semiconductor material has a greater dopant concentration than that of the first semiconductor material or that of the third semiconductor material.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: April 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Zheng-Yang Pan, Chun-Chieh Wang, Cheng-Han Lee, Shih-Chieh Chang
  • Patent number: 10553718
    Abstract: A device structure includes: a core structure formed on a support, and a shell material formed on the core structure and surrounding at least part of the core structure. The shell material is associated with a first bandgap; the core structure is associated with a second bandgap; and the first bandgap is smaller than the second bandgap. The shell material and the core structure are configured to form a quantum-well channel in the shell material.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: February 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Carlos H. Diaz, Chun-Hsiung Lin, Huicheng Chang, Syun-Ming Jang, Chien-Hsun Wang, Mao-Lin Huang
  • Patent number: 10475904
    Abstract: A method of forming a merged source/drain region is disclosed that includes forming first and second VOCS structures above a semiconductor substrate, forming a recess in the substrate between the first and second VOCS structures and forming a P-type-doped semiconductor material in the recess.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: November 12, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hiroaki Niimi, Steven Bentley, Romain Lallement, Brent A. Anderson, Junli Wang, Muthumanickam Sankarapandian
  • Patent number: 10319781
    Abstract: The present disclosure provides a display substrate, its manufacturing method, and a display device. The method includes a step of forming a plurality of TFTs. The method further includes steps of: forming a lattice matching layer on a substrate so as to deposit AlN thereon; depositing an AlN layer on the lattice matching layer by low-temperature pulse magnetron sputtering; and forming on the AlN layer GaN LEDs each including an n-type GaN layer, a multilayered quantum well structure and a p-type GaN layer and corresponding to one of the TFTs.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: June 11, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Feng Jiang, Li Zhou, Long Wang, Xingdong Liu, Chungchun Lee
  • Patent number: 10283537
    Abstract: A single chip including an optoelectronic device on the semiconductor layer in a first region, the optoelectronic device comprises a bottom cladding layer, an active region, and a top cladding layer, wherein the bottom cladding layer is above and in direct contact with the semiconductor layer, the active region is above and in direct contact with the bottom cladding layer, and the top cladding layer is above and in direct contact with the active region, a silicon device on the substrate extension layer in a second region, a device insulator layer substantially covering both the optoelectronic device in the first region and the silicon device in the second region, and a waveguide embedded within the device insulator layer in direct contact with a sidewall of the active region of the optoelectronic device.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: May 7, 2019
    Assignee: International Business Machines Corporation
    Inventors: Effendi Leobandung, Ning Li, Devendra K. Sadana
  • Patent number: 10199219
    Abstract: There is provided a method of manufacturing a semiconductor device, which includes: forming a first seed layer containing silicon and germanium on a substrate by performing, a predetermined number of times, a cycle which includes supplying a first process gas containing silicon or germanium and containing a halogen element to the substrate, supplying a second process gas containing silicon and not containing a halogen element to the substrate, and supplying a third process gas containing germanium and not containing a halogen element to the substrate; and forming a germanium-containing film on the first seed layer by supplying a fourth process gas containing germanium and not containing a halogen element to the substrate.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: February 5, 2019
    Assignee: Hitachi Kokusai Electric, Inc.
    Inventors: Satoshi Shimamoto, Yoshiro Hirose, Hajime Karasawa, Ryota Horiike, Naoharu Nakaiso, Yoshitomo Hashimoto
  • Patent number: 10186619
    Abstract: An object is to provide a semiconductor device having stable electric characteristics in which an oxide semiconductor is used. An oxide semiconductor layer is subjected to heat treatment for dehydration or dehydrogenation treatment in a nitrogen gas or an inert gas atmosphere such as a rare gas (e.g., argon or helium) or under reduced pressure and to a cooling step for treatment for supplying oxygen in an atmosphere of oxygen, an atmosphere of oxygen and nitrogen, or the air (having a dew point of preferably lower than or equal to ?40° C., still preferably lower than or equal to ?50° C.) atmosphere. The oxide semiconductor layer is thus highly purified, whereby an i-type oxide semiconductor layer is formed. A semiconductor device including a thin film transistor having the oxide semiconductor layer is manufactured.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: January 22, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Miyuki Hosoba, Junichiro Sakata, Hiroki Ohara, Shunpei Yamazaki
  • Patent number: 10159974
    Abstract: The invention relates to a surface treatment method for treating the inner walls of a microchannel made from a polymeric material that is at least partially photocured or thermoset. Said treatment is carried out via irradiation in the air at a wavelength of less than or equal to 300 nm. The invention also relates to a method for manufacturing a microfluidic device including such a surface treatment step.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: December 25, 2018
    Assignees: TOTAL PETROCHEMICALS, ECOLE SUPERIEURE DE PHYSIQUE ET CHIMIE INDUSTRIELLES DE LA VILLE DE PARIS, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE-CNRS
    Inventors: Ammar Azioune, Denis Bartolo, Bertrand Levache, Vincent Studer
  • Patent number: 10147602
    Abstract: A semiconductor structure is provided by a process in which two aspect ratio trapping processes are employed. The structure includes a semiconductor substrate portion of a first semiconductor material having a first lattice constant. A plurality of first semiconductor-containing pillar structures of a second semiconductor material having a second lattice constant that is greater than the first lattice constant extend upwards from a surface of the semiconductor substrate portion. A plurality of second semiconductor-containing pillar structures of a third semiconductor material having a third lattice constant that is greater than the first lattice constant extend upwards from another surface of the semiconductor substrate portion. A spacer separates each first semiconductor-containing pillar structure from each second semiconductor-containing pillar structure. Each second semiconductor-containing pillar structure has a width that is different from a width of each first semiconductor-containing pillar structure.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: December 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 10134895
    Abstract: The presence of a facet or a void in an epitaxially grown crystal indicates that crystal growth has been interrupted by defects or by certain material boundaries. Faceting can be suppressed during epitaxial growth of silicon compounds that form source and drain regions of strained silicon transistors. It has been observed that faceting can occur when epitaxial layers of certain silicon compounds are grown adjacent to an oxide boundary, but faceting does not occur when the epitaxial layer is grown adjacent to a silicon boundary or adjacent to a nitride boundary. Because epitaxial growth of silicon compounds is often necessary in the vicinity of isolation trenches that are filled with oxide, techniques for suppression of faceting in these areas are of particular interest. One such technique, presented herein, is to line the isolation trenches with SiN to provide a barrier between the oxide and the region in which epitaxial growth is intended.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: November 20, 2018
    Assignee: STMicroelectronics, Inc.
    Inventors: Nicolas Loubet, Prasanna Khare, Qing Liu
  • Patent number: 10134743
    Abstract: Forming an SRAM cell that includes first and second inverters cross-coupled for data storage, each inverter including at least one pull-up device and at least one pull-down devices; and at least two pass-gate devices configured with the two cross-coupled inverters, the pull-up devices, the pull-down devices and the pass-gate devices include a tunnel field effect transistor (TFET) that further includes a semiconductor mesa formed on a semiconductor substrate and having a bottom portion, a middle portion and a top portion; a drain of a first conductivity type formed in the bottom portion and extended into the semiconductor substrate; a source of a second conductivity type formed in the top portion, the second conductivity type being opposite to the first conductivity type; a channel in a middle portion and interposed between the source and drain; and a gate formed on sidewall of the semiconductor mesa and contacting the channel.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: November 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Harry-Hak-Lay Chuang, Bao-Ru Young, Ming Zhu, Wei Cheng Wu, Yi-Ren Chen
  • Patent number: 10050145
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. A structure includes a relaxed substrate including a bulk material, a strained layer directly on the relaxed substrate, where a strain of the strained layer is not induced by the relaxed substrate, and a transistor formed on the strained layer.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Anthony J. Lochtefeld, Thomas A. Langdo, Richard Hammond, Matthew T. Currie, Eugene A. Fitzgerald
  • Patent number: 10037917
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a gate dielectric layer, a work function layer, and a conductive filling over the work function layer. The semiconductor device structure also includes a dielectric layer covering the fin structure. The dielectric layer is in direct contact with the conductive filling.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: July 31, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 9941430
    Abstract: A silicon-based quantum dot device (1) is disclosed. The device comprises a substrate (8) and a layer (7) of silicon or silicon-germanium supported on the substrate which is configured to provide at least one quantum dot (51, 52: FIG. 5). The layer of silicon or silicon-germanium has a thickness of no more than ten monolayers. The layer of silicon or silicon-germanium may have a thickness of no more than eight or five monolayers.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: April 10, 2018
    Assignee: HITACHI, LTD.
    Inventors: Aleksey Andreev, David Williams, Ryuta Tsuchiya, Yuji Suwa
  • Patent number: 9855549
    Abstract: A metal oxide nanorod array structure according to embodiments disclosed herein includes a monolithic substrate having a surface and multiple channels, an interface layer bonded to the surface of the substrate, and a metal oxide nanorod array coupled to the substrate surface via the interface layer. The metal oxide can include ceria, zinc oxide, tin oxide, alumina, zirconia, cobalt oxide, and gallium oxide. The substrate can include a glass substrate, a plastic substrate, a silicon substrate, a ceramic monolith, and a stainless steel monolith. The ceramic can include cordierite, alumina, tin oxide, and titania. The nanorod array structure can include a perovskite shell, such as a lanthanum-based transition metal oxide, or a metal oxide shell, such as ceria, zinc oxide, tin oxide, alumina, zirconia, cobalt oxide, and gallium oxide, or a coating of metal particles, such as platinum, gold, palladium, rhodium, and ruthenium, over each metal oxide nanorod.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: January 2, 2018
    Assignee: UNIVERSITY OF CONNECTICUT
    Inventors: Pu-Xian Gao, Yanbing Guo, Zheng Ren
  • Patent number: 9842964
    Abstract: A method for producing a semiconductor layer sequence is disclosed. In an embodiment the includes growing a first nitridic semiconductor layer at the growth side of a growth substrate, growing a second nitridic semiconductor layer having at least one opening on the first nitridic semiconductor layer, removing at least pail of the first nitridic semiconductor layer through the at least one opening in the second nitridic semiconductor layer, growing a third nitridic semiconductor layer on the second nitridic semiconductor layer, wherein the third nitridic semiconductor layer covers the at least one opening at least in places in such a way that at least one cavity free of a semiconductor material is present between the growth substrate and a subsequent semiconductor layers and removing the growth substrate.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: December 12, 2017
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Joachim Hertkorn, Werner Bergbauer
  • Patent number: 9786548
    Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: October 10, 2017
    Assignee: Micron Technology, Inc.
    Inventor: David H. Wells
  • Patent number: 9761717
    Abstract: A method for forming strained fins includes etching trenches in a bulk substrate to form fins, filling the trenches with a dielectric fill and recessing the dielectric fill into the trenches to form shallow trench isolation regions. The fins are etched above the shallow trench isolation regions to form a staircase fin structure with narrow top portions of the fins. Gate structures are formed over the top portions of the fins. Raised source ad drain regions are epitaxially grown on opposite sides of the gate structure. A pre-morphization implant is performed to generate defects in the substrate to couple strain into the top portions of the fins.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: September 12, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Chun-Chen Yeh
  • Patent number: 9761661
    Abstract: A method for forming nanowires includes forming a plurality of epitaxial layers on a substrate, the layers including alternating material layers with high and low Ge concentration and patterning the plurality of layers to form fins. The fins are etched to form recesses in low Ge concentration layers to form pillars between high Ge concentration layers. The pillars are converted to dielectric pillars. A conformal material is formed in the recesses and on the dielectric pillars. The high Ge concentration layers are condensed to form hexagonal Ge wires with (111) facets. The (111) facets are exposed to form nanowires.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: September 12, 2017
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Pouya Hashemi, John A. Ott, Alexander Reznicek
  • Patent number: 9755104
    Abstract: A method of forming a rough surface includes: providing an article having a top surface, forming a plurality of agglomerated grains on the top surface by a deposition process, and patterning the top surface to form a rough surface by using the plurality of agglomerated grains as a mask.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: September 5, 2017
    Assignee: EPISTAR CORPORATION
    Inventors: Wei Jung Chung, Chi Hao Huang
  • Patent number: 9740082
    Abstract: A method of poling an organic polymeric electro-optic material. The method includes doping the organic polymeric electro-optic material with nanoparticles. The method also includes heating the organic polymeric electro-optic material to a poling temperature. The method also includes poling the organic polymeric electro-optic material by applying an electric field across the organic polymeric electro-optic material.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: August 22, 2017
    Assignee: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM
    Inventors: Benjamin R. Lund, Samsuddin Faisal Mahmood, Naixin Yang
  • Patent number: 9721951
    Abstract: According to one embodiment, a semiconductor device includes a first complementary semiconductor device provided on a semiconductor substrate, and including a CMOS circuit, a metal electrode provided above the first complementary semiconductor device, a semiconductor layer provided above the metal electrode, including an nMOS region and a pMOS region separated from each other, and containing Ge; and a second complementary semiconductor device including an nMOSFET provided on the first portion of the semiconductor layer and a pMOSFET provided on the second portion of the semiconductor layer.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: August 1, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiji Ikeda, Tsutomu Tezuka, Yuuichi Kamimuta, Kiyoe Furuse
  • Patent number: 9721950
    Abstract: A semiconductor device including fin type patterns is provided. The semiconductor device includes a first fin type pattern, a field insulation layer disposed in vicinity of the first fin type pattern and having a first part and a second part, the first part protruding from the second part, a first dummy gate stack formed on the first part of the field insulation layer and including a first dummy gate insulation layer having a first thickness, and a first gate stack formed on the second part of the field insulation layer to intersect the first fin type pattern and including a first gate insulation layer having a second thickness different from the first thickness.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: August 1, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Gun You, Jae-Chul Kim
  • Patent number: 9679966
    Abstract: The electronic device comprises a substrate (1), at least one semiconductor nanowire (2) and a buffer layer (3) interposed between the substrate (1) and said nanowire (2). The buffer layer (3) is at least partly formed by a transition metal nitride layer (9) from which extends the nanowire (2), said transition metal nitride being chosen from: vanadium nitride, chromium nitride, zirconium nitride, niobium nitride, molybdenum nitride, hafnium nitride or tantalum nitride.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: June 13, 2017
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Berangere Hyot, Benoit Amstatt, Marie-Francoise Armand
  • Patent number: 9627266
    Abstract: A method of forming an active device on a semiconductor wafer includes the steps of: forming a plurality of semiconductor fins on at least a portion of a semiconductor substrate; forming a dielectric layer on at least a portion of the semiconductor substrate, the dielectric layer filling gaps between adjacent fins; forming a plurality of gate structures on an upper surface of the dielectric layer; forming a channel region on the dielectric layer and under at least a portion of the gate structures, the channel region comprising a first crystalline semiconductor material; forming source and drain epitaxy regions on an upper surface of the dielectric layer and between adjacent gate structures, the source and rain regions being spaced laterally from one another; and replacing the channel region with a second crystalline semiconductor material after high-temperature processing used in fabricating the active device has been completed.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: April 18, 2017
    Assignee: International Business Machines Corporation
    Inventors: Sanghoon Lee, Effendi Leobandung, Renee T. Mo, Yanning Sun
  • Patent number: 9601565
    Abstract: A semiconductor structure including: trench-defining layer; an epitaxial layer; and a set of defect-blocking member(s). The trench-defining layer includes a trench surface which defines an elongated interior space called the “trench.” The epitaxial layer is grown epitaxially in the interior space of the trench. Each defect blocking member of the set of defect blocking members: (i) extends from a portion of trench surface into the interior space of the trench; and (ii) is located below a top surface of the epitaxial layer. The defect blocking member(s) are designed to arrest the propagation of generally-longitudinal defects in the epitaxial layer, as it is grown, where the generally-longitudinal defects are defects that propagate at least generally in the elongation direction of the trench.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: March 21, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Judson R. Holt, Shogo Mochizuki, Alexander Reznicek, Melissa A. Smith
  • Patent number: 9570297
    Abstract: A method of forming a semiconductor in a long trench. The method may include; forming a first semiconductor on a substrate and in a long trench; forming a first spacer along sidewalls of the long trench and above the first semiconductor, a portion of the first semiconductor remains exposed; recessing the exposed portion of the first semiconductor; forming an insulator layer on the recessed portion of the first semiconductor; forming a second semiconductor on the insulator layer; forming a second spacer on sidewalls of the first spacer and above the second semiconductor, a portion of the second semiconductor remains exposed; removing the exposed portion of the second semiconductor; and removing a frond end and a back end of the first semiconductor and the second semiconductor, wherein the front end and back end are separated by a central region and the central region extends across the width of the long trench.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: February 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9570459
    Abstract: In an example, a device comprises a vertical stack of memory cells. Each memory cell of the vertical stack may include more than one memory element. A first vertical gate line may be coupled to a first one of the memory elements in each memory cell, and a second vertical gate line may be coupled to a second one of the memory elements in each memory cell. The first vertical gate line may be electrically isolated from the second vertical gate line.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: February 14, 2017
    Assignee: UNITY SEMICONDUCTOR CORPORATION
    Inventor: Bruce Lynn Bateman
  • Patent number: 9564428
    Abstract: A method for fabricating a semiconductor device comprises forming a first sacrificial gate stack on a substrate, depositing an insulator layer on the substrate, adjacent to the first sacrificial gate stack, removing the first sacrificial gate stack to define a first cavity, forming a first metal gate in the first cavity, and depositing a conductive metal over a portion of the substrate adjacent to the first metal gate such that the first metal gate and the conductive metal partially define a capacitor.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: February 7, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng
  • Patent number: 9346686
    Abstract: A one-pot approach for preparing ArSH capped Cu2ZnSnS4, Cu2ZnSn(S(1-x)Sex)4, Cu2SnS3, CuInS2, and CuIn(S(1-x)Sex)2 nanocrystals is provided. Examples involving reacting copper (II) acetylacetonate and indium chloride with thiourea and 2-mercapto-5-n-propylpyrimidine in the presence of an organic solvent are described. Monodispersed CuInS2, nanocrystals having a size of about 100 nm were prepared. Examples involving reacting copper (II) acetylacetonate, zinc chloride, and tin chloride with thiourea and 2-mercapto-5-n-propylpyrimidine in the presence of an organic solvent are described. Monodispersed Cu2ZnSnS4 nanocrystals having a size of about 2 nm were prepared. Nanociystals obtained were found to have excellent crystallinity, stoichiometry, and high collective photovoltaic activity without the need for postprocessing such as high temperature annihilation in a sulfur atmosphere.
    Type: Grant
    Filed: December 24, 2012
    Date of Patent: May 24, 2016
    Assignee: The University of Western Ontario
    Inventors: Zhifeng Ding, Falong Jia, Dave Love, Myong In Oh, Daniel Vaccarello, Amy Tapley
  • Patent number: 9040393
    Abstract: A method of forming a semiconductor device includes chemically cleaning a surface of a substrate to form a chemical oxide material on the surface. At least a portion of the chemical oxide material is removed at a removing rate of about 2 nanometer/minute (nm/min) or less. Thereafter, a gate dielectric layer is formed over the surface of the substrate.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: May 26, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Liang-Gi Yao, Chia-Cheng Chen, Ta-Ming Kuan, Jeff J. Xu, Clement Hsingjen Wann
  • Patent number: 9040957
    Abstract: According to example embodiments, a field effect transistor includes a graphene channel layer on a substrate. The graphene channel layer defines a slit. A source electrode and a drain electrode are spaced apart from each other and arranged to apply voltages to the graphene channel layer. A gate insulation layer is between the graphene channel layer and a gate electrode.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: May 26, 2015
    Assignees: SAMSUNG ELECTRONICS CO., LTD., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Jae-ho Lee, Seong-jun Park, Kyung-eun Byun, David Seo, Hyun-jae Song, Hyung-cheol Shin, Jae-hong Lee, Hyun-jong Chung, Jin-seong Heo
  • Patent number: 9040331
    Abstract: In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Anthony J. Lochtefeld
  • Patent number: 9041159
    Abstract: An epitaxial growth method includes the steps of: providing a substrate; forming a sacrifice layer on the substrate; patterning the sacrifice layer to form a plurality of bumps spaced apart from each other on the substrate; epitaxially forming a first epitaxial layer on the substrate to cover a portion of each of the bumps; removing the bumps to form a plurality of cavities; and epitaxially forming a second epitaxial layer on the first epitaxial layer such that the cavities are enclosed by the first epitaxial layer and the second epitaxial layer. An epitaxial structure grown by the method is disclosed as well.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: May 26, 2015
    Assignee: LEXTAR ELECTRONICS CORPORATION
    Inventors: Jun-Rong Chen, Hsiu-Mei Chou, Jhao-Cheng Ye
  • Patent number: 9040392
    Abstract: A method of removing a semiconductor device layer from a base substrate is provided that includes providing a crack propagation layer on an upper surface of a base substrate. A semiconductor device layer including at least one semiconductor device is formed on the crack propagation layer. Next, end portions of the crack propagation layer are etched to initiate a crack in the crack propagation layer. The etched crack propagation layer is then cleaved to provide a cleaved crack propagation layer portion to a surface of the semiconductor device layer and another cleaved crack propagation layer portion to the upper surface of the base substrate. The cleaved crack propagation layer portion is removed from the surface of the semiconductor device layer and the another cleaved crack propagation layer portion is removed from the upper surface of the base substrate.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: May 26, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Cheng-Wei Cheng, Devendra K. Sadana, Kuen-Ting Shiu, Norma E. Sosa Cortes
  • Patent number: 9041137
    Abstract: A light emitting diode includes a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode, a second electrode. The second electrode includes a treated patterned carbon nanotube film. The treated patterned carbon nanotube film includes at least two carbon nanotube linear units spaced from each other; and carbon nanotube groups spaced from each other. The carbon nanotube groups are located between the at least two carbon nanotube linear units, and combined with the at least two carbon nanotube linear units.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: May 26, 2015
    Assignee: Beijing FUNATE Innovation Technology Co., LTD.
    Inventors: Chen Feng, Li Qian, Yu-Quan Wang
  • Patent number: 9041138
    Abstract: An organic light emitting diode includes a substrate, a first electrode, an organic functional layer; and a second electrode. One of the first electrode and the second electrode includes a treated patterned carbon nanotube film. The treated patterned carbon nanotube film includes at least two carbon nanotube linear units spaced from each other; and carbon nanotube groups spaced from each other. The carbon nanotube groups are located between the at least two carbon nanotube linear units, and combined with the at least two carbon nanotube linear units.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: May 26, 2015
    Assignee: Beijing FUNATE Innovation Technology Co., LTD.
    Inventors: Chen Feng, Yu-Quan Wang, Li Qian
  • Patent number: 9034676
    Abstract: The present invention provides a method of fabricating a vertical type light-emitting diode and a method of separating layers from each other. Crystalline rods are provided on a lower layer or a lower substrate. The crystalline rods comprise ZnO. A layer which constitutes light-emitting diode or a light-emitting diode structure is formed on the crystalline rods, and the lower substrate is separated therefrom. The crystalline rods are dissolved during the separation. The formation of the crystalline rods is achieved by the formation of a seed layer and selective growth based on the seed layer.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: May 19, 2015
    Assignee: GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Ki-Seok Kim, Gun-Young Jung
  • Patent number: 9034737
    Abstract: Approaches for enabling epitaxial growth of silicon fins in a device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming a set of silicon fins for a FinFET device, the FinFET device comprising: a set of gate structures formed over a substrate, each of the set of gate structures including a capping layer and a set of spacers; an oxide fill formed over the set of gate structures; a set of openings formed in the device by removing the capping layer and the set of spacers from one or more of the set of gate structures; a silicon material epitaxially grown within the set of openings in the device and then planarized; and wherein the oxide fill is etched to expose the silicon material and form the set of fins.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: May 19, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Johannes M. van Meer, Michael J. Hargrove, Christian Gruensfelder, Yanxiang Liu, Srikanth B. Samavedam
  • Patent number: 9029911
    Abstract: Disclosed are a light emitting device, a method of manufacturing the light emitting device, a light emitting device package and a lighting system. The light emitting device includes a silicon substrate; a nitride buffer layer on the silicon substrate; and a gallium nitride epitaxial layer on the nitride buffer layer, wherein the nitride buffer layer includes a first nitride buffer layer having a first aluminum nitride layer on the silicon substrate and a first gallium nitride layer on the first aluminum nitride layer.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: May 12, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventors: Jung Hun Jang, Jeong Sik Lee, Seung Keun Nam
  • Patent number: 9023718
    Abstract: A method of fabricating a semiconductor device includes: forming an epitaxial layer on a semiconductor substrate; forming a capping layer having a first thickness on the epitaxial layer; and oxidizing the capping layer in an oxygen atmosphere to form a first gate dielectric layer having a second thickness.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: May 5, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Ho Do, Ha-Jin Lim, Weon-Hong Kim, Hoi-Sung Chung, Moon-Kyun Song, Dae-Kwon Joo
  • Patent number: 9023673
    Abstract: A method to grow single phase group III-nitride articles including films, templates, free-standing substrates, and bulk crystals grown in semi-polar and non-polar orientations is disclosed. One or more steps in the growth process includes the use of additional free hydrogen chloride to eliminate undesirable phases, reduce surface roughness, and increase crystalline quality. The invention is particularly well-suited to the production of single crystal (11.2) GaN articles that have particular use in visible light emitting devices.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: May 5, 2015
    Assignee: Ostendo Technologies, Inc.
    Inventors: Lisa Shapovalov, Oleg Kovalenkov, Vladimir Ivantsov, Vitali Soukhoveev, Alexander Syrkin, Alexander Usikov
  • Patent number: 9018626
    Abstract: Disclosed herein are a ZnO film structure and a method of forming the same. Dislocation density of a ZnO film grown through epitaxial lateral overgrowth (ELOG) is minimized. In order to block a chemical reaction between the ZnO film and a mask layer at the time of performing the ELOG, a material of the mask layer is AlF3, NaF2, SrF, or MgF2. Therefore, the chemical reaction between ZnO and the mask layer is blocked and a transfer of dislocation from a substrate is also blocked.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: April 28, 2015
    Assignee: Gwangju Institute of Science and Technology
    Inventors: Seong-Ju Park, Yong Seok Choi, Jang-Won Kang, Byeong Hyeok Kim
  • Patent number: 9012292
    Abstract: A method for fabricating semiconductor memory device, includes providing a semiconductor substrate; forming a lower region which includes a first data storage device, which is carried by the semiconductor substrate; forming a switching device which is carried by the first data storage device; and forming an upper region which includes a second data storage device, which is carried by the switching device. The step of forming the first storage device includes forming a first electrode having a cylindrical or pillar shape, the first electrode being connected to the switching device.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: April 21, 2015
    Inventor: Sang-Yun Lee
  • Patent number: 9012306
    Abstract: The invention relates to a method for manufacturing a single crystal of nitride by epitaxial growth on a support (100) comprising a growth face (105), the method comprising the steps of formation of a sacrificial bed (101) on the support (100), formation of pillars (102) on said sacrificial bed, said pillars being made of a material compatible with GaN epitaxial growth, growth of a nitride crystal layer (103) on the pillars, under growing conditions such that the nitride crystal layer does not extend down to the support in holes (107) formed between the pillars, and removing the nitride crystal layer from the support.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: April 21, 2015
    Assignee: Saint-Gobain Cristaux et Detecteurs
    Inventors: Bernard Beaumont, Jean-Pierre Faurie
  • Patent number: 9006706
    Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, a light emitting layer, a first intermediate layer, and a second intermediate layer. The n-type and p-type semiconductor layers include a nitride semiconductor. The light emitting layer is provided between the n-type and p-type semiconductor layers, and includes barrier layers and a well layer. A bandgap energy of the well layer is less than that of the barrier layers. The first intermediate layer is provided between the light emitting layer and the p-type semiconductor layer. A bandgap energy of the first intermediate layer is greater than that of the barrier layers. The second intermediate layer includes first and second portions. The first portion is in contact with a p-side barrier layer most proximal to the p-type semiconductor layer. The second portion is in contact with the first intermediate layer.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: April 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hung Hung, Yoshiyuki Harada, Jongil Hwang, Mitsuhiro Kushibe, Naoharu Sugiyama, Shinya Nunoue
  • Patent number: 9000449
    Abstract: A semiconductor substrate that includes a semiconductor layer that exhibits high crystallinity includes a graphite layer formed of a heterocyclic polymer obtained by condensing an aromatic tetracarboxylic acid and an aromatic tetramine, and a semiconductor layer that is grown on the surface of the graphite layer, or includes a substrate that includes a graphite layer formed of a heterocyclic polymer obtained by condensing an aromatic tetracarboxylic acid and an aromatic tetramine on its surface, a buffer layer that is grown on the surface of the graphite layer, and a semiconductor layer that is grown on the surface of the buffer layer.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: April 7, 2015
    Assignees: The University of Tokyo, Tokai Carbon Co., Ltd., National Institute of Advanced Industrial Science and Technology
    Inventors: Hiroshi Fujioka, Tetsuro Hirasaki, Hitoshi Ue, Junya Yamashita, Hiroaki Hatori
  • Patent number: 8993403
    Abstract: The present invention provides a socket by which a capacitor element can be produced without causing contamination of chemical conversion treatment liquid or semiconductor layer forming liquid even if the chemical conversion treatment liquid or the semiconductor layer forming liquid has a corrosive property, and a lead wire of a positive electrode can be stably retained even if diameters of the lead wires are difference. The socket (1) of the present invention is provided with a conductive socket body portion (2) having an insertion port, a resin insulation portion (5) covering a part of the socket body portion (2) so as not to close an insertion port (37), and a resin coating portion (3) coating at least the insertion portion (37) of the socket body portion (2).
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: March 31, 2015
    Assignee: Showa Denko K.K.
    Inventor: Kazumi Naito
  • Patent number: 8993441
    Abstract: A method of forming a thin layer and a method of manufacturing a phase change memory device, the method of forming a thin layer including providing a first deposition source onto a substrate, the first deposition source not including tellurium; and providing a second deposition source onto the substrate, the second deposition source including a first tellurium precursor represented by the following Formula 1 and a second tellurium precursor represented by following the Formula 2: Te(CH(CH3)2)2??Formula 1 Ten(CH(CH3)2)2??Formula 2 wherein, in Formula 2, n is an integer greater than or equal to 2.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: March 31, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Do-Hyung Kim, Eun-Tae Kim, Sung-Lae Cho