IN-SITU DEPOSITED MASK LAYER FOR DEVICE SINGULATION BY LASER SCRIBING AND PLASMA ETCH
Methods of dicing substrates by both laser scribing and plasma etching. A method includes forming an in-situ mask with a plasma etch chamber by accumulating a thickness of plasma deposited polymer to protect IC bump surfaces from a subsequent plasma etch. Second mask materials, such as a water soluble mask material may be utilized along with the plasma deposited polymer. At least some portion of the mask is patterned with a femtosecond laser scribing process to provide a patterned mask with trenches. The patterning exposing regions of the substrate between the ICs in which the substrate is plasma etched to singulate the IC and the water soluble material layer washed off.
This is a Divisional application of Ser. No. 13/160,973 filed Jun. 15, 2011, which is presently pending.TECHNICAL FIELD
Embodiments of the present invention pertain to the field of semiconductor processing and, in particular, to masking methods for dicing substrates, each substrate having an integrated circuit (IC) thereon.BACKGROUND DESCRIPTION OF RELATED ART
In semiconductor substrate processing, ICs are formed on a substrate (also referred to as a wafer), typically composed of silicon or other semiconductor material. In general, thin film layers of various materials which are either semiconducting, conducting or insulating are utilized to form the ICs. These materials are doped, deposited and etched using various well-known processes to simultaneously form a plurality of ICs, such as memory devices, logic devices, photovoltaic devices, etc, in parallel on a same substrate.
Following device formation, the substrate is mounted on a supporting member such as an adhesive film stretched across a film frame and the substrate is “diced” to separate each individual device or “die” from one another for packaging, etc. Currently, the two most popular dicing techniques are scribing and sawing. For scribing, a diamond tipped scribe is moved across a substrate surface along pre-formed scribe lines. Upon the application of pressure, such as with a roller, the substrate separates along the scribe lines. For sawing, a diamond tipped saw cuts the substrate along the streets. For thin substrate singulation, such as 50-150 μms (μm) thick bulk silicon singulation, the conventional approaches have yielded only poor process quality. Some of the challenges that may be faced when singulating die from thin substrates may include microcrack formation or delamination between different layers, chipping of inorganic dielectric layers, retention of strict kerf width control, or precise ablation depth control.
While plasma dicing has also been contemplated, a standard lithography operation for patterning resist may render implementation cost prohibitive. Another limitation possibly hampering implementation of plasma dicing is that plasma processing of commonly encountered metals (e.g., copper) in dicing along streets can create production issues or throughput limits. Finally, masking of the plasma dicing process may be problematic, depending on, inter alia, the thickness and top surface topography of the substrate, the selectivity of the plasma etch, and the materials present on the top surface of the substrate.SUMMARY
Embodiments of the present invention include methods of masking semiconductor substrates for a hybrid dicing process including both laser scribing and plasma etching.
In an embodiment, a method of dicing a semiconductor substrate having a plurality of ICs includes forming a mask over the semiconductor substrate, the mask including a plasma deposited material covering and protecting the ICs. At least a portion of the mask thickness in the street is patterned with a laser scribing process to provide a patterned mask with gaps or trenches, exposing regions of the substrate between the ICs. The substrate is then plasma etched through the gaps in the patterned mask to singulate the ICs into chips.
In another embodiment, a system for dicing a semiconductor substrate includes a femtosecond laser and a plasma etch chamber, coupled to a same platform. The plasma etch chamber is utilized both for plasma etching of the substrate and for in-situ deposition of a polymeric masking material.
In another embodiment, a method of dicing a substrate having a plurality of ICs includes forming a water soluble mask layer over a front side of a silicon substrate. The water soluble mask layer covers and protects a majority of IC surfaces disposed on the front side of the substrate. The ICs include a copper bumped top surface having bumps surrounded by a passivation layer, such as polyimide (PI). Subsurface thin films below the bumps and passivation include a low-K interlayer dielectric (ILD) layer and a layer of copper interconnect. The water soluble material, the passivation layer, and subsurface thin films are patterned with a femtosecond laser scribing process to expose regions of the silicon substrate between the ICs. The water soluble material thickness is augmented with a polymeric mask material plasma deposited prior to the plasma etch in-situ with the etch chamber that is to perform the substrate etch. The silicon substrate is etched through with a deep silicon plasma etch process to singulate the ICs. The water soluble layer and in-situ deposited polymeric mask materials are then washed off in water or other solvent suitable for removal of etch polymer residue.
Embodiments of the present invention are illustrated by way of example, and not limitation, in the figures of the accompanying drawings in which:
Methods of dicing substrates, each substrate having a plurality of ICs thereon, are described. In the following description, numerous specific details are set forth, such as femtosecond laser scribing and deep silicon plasma etching conditions in order to describe exemplary embodiments of the present invention. However, it will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known aspects, such as IC fabrication, substrate thinning, taping, etc., are not described in detail to avoid unnecessarily obscuring embodiments of the present invention. Reference throughout this specification to “an embodiment” means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase “in an embodiment” in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments. Also, it is to be understood that the various exemplary embodiments shown in the Figures are merely illustrative representations and are not necessarily drawn to scale.
The terms “coupled” and “connected,” along with their derivatives, may be used herein to describe structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” my be used to indicate that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship).
The terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one material layer with respect to other material layers. As such, for example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer “on” a second layer is in contact with that second layer. Additionally, the relative position of one layer with respect to other layers is provided assuming operations are performed relative to a substrate without consideration of the absolute orientation of the substrate.
Generally, described herein is a hybrid substrate or substrate dicing process involving an initial laser scribe and subsequent plasma etch for die singulation is implemented with an etch mask including a plasma deposited material layer. For certain embodiments where plasma deposition of the mask layer and plasma etching of the substrate for singulation is performed by/occurs within a same plasma chamber, plasma deposition of the mask layer is referred to herein as “in-situ” while mask materials not form by the plasma etch chamber are referred to herein as “ex-situ.” The laser scribe process may be used to cleanly remove at least a partial thickness of an unpatterned (i.e., blanket) mask layer, a passivation layer, and subsurface thin film device layers. The laser etch process may then be terminated upon exposure of, or partial ablation of, the substrate. The plasma etch portion of the hybrid dicing process may then be employed to etch through the bulk of the substrate, such as through bulk single crystalline silicon, for singulation or dicing of chips.
In accordance with an embodiment of the present invention, a combination of femtosecond laser scribing and plasma etching is used to dice a semiconductor substrate into individualized or singulated ICs. In one embodiment, femtosecond laser scribing is an essentially, if not completely, non-equilibrium process. For example, the femtosecond-based laser scribing may be localized with a negligible thermal damage zone. In an embodiment, laser scribing is used to singulated ICs having ultra-low κ films (i.e., with a dielectric constant below 3.0). In one embodiment, direct writing with laser eliminates a lithography patterning operation, allowing the masking material to be non-photosensitive, and a plasma etch-based dicing processing implemented with very little cost to partition the substrate. In one embodiment, through silicon via (TSV)-type etching is used to complete the dicing process in a plasma etch chamber; the TSV-type etch depositing on sidewalls of the trench substantially the same material plasma deposited on a topside of the ICs to as the etch mask.
Method 100 begins with receipt of a substrate with ICs formed thereon. Referring to
In embodiments, first and second ICs 425, 426 include memory devices or complimentary metal-oxide-semiconductor (CMOS) transistors fabricated in a silicon substrate 406 and encased in a dielectric stack. A plurality of metal interconnects may be formed above the devices or transistors, and in surrounding dielectric layers, and may be used to electrically couple the devices or transistors to form the ICs 425, 426. Materials making up the street 427 may be similar to or the same as those materials used to form the ICs 425, 426. For example, street 427 may include thin film layers of dielectric materials, semiconductor materials, and metallization. In one embodiment, the street 427 includes a test device similar to the ICs 425, 426. The width of the street 427 may be anywhere between 10 μm and 100 μm.
At operation 102, a mask 402 including a plasma deposited layer is formed over substrate 406, covering both the ICs 425, 426 and intervening street 427 between the ICs 425, 426. In an embodiment, forming the mask 402 includes plasma depositing a polymer over the substrate. For certain in-situ embodiments, where the plasma etch is to be a deep trench etch process having a plurality of successive etch and deposition cycles, each deposition cycle during the etch operation 105 deposits an additional amount of substantially the same polymer formed during the masking operation 102. However, whereas a typical deep trench etch process is performed with a lithographically defined photo resist mask and does not dynamically accumulate polymer on non-vertical (e.g., horizontal) surfaces during etch, the plasma deposition at operation 102 is to replace a photo resist mask and therefore is performed for a sufficient duration prior to commencement of substrate etching so as to accumulate a polymer protection layer over horizontal surfaces (e.g., top surfaces) of the ICs 425, 426.
Depending on the embodiment, the mask 402 either consists only of the plasma deposited polymer layer formed at operation 102 or, as illustrated by the dashed line in
In one multi-layered mask embodiment where the method 100 includes ex-situ mask formation operation 101, the mask 402 includes a water soluble material disposed over the ICs 425, 426. For such embodiments, the water soluble material may be applied before or after plasma deposition of the polymeric material, to be disposed below or above the plasma deposited polymer layer formed at operation 102, respectively. Therefore, in reference to
In an embodiment, the water soluble mask layer is thermally stable to at least 60° C., preferably stable at 100° C., and ideally stable to 120° C. to avoid excessive crosslinking during the subsequent plasma etch process when the material's temperature will be elevated. Generally, excessive crosslinking adversely affects the solubility of the material, making post-etch removal more difficult. Depending on the embodiment, the water soluble layer may be either wet applied or applied as a dry film laminate. For either mode of application, exemplary materials include, at least one of: poly(vinyl alcohol), poly(acrylic acid), poly(methacrylic acid), poly(acrylamide), or poly(ethylene oxide) with many other water soluble materials also readily available. Dry films for lamination may include the water soluble material only or may further include an adhesive layer that may also be water soluble or not. In a particular embodiment, the dry film includes a UV sensitive adhesive layer which has reduced adhesive bond strength upon UV exposure. Such UV exposure may occur during the subsequent plasma street etch.
The maximum thickness of the mask 402 in the street, Tmax, is generally a function of the laser power and optical conversion efficiency associated with laser wavelength. As Tmax is associated with the street 427, street feature topography, street width, and the method of applying the water soluble layer may be designed to achieve a desired Tmax. In particular embodiments, the mask 402 has a street thickness Tmax less than 30 μm and advantageously less than 20 μm with a thicker etch mask calling for multiple laser passes.
The minimum thickness of the mask 402 is a function of the selectivity achieved by the subsequent plasma etch (e.g., operation 105 in
For embodiments where spin coating of the water soluble layer (
Continuing with the spin coating method 200, at operation 208 the aqueous solution is dried, for example on a hot plate. The drying temperature and time should be selected to avoid excessive crosslinking which may render subsequent mask removal difficult. Exemplary drying temperatures range from 60° C. to 150° C. depending on the material. For example, PVA was found to remain soluble at 60° C. while becoming more insoluble as the temperature approached the 150° C. limit of the range. Completing spin coating method 200, the substrate is unloaded or transferred in-vaccuo to a plasma etch chamber for in-situ plasma deposition of the second mask material or to a laser scribe module (returning to method 100 illustrated in
As the polymer deposition is performed within an etch chamber, the substrate temperature and more specifically any water soluble layer disposed on the substrate can be maintained at sufficiently low temperatures to retain water solubility of the water soluble material. In the exemplary embodiment, cooling power is applied during plasma deposition of polymer at operation 102 via an electrostatic chuck (ESC) chilled to −10° C. to −15° C. to maintain the water soluble mask material layer at a temperature below 100° C. and preferably between 70° C. and 80° C. throughout the duration of the plasma deposition process.
Generally, the plasma deposited polymer will provide an etch selectivity of between 1:20 and 1:30 (polymer:substrate). In comparison, to achieve similar etch resistance with photoresist for example, a hard bake at a temperature over 150° C. may be necessary and such a high bake temperature would be disadvantageous for embodiments employing a water soluble layer (e.g., causing excessive crosslinking) in contact with the ICs 425, 426. As such, the minimum thickness over a top bump surface of an IC (e.g., Tmin in
For the method 100, the mask 402, including the plasma deposited layer, is unpatterned prior to the laser scribing operation 103 with the laser scribe to perform a direct writing of the scribe lines by ablating portions of the mask 402 (e.g., water soluble layer 402A and plasma deposited layer 402B) disposed over the street 427. At operation 103 of method 100, and corresponding
In the exemplary embodiment illustrated in
In an embodiment, the mask 402 is patterned with a laser having a pulse width (duration) in the femtosecond range (i.e., 10−15 seconds), referred to herein as a femtosecond laser. Laser parameters selection, such as pulse width, may be critical to developing a successful laser scribing and dicing process that minimizes chipping, microcracks and delamination in order to achieve clean laser scribe cuts. A laser pulse width in the femtosecond range advantageously mitigates heat damage issues relative longer pulse widths (e.g., picosecond or nanosecond). Although not bound by theory, as currently understood a femtosecond energy source avoids low energy recoupling mechanisms present for picosecond sources and provides for greater thermal nonequilibrium than does a nanosecond-source. With nanosecond or picoseconds laser sources, the various thin film device layer materials present in the street 427 behave quite differently in terms of optical absorption and ablation mechanisms. For example, dielectrics layers such as silicon dioxide, is essentially transparent to all commercially available laser wavelengths under normal conditions. By contrast, metals, organics (e.g., low-κ materials) and silicon can couple photons very easily, particularly nanosecond-based or picosecond-based laser irradiation. If non-optimal laser parameters are selected, in a stacked structures that involve two or more of an inorganic dielectric, an organic dielectric, a semiconductor, or a metal, laser irradiation of the street 427 may disadvantageously cause delamination. For example, a laser penetrating through high bandgap energy dielectrics (such as silicon dioxide with an approximately of 9 eV bandgap) without measurable absorption may be absorbed in an underlying metal or silicon layer, causing significant vaporization of the metal or silicon layers. The vaporization may generate high pressures potentially causing severe interlayer delamination and microcracking. Femtosecond-based laser irradiation processes have been demonstrated to avoid or mitigate such microcracking or delamination of such material stacks.
Parameters for a femtosecond laser-based process may be selected to have substantially the same ablation characteristics for the inorganic and organic dielectrics, metals, and semiconductors. For example, the absorptivity/absorptance of silicon dioxide is non-linear and may be brought more in-line with that of organic dielectrics, semiconductors and metals. In one embodiment, a high intensity and short pulse width femtosecond-based laser process is used to ablate a stack of thin film layers including a silicon dioxide layer and one or more of an organic dielectric, a semiconductor, or a metal. In accordance with an embodiment of the present invention, suitable femtosecond-based laser processes are characterized by a high peak intensity (irradiance) that usually leads to nonlinear interactions in various materials. In one such embodiment, the femtosecond laser sources have a pulse width approximately in the range of 50 femtoseconds to 500 femtoseconds, although preferably in the range of 100 femtoseconds to 400 femtoseconds.
In certain embodiments, the laser emission spans any combination of the visible spectrum, the ultra-violet (UV), and/or infra-red (IR) spectrums for a broad or narrow band optical emission spectrum. Even for femtosecond laser ablation, certain wavelengths may provide better performance than others. For example, in one embodiment, a femtosecond-based laser process having a wavelength closer to or in the UV range provides a cleaner ablation process than a femtosecond-based laser process having a wavelength closer to or in the IR range. In a specific embodiment, a femtosecond laser suitable for semiconductor substrate or substrate scribing is based on a laser having a wavelength of approximately between 1570-200 nanometers although preferably in the range of 540 nanometers to 250 nanometers. In a particular embodiment, pulse widths are less than or equal to 500 femtoseconds for a laser having a wavelength less than or equal to 540 nanometers. However, in an alternative embodiment, dual laser wavelengths (e.g., a combination of an IR laser and a UV laser) are used.
In one embodiment, the laser and associated optical pathway provide a focal spot at the work surface approximately in the range of 3 μm to 15 μm, though advantageously in the range of 5 μm to 10 μm. The spatial beam profile at the work surface may be a single mode (Gaussian) or have a beam shaped top-hat profile. In an embodiment, the laser source has a pulse repetition rate approximately in the range of 200 kHz to 10 MHz, although preferably approximately in the range of 500 kHz to 5 MHz In an embodiment, the laser source delivers pulse energy at the work surface approximately in the range of 0.5 μJ to 100 μJ, although preferably approximately in the range of 1 μJ to 5 μJ. In an embodiment, the laser scribing process runs along a work piece surface at a speed approximately in the range of 300 mm/sec to 5 m/sec, although preferably approximately in the range of 600 mm/sec to 2 m/sec.
The scribing process may be run in single pass only, or in multiple passes, but is advantageously no more than two passes. The laser may be applied either in a train of single pulses at a given pulse repetition rate or a train of pulse bursts. In an embodiment, the kerf width of the laser beam generated is approximately in the range of 2 μM to 15 μm, although in silicon substrate scribing/dicing preferably approximately in the range of 6 μm to 10 μm, as measured at a device/silicon interface.
In one embodiment, the etch operation 105 entails a through via etch process. For example, in a specific embodiment, the etch rate of the material of substrate 406 is greater than 25 μms per minute. A high-density plasma source operating at high powers may be used for the plasma etching operation 105. Exemplary powers range between 3 kW and 6 kW, or more.
In an exemplary embodiment, a deep silicon etch (i.e., such as a through silicon via (TSV) etch) is used to etch a single crystalline silicon substrate or substrate 406 at an etch rate greater than approximately 40% of conventional silicon etch rates while maintaining essentially precise profile control and virtually scallop-free sidewalls. Effects of the high power on any water soluble material layer present in the mask 402 are controlled through application of cooling power via an electrostatic chuck (ESC) chilled to −10° C. to −15° C. to maintain the water soluble mask material layer at a temperature below 100° C. and preferably between 70° C. and 80° C. throughout the duration of the plasma etch process. At such temperatures, water solubility is advantageously maintained.
In a specific embodiment, the plasma etch operation 105 further entails a plurality of protective polymer deposition cycles interleaved over time with a plurality of etch cycles. The deposition time to etch time ratio is typically 1:1 to 1:1.4. For example, the etch process may have a deposition cycle with a duration of 250 ms-750 ms and an etch cycle of 250 ms-750 ms. As illustrated in
At operation 107, method 300 is completed with removal of the mask 402, including the in-situ deposited layer. In an embodiment, a water soluble mask layer is washed off with water, for example with a pressurized jet of de-ionized water or through submergence in an ambient or heated water bath. In alternative embodiments, the mask 402 may be washed off with aqueous solvent solutions known in the art to be effective for etch polymer removal. As further illustrated in
In the exemplary embodiment illustrated by
The aspect ratio (AR) of the scribed trench is laser scribed depth DL divided by the width of trench 412. For the exemplary embodiments with trench widths between 6 μm to 10 μm, the AR may be anywhere between 1.5:1 and 5:1. Proceeding with
Proceeding with method 150, at operation 105 the substrate is plasma etched (e.g., in the same chamber which performed the mask deposition operation 102) first with a polymer breakthrough to clear the polymer deposited in the scribed trench (without clearing the thicker polymer layer deposited outside of the trench) and second with a substrate etch employing any of the techniques and conditions described elsewhere herein for the method 100. In an embodiment, the polymer breakthrough step entails a higher bias power than utilized during the main etch/dep sequenced anisotropic etch process.
The substrate etch operation 105 generally employs an iterative or cyclic dep/etch process (e.g., same source gases) similar to those described in the context of the methods 100 and 150. However in one embodiment of method 190, the operation 105 leads off with a deposition cycle (rather than an etch cycle). In a further embodiment, the ratio of deposition time to etch time is relatively higher (e.g., dep time:etch time ratio is greater than 1:1 and more particularly between 1.2:1 and 2:1). For example, in one exemplary embodiment where deposition time is 400-500 ms and etch time is 300 ms, a water soluble mask with only a 2 μm Tmin over the copper bump 512 may survive an etch with a depth DE of 100 μm (e.g., 50:1 selectivity). Also, in the cyclic dep/etch process, each etch step is typically partitioned into two sub-steps, with the first sub etch step being directional etch to etch the deposited polymer and silicon on the trench bottom by applying 100-200 W bias power, and the second sub etch step being isotropic etch to etch polymer and silicon isotropically with no bias power being applied. At the fixed time ratio of deposition to etch, the ratio of the first sub etch step time to the second sub etch step time can be also adjusted to better control the consumption of mask layer on top of wafer surface.
It should also be noted that for mask embodiments including a water soluble layer, the spin coating method 200 may be performed prior to, or subsequent to, a backside grind (BSG). As spin coating is generally an accomplished technique for substrates having a conventional thickness of 750 μm the spin coating method 200 may be advantageously performed prior to backside grind. However, in the alternative, the spin coating method 200 is performed subsequent to the backside grind, for example by supporting both the thin substrate and taped frame upon a rotatable chuck.
A single process tool 600 may be configured to perform many or all of the operations in the hybrid laser ablation-plasma etch singulation process 100. For example,
A laser scribe apparatus 610 is also coupled to the FI 602. In an embodiment, the laser scribe apparatus 610 includes a femtosecond laser. The femtosecond laser to performing the laser ablation portion of the hybrid laser and etch singulation process 100. In one embodiment, a moveable stage is also included in laser scribe apparatus 610, the moveable stage configured for moving a substrate or substrate (or a carrier thereof) relative to the femtosecond-based laser. In a specific embodiment, the femtosecond laser is also moveable.
The cluster tool 606 includes one or more plasma etch chambers 608 coupled to the FI by a robotic transfer chamber 650 housing a robotic arm for in-vaccuo transfer of substrates. The plasma etch chambers 608 is suitable for both the plasma etch portion of the hybrid laser and etch singulation process 100 and to deposit a polymer mask over the substrate. In one exemplary embodiment, the plasma etch chamber 608 is further coupled to an SF6 gas source and at least one of a C4F8, C4F6, or CH2F2 source. In a specific embodiment, the one or more plasma etch chambers 608 is an Applied Centura® Silvia™ Etch system, available from Applied Materials of Sunnyvale, Calif., USA, although other suitable etch systems are also available commercially. In an embodiment, more than one plasma etch chamber 608 is included in the cluster tool 606 portion of integrated platform 600 to enable high manufacturing throughput of the singulation or dicing process.
The cluster tool 606 may include other chambers suitable for performing functions in the hybrid laser ablation-plasma etch singulation process 100. In the exemplary embodiment illustrated in
In still other embodiments, the deposition module 612 is a spin coating module for application of the water soluble mask layer described herein. As a spin coating module, the deposition module 612 may include a rotatable chuck adapted to clamp by vacuum, or otherwise, a thinned substrate mounted on a carrier such as backing tape mounted on a frame.
Processor 702 represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processor 702 may be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, etc. Processor 702 may also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. Processor 702 is configured to execute the processing logic 726 for performing the operations and steps discussed herein.
The computer system 700 may further include a network interface device 708. The computer system 700 also may include a video display unit 710 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT), an alphanumeric input device 712 (e.g., a keyboard), a cursor control device 714 (e.g., a mouse), and a signal generation device 716 (e.g., a speaker).
The secondary memory 718 may include a machine-accessible storage medium (or more specifically a computer-readable storage medium) 731 on which is stored one or more sets of instructions (e.g., software 722) embodying any one or more of the methodologies or functions described herein. The software 722 may also reside, completely or at least partially, within the main memory 704 and/or within the processor 702 during execution thereof by the computer system 700, the main memory 704 and the processor 702 also constituting machine-readable storage media. The software 722 may further be transmitted or received over a network 720 via the network interface device 708.
The machine-accessible storage medium 731 may also be used to store pattern recognition algorithms, artifact shape data, artifact positional data, or particle sparkle data. While the machine-accessible storage medium 731 is shown in an exemplary embodiment to be a single medium, the term “machine-readable storage medium” should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term “machine-readable storage medium” shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present invention. The term “machine-readable storage medium” shall accordingly be taken to include, but not be limited to, solid-state memories, and optical and magnetic media.
Thus, methods of dicing semiconductor substrates, each substrate having a plurality of ICs, have been disclosed. The above description of illustrative embodiments of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific implementations of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. The scope of the invention is therefore to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.
1. A system for dicing a semiconductor substrate comprising a plurality of ICs, the system comprising:
- a laser scribe module to pattern a mask and expose regions of a substrate between the ICs, the mask comprising a layer of water soluble material;
- a plasma etch module physically coupled to the laser scribe module, the plasma etch module to plasma deposit a polymer mask over the substrate and to singulate the ICs by plasma etching of the substrate; and
- a robotic transfer chamber to transfer a laser scribed substrate between the laser scribe module and the plasma etch module.
2. The system of claim 1, wherein the laser scribe comprises a femtosecond laser having a wavelength less than or equal to 540 nanometers and a pulse width of less than or equal to 400 femtoseconds.
Filed: Nov 5, 2013
Publication Date: Mar 6, 2014
Inventors: Madhava Rao Yalamanchili (Morgan Hill, CA), Wei-Sheng Lei (San Jose, CA), Brad Eaton (Menlo Park, CA), Saravjeet Singh (Santa Clara, CA), Ajay Kumar (Cupertino, CA), Banqiu Wu (Sunnyvale, CA)
Application Number: 14/072,653
International Classification: H01L 21/78 (20060101);