TRENCH GATE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR AND FABRICATING METHOD THEREOF
A trench gate metal oxide semiconductor field effect transistor includes a substrate and a gate. The substrate has a trench. The trench is extended downwardly from a surface of the substrate. The gate includes an insertion portion and a symmetrical protrusion portion. The insertion portion is embedded in the trench. The symmetrical protrusion portion is symmetrically protruded over the surface of the substrate.
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The present invention relates to a semiconductor device and a fabricating method thereof, and more particularly to a trench gate metal oxide semiconductor field effect transistor and a fabricating method thereof.
BACKGROUND OF THE INVENTIONA conventional trench gate metal oxide semiconductor field effect transistor comprises a gate structure, which is disposed within a trench. For fabricating the conventional trench gate metal oxide semiconductor field effect transistor, a trench is firstly formed in a semiconductor substrate, and then a gate dielectric layer is formed on a sidewall of the trench by thermal oxidation. Then, a polysilicon semiconductor material is filled into the trench. After a planarization process is performed, a polysilicon gate is formed in the trench.
Recently, since the integrated circuit becomes more complicated, the feature size and wiring space of the semiconductor device are gradually decreased, and the size of the polysilicon gate is reduced. After the polysilicon gate is formed, a metal contact plug is formed on the polysilicon gate in the subsequent process. As known, the size reduction of the polysilicon gate may result in misalignment between the polysilicon gate and the metal contact plug. If the metal contact plug is deviated because of misalignment, the metal contact plug and the neighboring circuits may be suffered from charge breakdown.
Therefore, there is a need of providing an improved trench gate metal oxide semiconductor field effect transistor and a fabricating method thereof in order to obviate the drawbacks encountered from the prior art.
SUMMARY OF THE INVENTIONIn accordance with an aspect, the present invention provides a trench gate metal oxide semiconductor field effect transistor. The trench gate metal oxide semiconductor field effect transistor includes a substrate and a gate. The substrate has a trench. The trench is extended downwardly from a surface of the substrate. The gate includes an insertion portion and a symmetrical protrusion portion. The insertion portion is embedded in the trench. The symmetrical protrusion portion is symmetrically protruded over the surface of the substrate.
In an embodiment, the symmetrical protrusion portion is wider than the trench.
In an embodiment, the gate is a T-shaped gate, which is symmetrical with respect to a central line of the trench.
In an embodiment, the trench has a width smaller than or equal to 0.8 μm and a depth of about 1.6 μm.
In an embodiment, the trench gate metal oxide semiconductor field effect transistor includes a dielectric material layer and a contact plug. The dielectric material layer is disposed over the surface of the substrate and the gate. The contact plug is penetrated through the dielectric material layer and electrically contacted with the symmetrical protrusion portion of the gate.
In an embodiment, the trench gate metal oxide semiconductor field effect transistor includes a first-conductive doped region, a second-conductive doped region, a gate dielectric layer, and a source region. The first-conductive doped region is formed in the substrate. The second-conductive doped region is formed in the substrate. A P/N junction is formed between the first-conductive doped region and the second-conductive doped region. The trench is extended downwardly from the surface of the trench, penetrated through the first-conductive doped region and the P/N junction, and inserted into the second-conductive doped region. The gate dielectric layer is formed on a sidewall of the trench. The source region is formed in the substrate and located beside the gate dielectric layer.
In an embodiment, the first-conductive doped region is a P-type body region, and the second-conductive doped region is an N-type well region.
In an embodiment, the trench gate metal oxide semiconductor field effect transistor further includes an N-type buried layer, which is disposed under the second-conductive doped region.
In an embodiment, the source region is an N-type well region, and the source region is extended from the surface of the substrate into the first-conductive doped region.
In accordance with an aspect, the present invention provides a method for fabricating a trench gate metal oxide semiconductor field effect transistor. The method includes the following steps. Firstly, a substrate is provided. Then, a hard mask layer is formed on the substrate. Then, an etching process is performed to remove a part of the hard mask layer and form a trench in the substrate. Then, an etching back process is performed to remove a part of the hard mask layer. Then, a conductive layer is formed on the hard mask layer and filled into the trench. Then, a planarization process is performed to remove the conductive layer by using the hard mask layer as a stop layer.
In an embodiment, before the hard mask layer is formed, the method further includes a step of forming a pad silicon oxide layer on the substrate.
In an embodiment, after the hard mask layer is formed, the method further includes a step of forming a sacrificial layer on the hard mask layer.
In an embodiment, before the conductive layer is formed, the method further comprises a step of forming a gate dielectric layer on a sidewall of the trench by a thermal oxidation process.
In an embodiment, the hard mask layer is a silicon oxide layer or a silicon nitride layer.
The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:
The present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed.
Firstly, as shown in
The first-conductive doped region 101a, the second-conductive doped region 101b, the source region 120 and the second-conductive deep well region 101c are formed in the substrate 101 by a plurality of ion implantation processes. The second-conductive doped region 101b is formed in the substrate 101. The first-conductive doped region 101a is disposed over the second-conductive doped region 101b, and extended downwardly from a surface 101d of the substrate 101 to be contacted with the second-conductive doped region 101b. Consequently, a P/N junction 102 is formed between the first-conductive doped region 101a and the second-conductive doped region 101b. The source region 120 is extended downwardly from the surface 101d of the substrate 101, and formed in the first-conductive doped region 101a. The second-conductive deep well region 101c is formed in the substrate 101, and extended downwardly from the surface 101d of the substrate 101, serving as the drain of the trench gate metal oxide semiconductor field effect transistor 100. Moreover, the second-conductive deep well region 101c is contacted with the second-conductive doped region 101b. Furthermore, a buried layer 119 with the same conductivity as the second-conductive doped region 101b is disposed under the second-conductive doped region 101b.
In this embodiment, the second-conductive doped region 101b is an N-type well region with a lower dopant concentration. The first-conductive doped region 101a is a P-type body region. The source region 120 is an N-type well region with a higher dopant concentration. The second-conductive deep well region 101c is an N-type deep well region. The second-conductive deep well region 101c is isolated from the first-conductive doped region 101a through a shallow trench isolation structure 103. The buried layer 119 is an N-type doped region with a higher dopant concentration. The buried layer 119 is disposed under the second-conductive doped region 101b and contacted with the second-conductive deep well region 101c. Preferably, an N-type well region 101e with a dopant concentration greater than that of the N-type (second-conductive) deep well region 101c, maybe formed in the N-type (second-conductive) deep well region 101c, and extended downwardly from the surface 101d of the substrate 101.
Then, as shown in
Then, as shown in
After the patterned photoresist layer 106 and the remaining hard mask layer 105 are removed, a thermal oxidation process is performed to form a gate dielectric layer 109 on a sidewall 108a of the trench 108 (see
After the planarization process 111 is performed, a patterned photoresist layer 112 is formed on the polysilicon layer 110. By using the pad silicon oxide layer 104 as an etch stop layer, another etching process 113 is performed to remove a part of the planarized polysilicon layer 110. Consequently, a T-shaped portion of the planarized polysilicon layer 110 is remained and serves as a T-shaped polysilicon gate 114 of the trench gate metal oxide semiconductor field effect transistor 100(see
Then, a metal interconnection process is performed. Consequently, a dielectric material layer 117 is firstly formed over the surface 101d of the substrate 101 and the polysilicon gate 114, and then a plurality of metal contact plugs 118 are formed in the dielectric material layer 117. Meanwhile, the trench gate metal oxide semiconductor field effect transistor 100 is produced. The resulting structure of the trench gate metal oxide semiconductor field effect transistor 100 is shown in
Please refer to
However, the above-mentioned method for fabricating the trench gate metal oxide semiconductor field effect transistor 100 still has some drawbacks. For example, since two photolithography and etching processes are required to form the polysilicon gate 114, every misalignment error of the photomask may further decrease the alignment accuracy. Moreover, during the performing of the etching process 113, the surface 101d of the substrate 101 is still completely covered by the planarized polysilicon layer 110. Since the alignment mark for the etching process 113 is possibly hindered by the planarized polysilicon layer 110, the misalignment error of the photomask is thereby increased. Due to the misalignment error of the photomask, the protrusion portion 114b of the polysilicon gate 114 may be unexpectedly and asymmetrically extended in the transverse direction. If the (alignment) process errors in the process of forming the metal contact plug 118 are taken into consideration, the total cumulative misalignment error of the semiconductor device is very large. Under this circumstance, the metal contact plug 118 and the neighboring circuits may be suffered from charge breakdown.
For solving the above drawbacks, the method of forming the polysilicon gate 114 needs to be further improved.
Firstly, the steps as shown in
Furthermore, for improved control of the etching back process 215, before the patterned photoresist layer 106 is formed, another silicon dioxide layer 316 may be optionally formed on the hard mask layer 105 (see
Then, a thermal oxidation process is performed to form a gate dielectric layer 109 on a sidewall 108a of the trench 108 (see
Then, a planarization process 111 (e.g. a chemical mechanical polishing process) is performed to remove the polysilicon layer 110 by using the hard mask layer 105 as a polish stop layer. After the remaining hard mask layer 105 is removed, a T-shaped polysilicon gate 214 is formed (see
Then, a metal interconnection process is performed. Consequently, a dielectric material layer 117 is firstly formed over the surface 101d of the substrate 101 and the polysilicon gate 214, and then a plurality of metal contact plugs 118 are formed in the dielectric material layer 117. Meanwhile, the trench gate metal oxide semiconductor field effect transistor 200 is produced. The resulting structure of the trench gate metal oxide semiconductor field effect transistor 200 is shown in
From the above discussions, the structure of the polysilicon gate 214 of the trench gate metal oxide semiconductor field effect transistor 200 is improved in comparison to the trench gate MOSFET 100 shown in
Moreover, according to the embodiments of the fabricating method of the present invention, only a single photolithography and etching process is sufficient to form a polysilicon gate, instead of requiring two photolithography and etching processes to form the same. Consequently, the fabricating method of the present invention is simplified, the photomask number is reduced, and the misalignment error of the semiconductor device is largely reduced. Since the misalignment error is largely reduced, the symmetrical protrusion portion of the polysilicon gate is no longer unexpectedly and asymmetrically extended in the transverse direction, and the total cumulative misalignment error of the semiconductor device is reduced.
From the above discussions, the present invention provides a trench gate metal oxide semiconductor field effect transistor and a fabricating method thereof. The fabricating method comprises the following steps. Firstly, a substrate is provided. Then, a hard mask layer is formed on the substrate. Then, an etching process is performed to remove a part of the hard mask layer and form a trench in the substrate. Then, an etching back process is performed to remove a part of the hard mask layer. Then, a polysilicon layer is formed on the hard mask layer and filled into the trench. Then, by using the hard mask layer as a stop layer, a planarization process is performed to remove the polysilicon layer. Consequently, a polysilicon gate with the symmetrical protrusion portion is formed.
The symmetrical protrusion portion of the polysilicon gate can provide a larger process window for subsequently forming the metal contact plug on the polysilicon gate. Consequently, even if the feature size of the device is shrunken down, the misalignment error will be largely reduced.
From the above descriptions, the symmetrical protrusion portion of the polysilicon gate is formed by etching back the hard mask layer to widen the entrance of the trench and then filling the polysilicon layer. Consequently, it is not necessary to perform an additional photolithography and etching process. In other words, the fabricating method of the present invention is simplified and cost-effective. Since it is not necessary to repeatedly use the photomask for alignment, the precision of the alignment between the metal contact plug and the polysilicon gate is enhanced.
While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.
Claims
1. A trench gate metal oxide semiconductor field effect transistor, comprising:
- a substrate having a trench formed therein, wherein the trench is extended downwardly from a surface of the substrate; and
- a gate comprising an insertion portion and a symmetrical protrusion portion, wherein the insertion portion is embedded in the trench, and the symmetrical protrusion portion is symmetrically protruded over the surface of the substrate.
2. The trench gate metal oxide semiconductor field effect transistor according to claim 1, wherein the symmetrical protrusion portion is wider than the trench.
3. The trench gate metal oxide semiconductor field effect transistor according to claim 1, wherein the gate is a T-shaped gate, which is symmetrical with respect to a central line of the trench.
4. The trench gate metal oxide semiconductor field effect transistor according to claim 1, wherein the trench has a width smaller than or equal to 0.8 μm and a depth of about 1.6 μm.
5. The trench gate metal oxide semiconductor field effect transistor according to claim 1, further comprising:
- a dielectric material layer disposed over the surface of the substrate and the gate; and
- at least one contact plug penetrated through the dielectric material layer and electrically contacted with the symmetrical protrusion portion of the gate.
6. The trench gate metal oxide semiconductor field effect transistor according to claim 1, further comprising:
- a first-conductive doped region formed in the substrate;
- a second-conductive doped region formed in the substrate, wherein a P/N junction is formed between the first-conductive doped region and the second-conductive doped region, the trench is extended downwardly from the surface of the trench, penetrated through the first-conductive doped region and the P/N junction, and inserted into the second-conductive doped region;
- a gate dielectric layer formed on a sidewall of the trench; and
- a source region formed in the substrate and located beside the gate dielectric layer.
7. The trench gate metal oxide semiconductor field effect transistor according to claim 6, wherein the first-conductive doped region is a P-type body region, and the second-conductive doped region is an N-type well region.
8. The trench gate metal oxide semiconductor field effect transistor according to claim 6, further comprising an N-type buried layer, which is disposed under the second-conductive doped region.
9. The trench gate metal oxide semiconductor field effect transistor according to claim 6, wherein the source region is an N-type well region, and the source region is extended from the surface of the substrate into the first-conductive doped region.
10. A method for fabricating a trench gate metal oxide semiconductor field effect transistor, the method comprising steps of:
- providing a substrate;
- forming a hard mask layer on the substrate;
- performing an etching process to remove a part of the hard mask layer and forming a trench in the substrate;
- performing an etching back process to remove a part of the hard mask layer;
- forming a conductive layer on the hard mask layer, and filling the polysilicon layer into the trench; and
- performing a planarization process to remove the conductive layer by using the hard mask layer as a stop layer.
11. The method according to claim 10, wherein before the hard mask layer is formed, the method further comprises a step of forming a pad silicon oxide layer on the substrate.
12. The method according to claim 10, wherein after the hard mask layer is formed, the method further comprises a step of forming a sacrificial layer on the hard mask layer.
13. The method according to claim 10, wherein before the conductive layer is formed, the method further comprises a step of forming a gate dielectric layer on a sidewall of the trench by a thermal oxidation process.
14. The method according to claim 10, wherein the hard mask layer is a silicon oxide layer or a silicon nitride layer.
Type: Application
Filed: Oct 18, 2012
Publication Date: Apr 24, 2014
Applicant: UNITED MICROELECTRONICS CORP. (HSINCHU)
Inventors: Chun-Hong PENG (Hsinchu), Yu-Hsi LAI (Hualien)
Application Number: 13/654,432
International Classification: H01L 29/78 (20060101); H01L 21/283 (20060101);