SEMICONDUCTOR PROCESSING METHOD
A method for detecting metal contamination from a film-forming process causing interface traps is described. The film-forming process is performed to form a dielectric film on a wafer. An annealing treatment is performed to reduce the interface traps between the wafer and the dielectric film. Thereafter, the bulk recombination lifetime (BRLT) of the wafer is measured to estimate the amount of the metal contamination.
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1. Field of Invention
This invention relates to a semiconductor processing method, and particularly relates to a method for detecting metal contamination from a film-forming process causing interface traps.
2. Description of Related Art
Metal contamination in a semiconductor wafer may be detected by measuring the bulk recombination lifetime (BRLT) of the wafer, because the metal species facilitates the recombination of electrons and holes. When the amount of metal contamination of the wafer is larger, the BRLT of the wafer is shorter. Accordingly, the amount of the metal contamination from an IC process can be detected by subjecting a wafer to the IC process and then measuring the BRLT of the wafer.
However, in cases that the wafer has been subjected to a film-forming process causing interface traps, the electron-hole recombination is significantly facilitated by the interface traps, and the BRLT of the wafer is short (<700 μsec) regardless of the metal contamination amount. Hence, the metal contamination from the film-forming process is difficult to detect based on the BRLT measurement of the wafer.
SUMMARY OF THE INVENTIONIn view of the foregoing, this invention provides a semiconductor processing method that is capable of reducing interface traps after a film-forming process.
This invention also provides, as an exemplary embodiment of the semiconductor processing method, a method for detecting metal contamination from a film-forming process causing interface traps.
In the detecting method of this invention, the film-forming process is performed to form a dielectric film on a wafer, an annealing treatment is performed to reduce the interface traps between the wafer and the dielectric film, and then the bulk recombination lifetime (BRLT) of the wafer is measured to estimate the amount of the metal contamination.
Because the density of interface traps (Dit) is significantly decreased due to the annealing treatment, the affect of the interface traps to the BRLT measurement is significantly reduced so that the metal contamination is detectable based on the BRLT.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, a preferred embodiment accompanied with figures is described in detail below.
It is noted that the following embodiment is intended to further explain this invention but not to limit the scope thereof. For example, although in the embodiment a wafer is used and is intended to investigate the metal contamination from the film-forming process, other kind of semiconductor wafer or substrate that has been subjected to a film-forming process causing interface traps may also be treated with the method of this invention, in which the density of interface traps is reduced by the annealing treatment in the method of this invention.
Referring to
The film-forming process may be a rapid thermal process (RTP), a high-density plasma chemical vapor deposition (HDP-CVD) process, or a LPCVD process. The LPCVD process may be carried out in a SINGEN™ system of Applied Materials, Inc. The rapid thermal process (RTP) may be a rapid thermal oxidation (RTO) process, which may cause metal contamination because of parts quality issue or damage. The dielectric film 14 may include silicon oxide, silicon nitride, or silicon oxynitride.
Referring to
Referring to
Based on the determination of the amount of metal contamination in the wafer with the above steps, the operator of the semiconductor manufacturing process is able to, for example, adjust the condition of the film-forming process to reduce the metal contamination of the subsequent work wafers.
To demonstrate the effects of this invention, an experiment example is described below. A certain number of control Si-wafers were each subjected to a rapid thermal oxidation (RTO) process using H2 and O2 at 1050° C. for 60 seconds, so that a thermal oxide film having a thickness of about 15 nm was formed on each sample wafer. The subsequent annealing treatment was performed with H2 gas, under a pressure of 20 Torr at 1000° C. for 30 seconds. The BRLT measurement was according to the aforementioned reference.
The result of the experiment example is shown in
It is clear from
This invention has been disclosed above in the preferred embodiments, but is not limited to those. It is known to persons skilled in the art that some modifications and innovations may be made without departing from the spirit and scope of this invention. Hence, the scope of this invention should be defined by the following claims.
Claims
1. A method for detecting metal contamination from a film-forming process causing interface traps, comprising:
- performing the film-forming process to form a dielectric film on a wafer;
- performing an annealing treatment to reduce interface traps between the wafer and the dielectric film; and
- measuring a bulk recombination lifetime (BRLT) of the wafer to estimate an amount of the metal contamination.
2. The method of claim 1, wherein the annealing treatment utilizes a gas containing at least one of H2, N2O and NO.
3. The method of claim 2, wherein the annealing treatment is performed at 1000° C. or higher for 30 to 60 seconds.
4. The method of claim 1, wherein the dielectric film comprises silicon oxide, silicon nitride, or silicon oxynitride.
5. The method of claim 1, wherein the film-forming process comprises a rapid thermal process (RTP), a high-density plasma chemical vapor deposition (HDP-CVD) process, or a LPCVD process.
6. A semiconductor processing method, comprising:
- performing a film-forming process to form a dielectric film on a semiconductor substrate; and
- performing an annealing treatment to reduce interface traps between the substrate and the dielectric film, wherein the annealing treatment utilizes a gas containing at least one of H2, N2O and NO.
7. The semiconductor processing method of claim 6, further comprising: measuring a bulk recombination lifetime (BRLT) of the substrate to estimate an amount of metal contamination therein.
8. The semiconductor processing method of claim 6, wherein the annealing treatment is performed at 1000° C. or higher for 30 to 60 seconds.
9. The semiconductor processing method of claim 6, wherein the dielectric film comprises silicon oxide, silicon nitride, or silicon oxynitride.
10. The semiconductor processing method of claim 6, wherein the film-forming process comprises a rapid thermal process (RTP), a high-density plasma chemical vapor deposition (HDP-CVD) process, or a LPCVD process.
Type: Application
Filed: May 14, 2013
Publication Date: Nov 20, 2014
Applicant: United Microelectronics Corp. (Hsinchu)
Inventors: Sheng Zhang (Singapore), Guang-You Yu (Singapore), Ying-Jie Xu (Singapore), Chaw Che (SINGAPORE)
Application Number: 13/894,031
International Classification: H01L 21/66 (20060101);