TECHNIQUES FOR FILAMENT LOCALIZATION, EDGE EFFECT REDUCTION, AND FORMING/SWITCHING VOLTAGE REDUCTION IN RRAM DEVICES
The present disclosure provides a system and method for forming a resistive random access memory (RRAM) device. A RRAM device consistent with the present disclosure includes a substrate and a first electrode disposed thereon. The RRAM device includes a second electrode disposed over the first electrode and a RRAM dielectric layer disposed between the first electrode and the second electrode. The RRAM dielectric layer has a recess at a top center portion at the interface between the second electrode and the RRAM dielectric layer. The present disclosure further provides a computing device. The computing device includes a motherboard, a processor mounted on the motherboard, and a communication chip fabricated on the same chip as the processor or mounted on the motherboard. The processor comprises a substrate, a first electrode, second electrode, and a RRAM layer which has a recess at the interface between the second electrode and RRAM oxide layer.
The present divisional application claims the benefit of priority under 35 U.S.C. 121 to U.S. Non-Provisional application Ser. No. 14/752,934, entitled “Techniques for filament localization, edge effect reduction, and forming/switching voltage reduction in RRAM devices” filed Jun. 27, 2015.
FIELDEmbodiments described herein generally relate to resistive random access memory (RRAM) devices and more particularly to techniques for localizing filaments within a RRAM device.
BACKGROUNDA RRAM device is a type of non-volatile random access memory computer memory that works by changing the resistance across a dielectric solid state material. During switching, the dielectric material, which is normally insulating, is made to conduct electrical current through a conduction path referred to as a filament. Conventional RRAM stacks are planar and therefore when a sufficiently high voltage is applied, an electric field is uniformly applied across the entire RRAM device.
As such, during switching, a filament can form randomly throughout the RRAM device. For example, in conventional RRAM devices, a filament may be formed near the edge of the device which may not provide a sufficient conductive path due to defects at the edge. In some instances, multiple deficient filaments may form randomly within the RRAM device. As such, there exists a need to provide a technique to form a localized filament within a RRAM device. The present disclosure addresses this need.
Described herein are systems and methods of random resistive access memory devices, and in particular (but not exclusively), to RRAM devices which implement techniques for filament localization and forming/switching voltage reduction. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present disclosure may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.
Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.
Implementations of the disclosure may be formed or carried out on a substrate, such as a semiconductor substrate. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present disclosure.
Top and bottom electrodes 101, 103 may be composed of a metal material. For example, top and bottom electrodes 101, 103 may be composed of titanium nitride (TiN) but are not limited thereto. In some embodiments, top and bottom electrodes 101, 103 may also include tungsten (W).
RRAM dielectric material 102 may include an oxide material. For example, RRAM dielectric material 102 may comprise titanium oxide (TiOx), hafnium oxide (HfOx), tantalum oxide (TaOx), or tungsten oxide (WOx).
Advantageously, recess 205 portion facilitates filament localization. In some embodiments, recess 205 is near the center of the RRAM dielectric material 202 and away from the edges of the RRAM dielectric material/ILD interface. As such, when a threshold voltage is applied to effect switching, a filament 206 forms extending from the recess 205 portion to the bottom electrode such that an electrical pathway extends from the top electrode 201 to the bottom electrode 203. In some implementations, the filament 206 area consists of oxygen vacancies as oxygen atoms have been removed by techniques described below. Most notably, the electric field generated by the applied threshold is approximately twice as great as the electric field in the dielectric material 202 external to the recess 205 portion according to some embodiments of the present disclosure.
In some embodiments, the threshold voltage needed to effect switching may range from 0.5-3 volts. However, the present disclosure is not limited thereto. In some embodiments, the threshold voltage to effect switching is 3 volts for a 4 nm-thick RRAM dielectric material 202.
In the embodiment shown in the figure, recess 205 portion has a square profile. However, as will be described below, the recess 205 portion is not limited thereto. The recess 205 portion may be formed by any conventional semiconductor process known in the art. For example, a subtractive process such as an etch process may be used to form the recess 205 portion as will be further described below. The depth of the recess 205 portion may range from 0.5 nm-10 nm. In some embodiments, the depth of the recess 205 portion is 2.0 nm. It should be understood by one having ordinary skill in the art that the dimensions of the recess 205 portion may depend on the material properties of the RRAM dielectric material 202.
The other layers of the RRAM device structure 200 may also be defined with regards to dimensions. The RRAM dielectric material 202 may have a thickness between 1 nm and 9 nm. For example, the thickness of RRAM dielectric material 202 is 4 nm. In an embodiment when the RRAM dielectric material 202 has a thickness of 4 nm, the thickness of the recess 205 portion is approximately 2 nm. In yet another embodiment, when the RRAM dielectric material 202 has a thickness of 8 nm, the thickness of the recess 205 portion is approximately 2 nm.
The top and bottom electrodes 201, 203 may have a thickness between 10 nm and 100 nm each. In some embodiments, the thickness of the top electrode 201 and the bottom electrode 203 is approximately 30 nm. The ILD regions 204a, 204b may have a thickness between 50 nm and 150 nm.
In
RRAM dielectric material 602 may be formed by a PVD or an atomic layer deposition (ALD) process. In an embodiment when a PVD process is employed, a RRAM dielectric material 602 may be deposited at a rate between 1 and 20 angstroms/second. Alternatively, when an ALD process is used, a RRAM dielectric material 602 may be deposited at a rate between 1 angstrom/(10 seconds) and 1 angstrom/(60 seconds). Various materials may be used for the RRAM dielectric material 602 such as hafnium oxide (HfOx), titanium oxide (TiOx), tantalum oxide (TaOx), or tungsten oxide (WOx).
In some embodiments, the recess portion 605 may have two regions with one region wider than the other.
Moving forward to
After the recess 605 is formed, the material used to form a top electrode is formed over the recess 605. A top electrode may be formed by a PVD process and the top electrode 605 material may be deposited at a rate between 1 angstrom/second and 100 angstroms/second.
The temperature employed within the process chamber during a PVD or ALD deposition process may be between 30° C. and 500° C. The pressure employed during the PVD deposition process may be between 0.5 and 10 mTorr whereas during the ALD deposition process, the pressure employed within the process chamber may be between 1 and 200 Torr.
In some embodiments, oxygen exchange layer 711 may create oxygen vacancies within the RRAM dielectric material 702 which may aid in the forming of a conductive path during the switching process. In addition, the recess 705 within the RRAM dielectric material 702 may localize a filament near the recess 705 (e.g., near the center of the stack). As such, the presence of oxygen exchange layer 711 may help to reduce the forming/switching voltage for the RRAM device structure 700.
Oxygen exchange layer 711 may comprise any of various materials such as, but not limited to, hafnium, titanium, tantalum, platinum, or palladium. The oxygen exchange layer 711 may be formed by any suitable process such as a PVD process with a deposition rate between 1 and 100 A/sec.
The interposer 1700 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.
The interposer may include metal interconnects 1708 and vias 1710, including but not limited to through-silicon vias (TSVs) 1712. The interposer 1700 may further include embedded devices 1714, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1700.
In accordance with embodiments of the present disclosure, apparatuses or processes disclosed herein may be used in the fabrication of interposer 1700.
Computing device 1800 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory 1810 (e.g., DRAM), non-volatile memory 1812 (e.g., ROM or flash memory), a graphics processing unit 1814 (GPU), a digital signal processor 1816, a crypto processor 1842 (a specialized processor that executes cryptographic algorithms within hardware), a chipset 1820, an antenna 1822, a display or a touchscreen display 1824, a touchscreen controller 1826, a battery 1830 or other power source, a power amplifier (not shown), a global positioning system (GPS) device 1828, a compass 1830, a motion coprocessor or sensors 1832 (that may include an accelerometer, a gyroscope, and a compass), a speaker 1834, a camera 1836, user input devices 1838 (such as a keyboard, mouse, stylus, and touchpad), and a mass storage device 1840 (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
The communications chip 1808 enables wireless communications for the transfer of data to and from the computing device 1800. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1808 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 1800 may include a plurality of communication chips 1808. For instance, a first communication chip 1808 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1808 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
The processor 1804 of the computing device 1800 includes one or more devices, such as RRAM devices, that are formed in accordance with embodiments of the present disclosure. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
The communication chip 1808 may also include one or more devices such as RRAM devices that are formed in accordance with embodiments of the present disclosure.
In further embodiments, another component housed within the computing device 1800 may contain one or more devices, such as RRAM devices, that are formed in accordance with implementations of the present disclosure.
In various embodiments, the computing device 1800 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 1800 may be any other electronic device that processes data.
The above description of illustrated implementations of the present disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. While specific implementations of, and examples for, the present disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure, as those skilled in the relevant art will recognize.
These modifications may be made to the present disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the present disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the present disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.
Claims
1. A resistive random access memory device, comprising:
- a substrate;
- a first electrode disposed over the substrate;
- a second electrode disposed over the first electrode; and
- a resistive random access memory oxide layer disposed between the first electrode and the second electrode;
- wherein the resistive random access memory oxide layer has a recess at the interface between the second electrode and the resistive random access memory oxide layer.
2. The resistive random access memory device of claim 1 further comprising an interlayer dielectric disposed on a perimeter of the first electrode, second electrode, and resistive random access memory oxide layer.
3. The resistive random access memory device of claim 1 further comprising an oxygen exchange layer disposed between the resistive random access memory oxide layer and the first electrode.
4. The resistive random access memory device of claim 1, wherein at least one of the cross-section of the recess is v-shaped or square-shaped.
5. The resistive random access memory device of claim 1, wherein at least one of the first electrode or the second electrode comprises titanium nitride.
6. The resistive random access memory device of claim 1, wherein at least a portion of the second electrode is disposed within the recess.
7. A resistive random access memory device, comprising:
- a first electrode;
- a resistive random access memory oxide layer disposed over the first electrode;
- an oxide layer disposed over the resistive random access memory oxide layer;
- wherein the oxide layer has a recess region at a center portion extending to a top portion of the resistive random access memory oxide layer; and
- a second electrode disposed over the oxide layer.
8. The resistive random access memory device of claim 7, wherein the cross-section of the recess is v-shaped or square-shaped.
9. The resistive random access memory device of claim 7 further comprising an oxygen exchange layer disposed on top of the oxide layer and within the recess region.
10. The resistive random access memory device of claim 7 further comprising a metal layer disposed between the first electrode and the resistive random access memory layer.
11. The resistive random access memory device of claim 10, wherein the metal layer comprises silver or copper.
12. The resistive random access memory device of claim 7, wherein the resistive random access memory oxide layer is disposed on the first electrode.
13. The resistive random access memory device of claim 7, wherein the oxide layer is disposed on the resistive random access memory oxide layer.
14. The resistive random access memory device of claim 7, wherein the recess region has a first recess and a second recess.
15. The resistive random access memory device of claim 14, wherein the first recess has a greater area than the area of the second recess.
16. A computing device, comprising:
- a motherboard;
- a processor mounted on the motherboard; and
- a communication chip fabricated on the same chip as the processor or mounted on the motherboard;
- wherein the processor comprises: a substrate; a first electrode disposed over the substrate; a second electrode disposed over the first electrode; and a resistive random access memory oxide layer disposed between the first electrode and the second electrode; wherein the resistive random access memory oxide layer has a recess at the interface between the second electrode and the resistive random access memory oxide layer.
17. The computing device of claim 16, wherein at least one of the cross-section of the recess is v-shaped or square-shaped.
18. The computing device of claim 16 further comprising an oxygen exchange layer disposed between the resistive random access memory oxide layer and the first electrode.
19. The computing device of claim 16, wherein at least a portion of the second electrode is disposed within the recess.
Type: Application
Filed: May 15, 2017
Publication Date: Aug 31, 2017
Inventors: Ravi Pillarisetty (Portland, OR), Prashant Majhi (Austin, TX), Uday Shah (Portland, OR), Niloy Mukherjee (Beaverton, OR), Elijah V. Karpov (Santa Clara, CA), Brian S. Doyle (Portland, OR), Robert S. Chau (Beaverton, OR)
Application Number: 15/595,868