CURRENT-BASED STIMULATORS FOR ELECTROGENIC CELLS AND RELATED METHODS

Methods and systems for stimulating and monitoring electrogenic cells are described. Some systems for stimulating electrogenic cells are based on the injection of electric currents into the cells via electrodes connected to the cells. Such stimulators may comprise an impedance element having an input terminal and an output terminal coupled to an electrode, and a voltage follower coupled between the input terminal and the output terminal of the impedance element, the voltage follower being configured to maintain a substantially constant voltage between the input terminal and the output terminal of the impedance element. The impedance element may comprise one or more switched capacitors at least in some embodiments. In some embodiments, the voltage follower may be implemented using a source follower.

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Description
RELATED APPLICATIONS

The present application claims the benefit under 35 U.S.C. § 119(e) of U.S. Provisional Patent Application Ser. No. 62/529,683 entitled “CURRENT-BASED STIMULATORS FOR ELECTROGENIC CELLS AND RELATED METHODS,” filed Jul. 7, 2017, which is incorporated herein by reference in its entirety, and claims the benefit under 35 U.S.C. § 119(e) of U.S. Provisional Patent Application Ser. No. 62/580,126 entitled “ELECTRONIC CIRCUITS FOR ANALYZING ELECTROGENIC CELLS AND RELATED METHODS,” filed Nov. 1, 2017, which is incorporated herein by reference in its entirety.

BACKGROUND

The present application relates to stimulation and monitoring of electrogenic cells, such as brain cells, heart cells, endocrine cells, and other muscular cells.

BRIEF SUMMARY

According to one aspect of the present application, an apparatus is provided. The apparatus may comprise an electrogenic cell, an electrode electrically in contact with the electrogenic cell, a stimulation circuit coupled to the electrode, the stimulation circuit comprising: an impedance element having an input terminal and an output terminal coupled to the electrode; and a voltage follower coupled between the input terminal and the output terminal of the impedance element, the voltage follower being configured to maintain a substantially constant voltage between the input terminal and the output terminal of the impedance element.

In some embodiments, the impedance element comprises a switched capacitor.

In some embodiments, the apparatus further comprises a control circuit coupled to the switched capacitor, the control circuit having a frequency tuner.

In some embodiments, the electrogenic cell and the electrode form a load having a first capacitance, and wherein the switched capacitor has a second capacitance that is lower than the first capacitance.

In some embodiments, the voltage follower comprises one or more transistors arranged in a source follower configuration.

In some embodiments, the one or more transistors comprise a respective gate terminal coupled to the output terminal of the impedance element and a respective source terminal coupled to the input terminal of the impedance element.

In some embodiments, the apparatus further comprises control circuitry configured to electrically couple the source follower to the input terminal of the impedance element during a first time period and to electrically couple the source follower to the output terminal of the impedance element during a second time period different than the first time period.

In some embodiments, the first time period and the second time period do not overlap in time.

In some embodiments, the stimulation circuit lacks operational amplifiers.

In some embodiments, the electrogenic cell is selected from the group consisting of a brain cell, a heart cell and an endocrine cell.

In some embodiments, the apparatus further comprises an operational amplifier coupled to the voltage follower; and a receiver circuit coupled to the electrode and comprising a high-frequency cutting filter configured to block ripples generated by the stimulation circuit.

According to another aspect of the present application, a method for electrically stimulating an electrogenic cell is provided. The method may comprise generating an output current by: causing an input voltage of an impedance element to follow an output voltage of the impedance element, and coupling the output voltage to an electrode coupled to the electrogenic cell; and driving the electrogenic cell with the output current.

In some embodiments, causing the input voltage of the impedance element to follow the output voltage of the impedance element comprises causing a first terminal of a transistor to follow a second terminal of the transistor.

In some embodiments, causing the input voltage of the impedance element to follow the output voltage of the impedance element comprises causing a source terminal of a transistor to follow a gate terminal of the transistor.

In some embodiments, the method further comprises charging the impedance element during a first time period and discharging the impedance element during the second time period different than the first time period.

In some embodiments, driving the electrogenic cell with the output current is performed in the second time period.

In some embodiments, the first time period and the second time period do not overlap in time.

According to yet another aspect of the present application, a method for monitoring an electrogenic cell is provided. The method may comprise decreasing an input impedance of the electrogenic cell by driving an output current through an electrode placed in contact with the electrogenic cell, and sensing electric signals generated by the electrogenic cell with an amplifying circuit coupled to the electrode.

In some embodiments, driving the output current through the electrode comprises: causing an input voltage of an impedance element to follow an output voltage of the impedance element, and coupling the output voltage to the electrode.

In some embodiments, causing the input voltage of the impedance element to follow the output voltage of the impedance element comprises causing a source terminal of a transistor to follow a gate terminal of the transistor.

In some embodiments, driving the output current through the electrode comprises driving a direct current (DC) for at least one minute.

In some embodiments, the output current is controlled to alternate between two or more values.

According to yet another aspect of the present application a method for manufacturing a current-based electrogenic stimulator is provided. The method may comprise forming an electrode; forming a stimulation circuit coupled to the electrode, wherein forming the stimulation circuit comprises: forming an impedance element having an input terminal and an output terminal coupled to the electrode; and forming a voltage follower coupled between the input terminal and the output terminal of the impedance element.

In some embodiments, the stimulation circuit and the electrode are disposed on a common substrate.

In some embodiments, forming the impedance element comprises forming a switched capacitor.

BRIEF DESCRIPTION OF THE DRAWINGS

Various aspects and embodiments of the application will be described with reference to the following figures. It should be appreciated that the figures are not necessarily drawn to scale. Items appearing in multiple figures are indicated by the same reference number in all the figures in which they appear.

FIG. 1 is schematic diagram illustrating an electrogenic network and a probing system, according to some non-limiting embodiments.

FIG. 2 is a block diagram of a representative electrogenic stimulator, according to some non-limiting embodiments.

FIG. 3A is a schematic diagram of a representative system for monitoring electrogenic activity, according to some non-limiting embodiments.

FIG. 3B is a circuit diagram of a representative system for monitoring electrogenic activity, according to some non-limiting embodiments.

FIG. 3C is a plot illustrating the voltage obtained when a cell is probed using the system of FIG. 3B, according to some non-limiting embodiments.

FIG. 3D is a plot illustrating a representative current for probing a cell, according to some non-limiting embodiments.

FIG. 3E is plot illustrating the voltage obtained when a cell is probed using the current of FIG. 3D, according to some non-limiting embodiments.

FIGS. 4A-4E are circuit diagrams of representative electrogenic stimulators, according to some non-limiting embodiments.

FIGS. 5A-5B are circuit diagrams of representative electrogenic stimulators, according to some non-limiting embodiments.

FIGS. 5C-5D are plots illustrating the behavior of the electrogenic stimulators of FIGS. 5A-5B, according to some non-limiting embodiments.

FIG. 6A is a circuit diagram of a representative electrogenic stimulator, according to some non-limiting embodiments.

FIGS. 6B-6C are plots illustrating the behavior of the electrogenic stimulator of FIG. 6A, according to some non-limiting embodiments.

FIGS. 7A-7C are circuit diagrams of representative biphasic electrogenic stimulators, according to some non-limiting embodiments.

FIG. 7D is a circuit diagram illustrating a representative electrogenic stimulator including an operational amplifier, according to some non-limiting embodiments.

FIG. 7E is a circuit diagram illustrating a representative electrogenic stimulator arranged to limit voltage ripples, according to some non-limiting embodiments.

FIG. 8 is a circuit diagram illustrating a representative system for stimulating electrogenic cells, according to some non-limiting embodiments.

FIG. 9 is a layout illustrating a representative system for stimulating electrogenic cells, according to some non-limiting embodiments.

FIG. 10A is a circuit diagram illustrating a representative experimental setup for stimulating electrogenic cells, according to some non-limiting embodiments.

FIGS. 10B-10D are plots illustrating the behavior of the circuit of FIG. 10A, according to some non-limiting embodiments.

FIG. 11 illustrates a plurality of plots representing the current response of the circuit of FIG. 10A, according to some non-limiting embodiments.

FIG. 12A is a circuit diagram illustrating another representative experimental setup for stimulating electrogenic cells, according to some non-limiting embodiments.

FIGS. 12B-12C are plots illustrating the behavior of the circuit of FIG. 12A, according to some non-limiting embodiments.

FIG. 13 illustrates plots representing the current and voltage response of the circuit of FIG. 12A, according to some non-limiting embodiments.

FIGS. 14A-14B are tables illustrating representative circuit parameters, according to some non-limiting embodiments.

FIG. 15A is a schematic diagram illustrating an array of nanowires before and after insertion into a cell, according to some non-limiting embodiments.

FIG. 15B is a schematic diagram illustrating a nanowire connected to a metal pad and inserted into a cell, according to some non-limiting embodiments.

FIG. 15C is a schematic diagram illustrating a representative system for probing a neuronal network comprising a complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) and a nanowire array, according to some non-limiting embodiments.

DETAILED DESCRIPTION I. Overview

The inventors have recognized and appreciated that stimulation of electrogenic cells may be improved relative to conventional techniques by using current stimulators. Unlike conventional stimulators, these current stimulators may be configured to accurately control the amount of electric charge, and hence of electric current, provided to an electrogenic cell. As a result, delivery of large currents that can seriously harm the integrity of a cell (which often occur in conventional stimulators) may be prevented.

Electrogenic cells are biological cells that are capable of generating and/or responding to electric signals. Electrogenic cells can be arranged in networks, where the cells communicate with other cells of the network via electric signals (referred to herein also as bioelectric events). Examples of electrogenic cells include, but are not limited to, brain cells, heart cells, endocrine cells, and other muscular cells. Action potentials are one example of these electric signals. Action potentials occur in several types of biological cells and can be generated by special types of voltage-gated ion channels embedded in a cell's plasma membrane. These channels may be shut when the membrane potential is near the resting potential of the cell, and may be opened if the membrane increases to a precisely defined threshold voltage.

The inventors have further recognized and appreciated that, in some circumstances, it is desirable to simultaneously stimulate multiple electrogenic cells (e.g., a few thousands, a few millions, or even more) to control and/or characterize the behavior of the overall electrogenic network. As such, large arrays of stimulators may be needed to stimulate each cell individually. However, the size of conventional stimulators limits the number of stimulators that can be integrated on a single circuit, such as a single chip. Some embodiments of the present application are directed to stimulators having small footprints, thus enabling the integration of multiple stimulators onto a single circuit. Such a reduction in the size of the stimulators can be achieved, at least in some embodiments, by employing circuit elements that can be implemented using a small number of transistors or other electric components. Accordingly, in some such embodiments, the stimulator lacks circuits including large number of transistors (such as more than fifty transistors), such as operational amplifiers or other circuits having a voltage gain that is greater than one.

Some embodiments of the present application are directed to stimulators capable of controlling the amount of current provided to an electrogenic cell with a high precisions (e.g., within few nanoamperes (nA), within a few picoamperes (pA) or less). Such precise control of the current may be achieved, at least in some embodiments, by employing an impedance element having an adjustable resistance and a voltage follower. In these embodiments, the amount of current output by the stimulator may be set by setting the value of the impedance element's resistance. The voltage follower may be configured to stabilize the voltage across the terminals of the impedance element, and as a result, the output current. In some such embodiments, the impedance element comprises a switched capacitor, and the resistance of the switched capacitor may be set by varying the frequency of the signal driving the impedance element.

Some embodiments of the present application are directed to systems and methods for monitoring the electric activity of one or more electrogenic cells. Due to the large impedance of electrogenic cells relative to the surrounding environment, obtaining signals from the cells that accurately represent the cell's activity is often challenging. The inventors have recognized and appreciated a method for improving the ability to electrically probe these cells by reducing the impedance of the cells. In some embodiments, a reduction in a cell's impedance may be achieved by generating a potential difference between the electrode used to probe the cell and a node positioned adjacent the cell. This potential difference may be generated, at least in some embodiments, by forcing an electric current to flow through the electrode. Once this potential difference is established, the difference in impedance between the cell and the surrounding environment may be reduced, thus facilitating electric probing of the cell.

II. Electrogenic Stimulators

FIG. 1 is a schematic diagram illustrating an electrogenic network and a probing system. Probing system 100 may be implemented, in some embodiments, using electronic circuits such as CMOS circuits. Electrogenic network 102 comprises a plurality of electrogenic cells 1041, 1042 . . . 104N. These cells may be interconnected with one another is any suitable fashion and may communicate with one another via electric signals, such as action potentials. The cells of electrogenic network 102 may be probed using probing system 100 in vitro, in vivo, or in any other suitable way. These cells may be brain cells, heart cells, endocrine cells, or other types muscular cells. N may be between 1 and 10, between 1 and 100, between 1 and 1000, between 1 and 10000, between 1 and 100000, or greater than 100000.

Probing system 100 may comprise electrodes 1061, 1062 . . . 106N, receivers 1081, 1082 . . . 108N, stimulators 1101, 1102 . . . 110N, and control read-out circuit 112. In some embodiments, these components of probing system 100 are integrated on a single integrated circuit. Of course, multiple integrated circuits may be used, as the application is not limited in this respect.

Electrodes 1041, 1042 . . . 104N may be placed in electrical contact with respective electrogenic cells. For example, the electrogenic cells may be placed in a container with an electrically conductive solution, and the electrodes may be placed in the solution. The electrodes may have areas ranging from 1 nm2 to 1 cm2, though other ranges are also possible.

Stimulators 1101, 1102 . . . 110N may be electrically connected to respective electrodes, and may be configured to stimulate respective electrogenic cells. In some embodiments, the stimulus may be an electric current. Representative implementations for the stimulators are described further below. When stimulated with an electric signal, an electrogenic cell may in response produce electric activity in conjunction with other cells of the network.

As will be described further below, the amount of current provided to a cell may be controlled, at least in some embodiments, by setting the frequency with which a stimulator is driven. As such, the stimulators 1101, 1102 . . . 110N may be coupled to frequency tuner 114, a circuit configured to generate electric signals with a desired frequency. The frequency may be varied in any of numerous ways, including, for example, with a controllable oscillator.

Receivers 1081, 1082 . . . 108N may be configured to monitor the electric activity of the respective cells. For example, the receivers may sense electric signals, such as voltages or currents, which may be representative of the cells' action potentials. In some embodiments, receivers 1081, 1082 . . . 108N comprise signal amplifiers (e.g., voltage amplifiers or transimpedance amplifiers).

In some embodiments, the stimulators may be configured to stimulate the cells by providing them with electric currents, and as such may comprise circuits for sourcing electric currents. A representative system for sourcing electric currents is illustrated in FIG. 2. Stimulator 200 comprises an impedance element 204, a first voltage follower 2021 and a second voltage follower 2022. While two voltage followers are shown in this example, any suitable number of voltage followers greater than or equal to one may be employed. Stimulator 200 is coupled to load 206, which may reflect the electric characteristics of an electrode 106 and/or a cell 104. Depending on the type of cell and/or electrode, the load 206 may be a resistive load, a capacitive load, or any combination thereof.

Impedance element 204 may have an output terminal coupled to load 206, and an input terminal. Electric currents may be provided to the load via the output terminal. In some embodiments, the voltage follower(s) may be coupled between the output terminal and the input terminal of impedance element 204. Impedance element 204 may be implemented in any of numerous ways, including but not limited to a resistor (or a combination of resistors), a capacitor (or a combination of capacitors), and/or one or more switched capacitors (e.g., one or more capacitors and one or more switches).

In some embodiments, impedance element 204 may be configured to provide the load with a current that is proportional to the difference between the voltage appearing at its input terminal and the voltage appearing at its output terminal. However, such a voltage difference may fluctuate over time, thus leading to a fluctuating current. Such behavior is often undesirable as it diminishes the ability to stimulate different cells uniformly.

Voltage followers 2021 and 2022 may be arranged to limit fluctuations in the current provided to the load. For example, the voltage followers may be configured to ensure that the voltage appearing at the input terminal of the impedance element follows the voltage appearing at the output terminal of the impedance element. In this way, the difference between the voltages may remain substantially constant over time, thus limiting current fluctuations.

In some embodiments, only one voltage follower may be active at a time. For example, voltage follower 202k may be active during a first time period while voltage follower 2022 may be deactivated (for example by opening a switch). The opposite configuration may occur during a second time period. In this manner, no voltage sources are activated in parallel at the same time.

III. Monitoring of Electrogenic Activity

As described above, electrogenic cells stimulators may be employed to stimulate cells to produce electrogenic activity. However, stimulators of the types described herein may be used in different settings. One such setting is in the monitoring of electrogenic activity. FIG. 3A illustrates a non-limiting implementation of an electrogenic stimulator used in electrogenic monitoring. As illustrated, electrode 106 is coupled to receiver 108, to stimulator 110 (which may be implemented according to any of the embodiments described above and below), and to cell 104. Cell 104 may be placed in a container 150, which may comprises for example an electrolyte. In the embodiments in which the container includes an electrolyte, the impedance of the electrolyte may be substantially lower than the impedance of the cell 104. As a result, electrically probing of the cell using receiver 108 may be challenging, since the majority of the signal received would solely (or for the most part) depend on the impedance of the electrolyte, rather than the impedance of the cell.

In some embodiments, the impedance of the cell at location “B” (inside the cell), may be decreased by generating a voltage between electrode 106 and a location “A” (outside the cell). This voltage may be generated for example by forcing a current sourced by stimulator 110 to flow through electrode 106. When such a current is flown, the impedance at location A is decreased. As a result, the impedance at location B relative to the surrounding electrolyte is also decreased, thus facilitating the monitoring of the cell's electrogenic activity.

In some embodiments, current may be sourced by the stimulator for the duration of a monitoring session, which may range between one second and several hours.

FIG. 3B is a circuit diagram illustrating a system for monitoring electrogenic activity, according to some embodiments. As shown, a cell 104 is immersed in an electrolyte 152, which may be contained inside container 150 of FIG. 3A. The cell exhibits an input resistance Rjm, which may be for example more than 10 GΩ or more than 100 GΩ. Voltage Vm (the quantity to be sensed) may represent for example an action potential.

Electrode 106 is represented in FIG. 3B by its impedance Ze. The electrode is coupled to receiver 108. Rs represents the resistance of the electrolyte, which may be for example between 1MΩ and 100MΩ. Since Rjm is, at least in some embodiments, a few orders of magnitude greater than Rs, attempts to sense to sense Vm using receiver 108 will result in the sensing of Vj, rather than Vm. The inventors have appreciated, however, that sensing of Vm may be enabled by injecting (or extracting) a current through the electrode into the electrolyte, which results in a substantial decrease in the value of Rjm. Accordingly, stimulator 110 includes a current generator Ie configured to drive a current through the electrolyte.

FIG. 3C is a plot illustrating the response of the system when a current is generated with the current generator of FIG. 3B. Specifically, FIG. 3C illustrates an example of a current Ie, and the response of the system in terms of voltage Ve, at the electrode 106. Prior to t=t0, no current is generated (0 nA). In this period of time, voltage Ve exhibits an amplitude of the order of 0.2 mV. Voltage peaks of about 0.1 mV in amplitude are observed. Given their low amplitude, these peaks are an attenuated and distorted representation of the intracellular activity (e.g., action potentials).

At t=t0, the current Ie output by the current generator is set to −1 nA (where the negative sign indicates a current flowing away from the electrolyte). It should be appreciated that most of the current generated flows through electrode 106, rather than receiver 108, since receiver 108 exhibits a capacitive input impedance, at least in some embodiments. After t0, but prior to t1, Ve exhibits several peaks with amplitude of the order of 4 mV. These peaks are the result of electrogenic activity in the cell. As illustrated, the amplitude of the peaks is significantly higher than the noise floor, thus making it easily detectable by receiver 108. The increase in the peaks of Ve is due to a reduction in Rjm when Ie is set to −1 nA. Further sub-threshold signals are able to measured with the increased signal-to-noise ratio, in this example excitatory post synaptic potentials, which are unable to be resolved from the noise without the application of Ie=−1 nA. Of course, other values of Ie other than −1 nA are also possible in other embodiments.

In some embodiments, to further enhance the cell's response, the stimulators may generate a first current value for reducing the value of Rjm, and subsequently a second current value for stimulating electrogenic activity. In some embodiments, the stimulator may alternate between the first and second current values, for example in a periodic fashion. An example of a current Ie that may be generated to reduce resistance Rjm and stimulate electrogenic activity is illustrated in the plot of FIG. 3D, in accordance with some embodiments. In this case, a −1.1 nA current is used to reduce Rjm, and a −550 pA is used to stimulate electrogenic activity. In response to such a current, voltage Ve responds with the behavior of FIG. 3E. As shown, multiple peaks are generated in response to the −550 pA pulses. The peaks are the result of electrogenic activity within different cells. The peaks have amplitude of the order of 20 mV, thus significantly greater than those of FIG. 3C. It should be noted that voltage Ve exhibits a decaying exponential characteristic owing to the fact that the electrode behaves with a low-pass response. The decaying exponential may be eliminated (or at least reduced) using a high-pass filter.

IV. Non-Limiting Examples of Stimulators

In some embodiments, impedance element 204 may be implemented as a switched capacitor. In some such embodiments, the magnitude of the current provided to the load may be set by setting the frequency output by frequency tuner 114.

IV.1 Basic Topology and Operating Principle

A capacitor CSC switched between DC voltages V1 and VOUT (V1>VOUT) with a non-overlapping two-phase (Φ1, Φ2) clock of frequency fSC (FIG. 4a) is equivalent to a resistor Reff=1/fSCCSC connecting the two DC voltages. The output current into the VOUT DC voltage source, averaged over a clock period, is given by IOUT=fSCCSC(V1−VOUT). As fSC can be varied over many orders of magnitude, IOUT can assume a wide range of values (with its minimum value being or example in the pA region). For example, with CSC=30 fF, V1−VOUT=0.6 V, and fSC increasing from 1 kHz by many orders of magnitude, IOUT can be tuned up from 18 pA by the same orders of magnitude. Capacitor CSC and switches Φ1, Φ2 may serve as impedance element 204.

First, a case in which the switched capacitor drives the electrode immersed in an electrolyte (which is modeled as a Faradaic resistor RL in shunt with a double layer capacitor CL) is considered (as in FIG. 4b). VOUT may not be constant and generally may vary as the current passes through the electrode, while V1 may be still a DC voltage. IOUT injected into the electrode can be still approximated as IOUT≈fSCCSC(V1−VOUT) but since VOUT varies with time, IOUT may not be set at a constant value. In other words, as IOUT linearly varies with VOUT, the small-signal output resistance ZOUT=|∂IOUT/∂VOUT| may be the same as the effective resistance of the switched capacitor, Reff. It should be appreciated that an infinite small-signal output resistance may be desired in current sources.

To promote a constant current, an active circuit (which may serve as the voltage follower 2021 of FIG. 2) can be designed around the switched capacitor (FIG. 4c). If the active circuit achieves a constant V1−VOUT by making V1 follow the change in VOUT and if it does not draw any appreciable current (IA≈0), IOUT≈fSCCSC(V1−VOUT) may still hold and may be set at a desired constant by fSC and CSC, independent of the generally changing VOUT. This may result in an infinite ZOUT.

FIG. 4d shows one non-limiting embodiment of the switched-capacitor current stimulator of FIG. 4c, where a PMOS source follower serves as the active circuit. Of course, other types of transistors may be used in lieu of or in addition to the PMOS in some embodiments (e.g., an NMOS). The V1 and VOUT nodes of the switched capacitor are connected to the source and gate of the PMOS transistor. V1 thus follows the variation of VOUT with V1−VOUT=VSG, the source-gate voltage of the transistor. In the absence of transistor channel length modulation, VSG is set by the transistor parameters and its bias current I0. Consequently, V1−VOUT=VSG is a constant independent of VOUT. At the same time, the source follower may draw a negligible current from the VOUT node due to the small gate capacitance of the PMOS transistor. Therefore, IOUT≈fSCCSC(V1−VOUT)=fSCCSCVSG is substantially independent of VOUT and can be set by fSC and CSC to a constant as needed.

In the presence of transistor channel length modulation, VSG may vary with VOUT although it may do so with a weak dependence. Thus IOUT˜fSCCSC(V1−VOUT)=fSCCSCVSG may be well controlled, almost independent of VOUT. The weak yet non-vanishing dependence of IOUT on VOUT can be quantified by evaluating ZOUT with the small-signal model of FIG. 4e, where ro,sf and ro,cm are respectively the output resistances of the PMOS transistor and the current (I0) bias circuit, and gm is the transconductance of the PMOS transistor:

Z OUT = ( r o , cm r o , sf + r o , cm R eff + r o , sf R eff + g m r o , cm r o , sf R eff ) / ( r o , cm + r o , sf ) ( g m r o / 2 ) × 1 / ( f SC C SC ) + r 0 / 2. ( 1 )

Here the second line is approximated by setting ro,sf≈ro,cm≡ro without losing essence and by using gmro>>1. As seen, ZOUT may be boosted from the effective resistance Reff=1/fSCCSC of the switched capacitor by a factor of gmro/2 (plus an extra term r0/2). In the absence of transistor channel length modulation (ro=∞), ZOUT=∞. By way of example and not limitation, setting gmro/2˜400, may cause output current variation of only 0.3% across the output voltage range.

IV.2 Circuit Dynamics

In analysing the dynamics of the current stimulator of FIG. 4d, we first consider the capacitive load CL only (RL=∞) (Sec. IV.3) and then add the effect of the resistive load RL (Sec. IV.4). In this example, table I (FIG. 14a) summarizes the key time constants associated with the main signal path, along with associated capacitances and resistances. Of course, values other than those shown in table I may be used.

IV.3 Dynamics with CL Only (RL=∞)

During the n-th clock phase Φ1 (n=1, 2, 3, . . . ), the switched capacitor may be disconnected from the VOUT node and connected to the V1 node via the switch on-resistance, RSW (FIG. 5a). Throughout this Φ1 phase, VOUT may be at a constant value αn, and thus V1 may be also maintained at a constant value αn+VSG; in contrast, the switched capacitor voltage, VSC, may exhibit a rapid upward transition from VOUTn to equalize with V1n+VSG (FIG. 5c), as CSC is charged with time constant τ1=RSWCSC<1 ns (Table I). This fast rise in VSC may occur in the very beginning of the Φ1 phase. After VSC settles, it may remain constant for the remainder of the Φ1 phase at VSC=V1n+VSG. The differential charge stored on CSC during this phase may be ΔQSC=CSCΔVSC=CSCVSG.

During the subsequent clock phase Φ2, the switched capacitor may be disconnected from the V1 node and connected to the VOUT node via the switch on-resistance, RSW (FIG. 5b). This re-configuration may rapidly redistribute the differential charge ΔQSC=CSCVSG between CSC and CL with time constant τ2=RSWCLCSC/(CL+CSC)≈RSWCSC<1 ns (Table I; note CL>>CSC), discharging CSC (lowering VSC) and charging CL (raising VOUT) until VSC=VOUT. Specifically, as shown in FIG. 5c, VOUT may rise from its initial value αn to final value αn+ΔVOUT where


ΔVOUT−ΔQSC/(CSC+CL)CSCVSG/(CSC+CL)≈CSCVSG/CL  (2)

while VSC may fall from its initial value αn+VSG to final value αn+ΔVOUT (V1 may follow the increase of VOUT to maintain the difference VSG). These changes of VSC and VOUT may occur during the early part of the phase Φ2 due to the short time constant τ2, and all three voltages (VSC, VOUT and V1) may remain constant throughout the remainder of the phase Φ2. The charge packet injected to CL during the charge redistribution in the early part of Φ2 may be ΔQOUT=CLΔVOUT. The output current IOUT driving CL may be due to this charge packet injection, and its average over a clock period may be given by


IOUT=fSCCLΔVOUT=fSCCSCVSG×[CL/(CSC+CL)]≈fSCCSCVSG,  (3)

which is the expression introduced earlier. The process may be repeated at each clock cycle (FIG. 5c), and VOUT may rise in a staircase manner. After many clock cycles, VOUT may eventually start to roll off when V1 becomes large enough to drive the current mirror transistor (not explicitly shown in the bias current (I0) source of FIG. 4d) into the triode regime. Specifically, this VOUT roll-off may occur when V1>VDD−VOV or when VOUT>VDD−VOV−VSG where VOV is the overdrive voltage of the current mirror transistor (FIG. 5d). In this region, VSG may decrease leading to a corresponding decrease in IOUT due to Eq. (3) and VOUT may be eventually clipped at VDD, at which point IOUT is diminished.

IV.4 Dynamics with CL and RL

Next, a load having a resistive component RL in parallel with CL is considered (FIG. 6a). Since RL>>RSW and CL>>CSC, the load's time constant τL=RLCL satisfies τL>>τ1, τ2 (Table I). Consequently, essentially the same rapid dynamics of the previous subsection may occur here too with time constant τ1 in phase Φ1 and with τ2 in phase Φ2, except that these fast dynamics may be overlaid with a decay of VOUT, and therefore V1=VOUT+VSG, in the background due to the slow discharge of CL through RL with time constant τL (FIG. 6b, bottom). VSC may also exhibit a slow background decay with time constant τL, equalized with V1 during most of phase Φ1 (after a rapid upward transition from VOUT to V1 with time constant τ1 in the beginning of Φ1) and equalized with VOUT during most of phase Φ2 (after a rapid downward transition from V1 to VOUT with time constant τ2 in the beginning of Φ2).

With repeated clock cycles VOUT may be a sequence of a rapid ΔVOUT up-step (time constant τ2) followed by a slow decay (time constant τL): see FIG. 6b, bottom. Here ΔVOUT in the beginning of each clock phase Φ2 may be again by Eq. (2). Therefore, IOUT injected into the electrode corresponds to the charge packet ΔQOUT CLΔVOUT injected into CL, and thus IOUT may remain the same as Eq. (3) (FIG. 6b, top). If we break down IOUT into current IOUT,R through RL and current IOUT,C through CL (IOUT=IOUT,R+IOUT,C) in phase Φ2, the rapid charging of CL in the beginning of the phase may be described by IOUT≈IOUT,C>0, while the background slow discharging of CL through RL maybe described by −IOUT,C≈IOUT,R (IOUT,C<0) with IOUT≈0 (FIG. 6b, top and middle).

In the initial clock cycles, the charging of CL by the charge packet injection ΔQOUT=CLΔVOUT per clock cycle may exceed its discharging through RL per clock cycle thus VOUT may rise, but once CL is sufficiently charged at later clock cycles, its charging and discharging may balance each other, and VOUT may reach a plateau (except ripples) (FIG. 6b, bottom; FIG. 6c). This evolution of VOUT into the steady state (neglecting the ripples) can be quantified by evaluating VOUT at t=n/fSC or at the end of n-th clock phase Φ2 as follows,

V OUT ( t ) = Δ V OUT k = 1 n exp ( - k f SC R L C L ) × ( - 1 2 f SC R L C L ) I OUT _ R L [ 1 - exp ( - t R L C L ) ] , ( 4 )

where fSCτL=fSCRLCL>>1. ΔVOUT may converge to IOUTRL in steady state (FIG. 6c). This is equivalent to flowing IOUT into the electrolyte through the resistance RL. In fact, the overall voltage response of the RLCL load to the switched-capacitor current stimulator captured by Eq. (4) (ignoring the ripples) may be the same as the voltage response of the RLCL load to an ideal step current with a magnitude IOUT (FIG. 6c).

As such, the current stimulator may be viewed, at least in some embodiments, as a source of constant current (or at least, substantially constant). At least in some biological applications, the biological tissue may have RC time constants≈1 ms, which will smoothen the high frequency ripples. It should be appreciate that, while resistance RL has been assumed as a constant in the analysis above, it may be a function of the current in some embodiments.

While the foregoing discussion has assumed IOUTRL<VDD−VOV−VSG, this need not necessarily be the case in all embodiments; if IOUTRL>VDD−VOV−VSG, VOUT may roll off and be clipped at VDD instead of saturating to IOUTRL.

IV.5 Representative Implementation

Some embodiments are directed to biphasic stimulators, which may be configured to drive current towards the cells and/or away from the cells. A representative biphasic stimulator is illustrated in FIGS. 7a-7c. In this configuration, transistor Mn (NMOS) may serve as voltage follower 2021 and transistor Mp (PMOS) may serve as voltage follower 2022. These biphasic stimulators allow for control of the current polarity by turning on either current source I0,p or I0,n. For example, with I0,p on and I0,n off, only PMOS transistor Mp is activated (FIG. 7b); in this regime, the PMOS source follower around the switched capacitor may set V1−VOUT=VSG,PMOS>0, thus enabling the switched capacitor to inject a positive current IOUT PMOS≈fSCCSCVSG,PMOS>0. On the other hand, with I0,n on and I0,p off, only NMOS transistor Mn is activated (FIG. 7c). The NMOS source follower around the switched capacitor may set V1−VOUT=−VGS,NMOS<0, injecting a negative current IOUT NMOS≈−fSCCSCVGS,NMOS<0. It should be appreciated that, while the illustrated implementation uses a PMOS transistor to drive current in one direction and an NMOS transistor to drive current in the other direction, other arrangements are also possible.

In some embodiments, current-based stimulators may be implemented using operational amplifiers. FIG. 7D illustrates an example of a stimulator including an operational amplifier. In this case, operational amplifier OA control the operations of transistors M1 and M2, which are arranged as voltage followers. Switched capacitor Cs serves as the impedance element. The output current Iout delivered by the stimulator of FIG. 7D is proportional to the switching frequency f, the capacitance Cs and the voltage across the switches VSC. Because VSC is set by the difference between VGS2 and VGS1 (which in turn may depend upon currents I2 and I1), this stimulator is able, at least in some embodiments, to deliver currents of less than 1 pA, when needed.

The inventors have appreciated that at least some of the electrogenic stimulators described herein may suffer from voltage ripples, as shown for example in FIG. 6C. In some circumstances, these voltage ripples may couple to and potentially negatively affect the operations of a receiver 108. In some embodiments, coupling of the voltage ripples to a receiver may be limited, or even eliminated, by 1) providing a sufficiently high frequency (e.g., greater than 1 MHz) to the switched capacitor serving as the impedance element, and 2) including a high-frequency cutting filter (e.g., a low-pass filter or a band-pass filter) having a sufficiently low cut-off frequency (less than the frequency driving the switched capacitor) in a receivers 108. In this way, the voltage ripples are blocked by the filter, and do not reach the receiver 108.

In some embodiments, the operational amplifier may be added to further reduce the effect of the ripples at the receiver. By including an operational amplifier in the current stimulator, the input frequency can be significantly increased to values above the cut-off frequency of the receiver filter. This is because, using the operational amplifier, the voltage VSC (and thus Iout) can be increased without having to necessarily increase the frequency f. In this way, the frequency f can be kept outside the band of the filter, thus suppressing the noise frequency. FIG. 7E illustrates another example of a current-based stimulator including an operational amplifier, according to some embodiments. In this case, transistors M5, M6, M7 and M8 serve as operational amplifier OA, and transistors M1 and M2 set the voltage VSC VGS2−VGS1. In this case, the value of VGS2 can be set based on VPMIR. By keeping I1 constant and adjust I2 through VPMIR, any suitable value of VSC can be obtained, thus providing a continuous tunability on the output current Iout.

The middle of FIG. 8 (solid box) shows a representative transistor-level schematic of the circuit of FIG. 7a. In this example, the core switched capacitor circuit uses two transmission gates and allows for the option of a 10 fF or 100 fF switched capacitance (control signals: EN_C1, EN_C2). Transistors M10 and M11, corresponding to Mn and Mp of FIG. 7a, are the complementary source follower transistors. As discussed above, channel length modulation may partially degrade the source following behavior, by rendering |VSG| of transistors M10 and M11 weakly dependent on VOUT.

The inventors have appreciated that the body effect can further weaken, at least in some embodiments, the source following behavior by increasing the |VSG| dependency on VOUT. As such, the body effect is limited, at least in some embodiments, by connecting the source and body terminals not only in the PMOS transistor M11 but also in the NMOS transistor M10; while such body-source connection is often not possible for NMOS transistors, some CMOS technologies allow for triple-well NMOS transistors, which in turn allows for the source-body connection at the expense of increased transistor area.

Transistors M1-M9 together with resistor RBIAS (˜750 kΩ in this example) may form a current bias network that realizes the I0,p and I0,n current sources of FIG. 7a. The M1-M5 network with RBIAS may set the reference current that is mirrored as I0,p by the PMOS pair M6-M7 and as I0,n by the NMOS pair M8-M9. In this bias network, either the PMOS mirror M6-M7 or the NMOS mirror M8-M9 is active (control signal: EN_POS) so that the overall circuit can work in either positive or negative injection mode, as explained in connection with FIG. 7 (the bias network can also be turned off entirely by using the control signal EN_SC). In this case, I0,n=I0,p=˜3 μA and |VSG|˜0.6 V for both M10 and M11. The theoretical maximum output current |IOUT MAX may be ˜1.5 μA, the half of I0,n=I0,p=˜3 μA, due to symmetric 50% duty cycle clock phases, Φ1 and Φ2 (FIG. 8, top). Furthermore, the clock phases Φ1 and Φ2 may be non-overlapping to prevent shoot through from V1 to VOUT. The master clock, CLK_IN can be selected from three clock inputs, CLK[1:3], thus enabling flexible control of fSC. All control signals may be stored locally or controlled externally through a n-bit (7-bit in the example of FIG. 8) transparent latch memory.

In the non-limiting example in which VDD=1.8 V and VSS=−1.8 V, |VSG|˜0.6 V for M10 and M11, IOUT may be nearly constant with only 0.3% simulated variation for VOUT within ±1.2 V for biphasic stimulation. By varying fSC between 1 kHz, which is near the high frequency cutoff of typical electrogenic cells, and 10 MHz, |IOUT| of Eq. (3) is varied from 6 pA to 60 nA for CSC=10 fF and from 60 pA to 0.6 μA for CSC=100 fF. This range of |IOUT| can cover both intracellular and extracellular stimulation. The ripple voltage ΔVOUT of Eq. (2) varies, in this example, from 0.6 mV to 60 mV depending on CSC and CL (Table I). This ΔVOUT is much less than typical stimulation voltages on the order of 0.1˜1 V and would be averaged out by the RC network of the cells.

The circuit of FIG. 8 was fabricated in a 0.18 m-CMOS technology (FIG. 9) in an active area of only 0.003 mm2. The memories, 7 bits in total, and logic occupy ˜0.001 mm2, current mirrors and source followers ˜0.001 mm2, bias resistor ˜0.0004 mm2, and the 10 fF and 100 fF capacitors of the standard MIM structure on the top metal layer together ˜0.0002 mm2.

IV.6 Experimental Results

The circuit of FIG. 8 was characterized by measuring IOUT of the current stimulator when VOUT is fixed to a variable DC voltage VREF (which may be an input to an off-chip operational amplifier in a negative feedback and may set by a data acquisition (DAQ) card) (FIG. 10a). The negative feedback loop of the operational amplifier comprises in the example a parallel RfCf network with either (Rf, Cf)=(100 MΩ, 10 pF) or (Rf, Cf)=(10 MΩ, 100 pF). Either of these transimpedance operational amplifiers configurations has a bandwidth of 100 Hz and thus is configured to average out the ripples in IOUT. The second set of Rf and Cf values may be configured to limit the voltage drop across the negative feedback path when IOUT is large.

FIG. 10b shows the measured positive and negative IOUT vs. fSC swept from 1 kHz to 10 MHz for VOUT=VREF=0 V. As illustrated, |IOUT| exhibits a linear dependence relative to fSC over the four decades of frequency. By fitting these curves, the following parameters can be extracted: VSG,PMOS=0.63 V, VGS,NMOS=0.56 V, and a parasitic capacitance Cp of 26 fF in shunt with the two alternate switched capacitances of 10 fF and 100 fF. In this case, the minimum |IOUT| is ˜20 pA at fSC=1 kHz with CSC=10 fF and Cp=26 fF and the maximum |IOUT| is ˜0.7 μA at fSC=10 MHz with Csc=100 fF and Cp=26 fF.

To demonstrate the weak dependence of IOUT on VOUT for a given frequency, VOUT=VREF is swept from −1.8 V to 1.8 V while fixing fSC at 100 kHz. The positive IOUT shows a flat response for VOUT between −1.8 V and 1.2 V and rolls off outside of this range; the negative IOUT shows a flat response between −1.2 V and 1.8 V and rolls off outside of this range (FIG. 10c). This demonstrates that the VOUT range for biphasic stimulation is ±1.2 V as expected. Furthermore, the measured variations of |IOUT| in the flat regions are within ˜4% for CSC=10 fF and even less for CSC=100 fF (FIG. 10d). Given the smaller variation of CSC=100 fF compared to CSC=10 fF and the similarity of the voltage dependence for both positive and negative injections, the observed max ˜4% variations of IOUT with VOUT, which is larger than the theoretical 0.3%, are mainly attributed to the voltage dependence of the parasitic capacitance. Nonetheless, even the measured 4% of current variation may be sufficient in most biological applications. In addition, the observed variations of IOUT with VOUT remains substantially the same when fSC is swept from 1 kHz to 10 MHz due to ZOUT's direct dependence on IOUT.

The same line of measurements of FIG. 10 was repeated across 25 different circuits to examine the variability. Results with fSC=1 kHz are displayed in FIG. 11. The IOUT averaged over the 25 devices is slightly increased relative to FIG. 10, because the measurements of FIG. 11 were performed after post-fabrication of platinum electrodes on the chip surface for the later characterization in electrolyte, which increased the parasitic capacitance of the MIM switched capacitors located near the surface. However, the chip-to-chip variations—whose evaluation is the key goal of the FIG. 11 measurements-exhibit a standard deviation of ˜1.0% for both positive and negative IOUT: this variability is due to process-dependent |VGS|, CSC, and parasitic capacitance.

The CMOS current stimulator was characterized with varying size of electrodes immersed in a salt solution containing NaCl (119 mM), KCl (5 mM), HEPES (20 mM), CaCl2 (2 mM), MgCl2 (2 mM), glucose (30 mM) and glycine (0.001 mM). FIG. 12a shows the measurement setup. Three current stimulator circuits are used, where the VOUT of each circuit is connected to an open pad on the top-most metal layer. Circular platinum electrodes are post-fabricated on the surface by first depositing Pt onto the open pads and subsequently depositing an insulating ˜500 nm of SiO2. Circular regions of Pt with diameters of 2 μm, 4 μm, and 8 μm are then selectively etched open. The theoretical capacitance, CL, of these 2 μm, 4 μm, and 8 μm Pt electrodes are 1.7 pF, 6.8 pF, and 27 pF, respectively, with voltage dependent Faradaic resistances RL, on the order of ˜50 MΩ to ˜2 GΩ. Polydimethylsiloxane (PDMS) microfluidic wells are attached to contain the salt solution. A DC input VREF to an off-chip transimpedance op-amp with a 100-Hz bandwidth is connected to an Ag/AgCl reference electrode to bias the salt solution at VREF=−0.2 V, which initializes the bias for VOUT approximately at 0 V in the middle between VDD=1.8 V and VSS=−1.8 V, with the difference between VOUT and VREF arising from the built-in potential of the electrode. The current measured through the reference electrode is the same as IOUT. An additional op-amp buffer is used to measure VOUT, sampling it at 100 kHz.

The parameters of the three circuits—such as fSC—are adjusted through the DAQ card to produce an equal magnitude (500 pA) of positive and negative currents (FIG. 12b). As a result, a 500-pA constant amplitude biphasic current pulse with a pulse duration of 50 ms is injected through each electrode. This injection of constant |IOUT| measured through the platinum and reference electrode (FIG. 12b, top)—which is averaged by the transimpedance op-amp and thus can be regarded as |IOUT|—occurs while the measured VOUT rises (FIG. 12b, bottom).

A 50 nA, 2-ms duration biphasic pulse is then injected to mimic an extracellular stimulation (FIG. 12c; for this higher pulse rate with the larger current magnitude, Rf=10 MΩ in parallel with Cf=100 pF is used for the transimpedance op-amp with two subsequent high-frequency boost circuits to extend the measurement bandwidth to ˜10 kHz). With this larger |IOUT| injection, the circuit with the 8-μm diameter electrode shows the same behavior as in FIG. 12b with no reduction in |IOUT| thanks to the relatively smaller RL. In contrast, for the two circuits with the 4-μm and 2-μm diameter electrodes with relatively larger RL's, |IOUT| is reduced (FIG. 12c, top) due to VOUT entering the regions of |VOUT|>1.2 V, as expected (FIG. 12c, bottom; the measured high-end VOUT is clipped at ˜0.9 V due to the saturation of the op-amp buffer).

The measurements of FIG. 13 are done with the same setup as in FIG. 12a and highlight the small amplitude current injection using the 2-μm diameter electrode immersed in the salt solution. fSC is increased from 0 Hz to 1 kHz and then decreased back to 0 Hz, in 200 Hz increments. This results in ˜5 μA step current increases/decreases for positive/negative injections (FIG. 13, top). For these measurements, the transimpedance op-amp circuit of FIG. 12a uses Rf=10 MΩ and Cf=100 pF but without high-frequency boost circuits; a moving window average having a window size of 10 ms is used to minimize the measurement noise. The positive current injection (top waveform in FIG. 13) reaches a maximum of 28 pA while the negative injection (bottom waveform) reaches a minimum of −25 pA. The ripple voltage can be seen (FIG. 13, middle), with ˜20 mV step size for both positive and negative injections.

Table II (FIG. 14b) summarizes the results obtained in the characterization described above.

It should be appreciated that the parameters provided in Table I are only representative, as other values may be used. For example, RSW may be between 1Ω and 10 kΩ, CSC may be between 0.1 fF and 10 nF, CL may be between 1 fF and 10 nF, RL may be between 1 kΩ and 100 GΩ, τ1 may be between 1 ps and 10 ns, τ2 may be between 1 ps and 10 ns, and τL may be between 100 ns and 10 ms. It should be further appreciated that not all embodiment are limited to CL>>CSC, RL>>RSW, and/or τL>>τ1, τ2.

V. Electrode Design

In some embodiments, the electrodes 1061, 1062 . . . 106N may be shaped as nanowires or as pluralities of nanowires. One example of an electrode being shaped as a plurality of nanowires is depicted in FIG. 15A, where a cell 104 is brought into contact with a substrate 1520 having an array of vertical nanowires 1530. The substrate may be planar or substantially planar in some embodiments. One or more of the ends 1540 of nanowires 1530 may be inserted into cell 104. As discussed herein, some or all of the nanowires may be individually addressable, e.g., for recording and/or for applying an electrical force to the cell. Nanowires that may be used can be formed of material with low cytotoxicity, such as silicon, silicon oxide, silicon nitride, silicon carbide, iron oxide, aluminum oxide, iridium oxide, tungsten, stainless steel, silver, platinum, and gold. Other suitable materials include aluminum, copper, molybdenum, tantalum, titanium, nickel, tungsten, chromium, or palladium. In some embodiments, the nanowire comprises or consists essentially of a semiconductor. Typically, a semiconductor is an element having semiconductive or semi-metallic properties (i.e., between metallic and non-metallic properties). An example of a semiconductor is silicon. Other non-limiting examples include elemental semiconductors, such as gallium, germanium, diamond (carbon), tin, selenium, tellurium, boron, or phosphorous. In other embodiments, more than one element may be present in the nanowires as the semiconductor, for example, gallium arsenide, gallium nitride, indium phosphide, cadmium selenide, etc.

The nanowires may be upstanding or substantially oriented vertically, with respect to the surface in some embodiments. For example, on average, the upstanding nanowires may form an angle with respect to a substrate of between about 80° and about 100°, between about 85° and about 95°, or between about 88° and about 92°. In some cases, the average angle is about 90°. Examples of such nanowires may be found in, for example, Int. Pat. Appl. Pub. No. WO 2016/112315, published Jul. 14, 2016, which is incorporated herein by reference in its entirety, and in U.S. Provisional Patent Application Ser. No. 62/580,126, which is incorporated herein by reference in its entirety. As used herein, the term “nanowire” (or “NW”) refers to a material in the shape of a wire or rod having a diameter in the range of 1 nm to 1 micrometer (μm). FIG. 15B illustrates a representative nanowire 1530 that is positioned in contact with an metal pad 1506 and a cell 104. The metal pad may be in communication with a corresponding receiver and a stimulator. As further illustrated in FIG. 15C, arrays of nanowires may be used to probe multiple cells. Stimulation and monitoring activity may be performed using CMOS circuits. While FIG. 15C illustrates a nanowire array for probing a neuronal network, nanowires of the types described herein can be used to probe any type of electrogenic cell network.

VI. Conclusion

Having thus described several aspects and embodiments of the technology of this application, it is to be appreciated that various alterations, modifications, and improvements will readily occur to those of ordinary skill in the art. Such alterations, modifications, and improvements are intended to be within the spirit and scope of the technology described in the application. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described. In addition, any combination of two or more features, systems, articles, materials, and/or methods described herein, if such features, systems, articles, materials, and/or methods are not mutually inconsistent, is included within the scope of the present disclosure.

Also, as described, some aspects may be embodied as one or more methods. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.

All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and/or ordinary meanings of the defined terms.

The indefinite articles “a” and “an,” as used herein in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean “at least one.” The phrase “and/or,” as used herein in the specification and in the claims, should be understood to mean “either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases.

As used herein in the specification and in the claims, the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase “at least one” refers, whether related or unrelated to those elements specifically identified.

In the claims, as well as in the specification above, all transitional phrases such as “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” “holding,” “composed of,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. The transitional phrases “consisting of” and “consisting essentially of” shall be closed or semi-closed transitional phrases, respectively.

Claims

1. An apparatus comprising:

an electrode configured to electrically contact a sample; and
a stimulation circuit coupled to the electrode, the stimulation circuit comprising: an impedance element having an input terminal and an output terminal coupled to the electrode; and a voltage follower coupled between the input terminal and the output terminal of the impedance element, the voltage follower being configured to maintain a substantially constant voltage between the input terminal and the output terminal of the impedance element.

2. The apparatus of claim 1, wherein the impedance element comprises a switched capacitor.

3. The apparatus of claim 2, further comprising a control circuit coupled to the switched capacitor, the control circuit having a frequency tuner.

4. The apparatus of claim 2, wherein the sample and the electrode form a load having a first capacitance, and wherein the switched capacitor has a second capacitance that is lower than the first capacitance.

5. The apparatus of claim 1, wherein the voltage follower comprises one or more transistors arranged in a source follower configuration.

6. The apparatus of claim 5, wherein the one or more transistors comprise a respective gate terminal coupled to the output terminal of the impedance element and a respective source terminal coupled to the input terminal of the impedance element.

7. The apparatus of claim 1, further comprising control circuitry configured to electrically couple the source follower to the input terminal of the impedance element during a first time period and to electrically couple the source follower to the output terminal of the impedance element during a second time period different than the first time period.

8. The apparatus of claim 1, wherein the electrode comprises a nanowire.

9. The apparatus of claim 1, wherein the sample comprises an electrogenic cell.

10. The apparatus of claim 1, wherein the sample is selected from the group consisting of a brain cell, a heart cell and an endocrine cell.

11. A method for electrically stimulating a sample, the method comprising:

generating an output current by: causing an input voltage of an impedance element to follow an output voltage of the impedance element, and coupling the output voltage to an electrode coupled to the sample; and
driving the sample with the output current.

12. The method of claim 11, wherein causing the input voltage of the impedance element to follow the output voltage of the impedance element comprises causing a first terminal of a transistor to follow a second terminal of the transistor.

13. The method of claim 11, wherein causing the input voltage of the impedance element to follow the output voltage of the impedance element comprises causing a source terminal of a transistor to follow a gate terminal of the transistor.

14. The method of claim 11, further comprising charging the impedance element during a first time period and discharging the impedance element during the second time period different than the first time period.

15. The method of claim 14, wherein driving the sample with the output current is performed in the second time period.

16. A method for monitoring a sample, the method comprising:

decreasing an input impedance of the sample by driving an electrode placed in contact with the sample with a first current;
stimulating the sample by driving the electrode with a second current, the first and second currents having different amplitudes; and
sensing electric signals generated by the sample with an amplifying circuit coupled to the electrode.

17. The method of claim 16, wherein driving the electrode comprises:

causing an input voltage of an impedance element to follow an output voltage of the impedance element, and coupling the output voltage to the electrode.

18. The method of claim 17, wherein causing the input voltage of the impedance element to follow the output voltage of the impedance element comprises causing a source terminal of a transistor to follow a gate terminal of the transistor.

19. The method of claim 16, wherein driving the output current through the electrode comprises driving a direct current (DC) for at least one minute.

20. The method of claim 16, wherein the electrode comprises a nanowire, and wherein the method further comprises contacting the sample with the nanowire.

Patent History
Publication number: 20210371846
Type: Application
Filed: Jul 6, 2018
Publication Date: Dec 2, 2021
Applicant: PRESIDENT AND FELLOWS OF HARVARD COLLEGE (Cambridge, MA)
Inventors: Donhee Ham (Sudbury, MA), Jeffrey T ABBOTT (Watertown, MA), Hongkun PARK (Lexington, MA), Wenxuan WU (Waltham, MA)
Application Number: 16/625,603
Classifications
International Classification: C12N 13/00 (20060101); C12M 1/42 (20060101); G01N 27/00 (20060101);