BURIED PAD FOR USE WITH GATE-ALL-AROUND DEVICE
A semiconductor structure includes an isolation structure formed on a substrate, a gate-all-around transistor structure formed on the isolation structure, a via electrically coupled to a gate terminal of the gate-all-around transistor structure, and a buried conductive pad formed within the isolation structure and electrically coupled to the via. The buried conductive pad can extend through the isolation structure in two dimensions, such as in both a vertical dimension and a horizontal dimension. The semiconductor structure can provide advantages in terms of routing flexibility, among other possible advantages.
Latest Taiwan Semiconductor Manufacturing Company Ltd. Patents:
The present disclosure generally relates to semiconductor devices and methods for fabricating semiconductor devices, and particularly to designing layouts of circuits that include semiconductor devices. As feature size of semiconductor devices continues to decrease, constraints with respect to use of space in circuit layouts generally arise. Semiconductor devices are used in a wide variety of electronics, and improvements regarding both production and performance of semiconductor devices are generally desired.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
The present disclosure provides a semiconductor structure such as implemented in an integrated circuit. The semiconductor structure includes a gate-all-around transistor structure that is electrically coupled to a buried conductive pad formed within an isolation structure using a via. The formation of the buried conductive pad within the isolation structure, such as a shallow trench isolation structure formed on a substrate, can provide advantages in terms of routing flexibility when designing a circuit layout.
Referring now to
Semiconductor structure 100 is shown to include a plurality of epitaxial regions 110. As illustrated in
Semiconductor structure 100 is also shown to include a plurality of channel structures 120. Channel structures 120 can be implemented using nanowires or nanosheets. For example, each channel structure can be implemented using three (or more or less) nanosheets formed using a semiconductor material such as indium gallium arsenide (InGaAs). Other suitable semiconductor materials can also be used to form the nanosheets. Likewise, each channel structure can be implemented using three (or more or less) nanowires formed using a semiconductor material such as indium gallium arsenide among other suitable semiconductor materials. Nanosheets generally have a more flat geometrical profile, whereas nanowires generally have a more round geometrical profile. It will be appreciated that channel structures 120 can also be implemented using other suitable structures in addition to nanosheets and nanowires. As illustrated in the top view of
Semiconductor structure 100 is also shown to include a plurality of gate structures 140. Gate structures 140 can be implemented as polysilicon or metal gate structures, for example. Each of the gate structures 140 is formed around a respective portion of each channel structure 120 in order to form individual gate-all around transistor structures along with corresponding epitaxial regions 110. Gate structures 140 can be formed using a variety of suitable processes, including chemical vapor deposition (CVD) and other suitable processes and combinations thereof. While not explicitly illustrated in
Semiconductor structure 100 is also shown to include a plurality of buried (or backside) conductive pads 130, as discussed in further detail below, and two cross sections: a cross section 150 and a cross section 160. Cross section 150 is cut in a vertical direction (from the top view shown in
Referring now to
Also shown in
Referring now to
Referring now to
Since channel structures 220 are formed on the isolation structure of semiconductor structure 200 and not within the isolation structure, added routing flexibility can be achieved for buried conductive pads 230. Since there are no fins (e.g. of a FinFET device) present within the isolation structure, buried conductive pads 230 can be formed in multiple directions within the isolation structure without any concern of running into the fins. Various possibilities for forming buried conductive pads 230 that extend in two dimensions within semiconductor structure 200, some of which are contemplated below with respect to example circuit layouts 300, 400, and 500. Moreover, due to this routing flexibility, circuit layouts with reduced area requirements for buried conductive pads 230 can be implemented since buried conductive pads 230 will not run into fins or other obstacles within the isolation structure.
Referring now to
In
Referring now to
Referring now to
In
Referring then to
Referring now to
In
Referring now to
As described in detail above, the present disclosure provides a semiconductor structure such as implemented in an integrated circuit. The semiconductor structure includes a gate-all-around transistor structure that is electrically coupled to a buried conductive pad formed within an isolation structure using a via. The formation of the buried conductive pad within the isolation structure, such as a shallow trench isolation structure formed on a substrate, can provide advantages in terms of routing flexibility when designing a circuit layout.
An implementation of the present disclosure is a semiconductor structure. The semiconductor structure includes an isolation structure formed on a substrate, a gate-all-around transistor structure formed on the isolation structure, a via electrically coupled to a gate terminal of the gate-all-around transistor structure, and a buried conductive pad formed within the isolation structure and electrically coupled to the via.
Another implementation of the present disclosure is a circuit. The circuit includes a shallow trench isolation structure formed on a substrate, a gate structure formed on the shallow trench isolation structure and around a plurality of nanowires, a via electrically coupled to the gate structure; and a buried conductive pad formed within the shallow trench isolation structure and electrically coupled to the via, the buried conductive pad extending in two dimensions within the isolation structure.
Yet another implementation of the present disclosure is another semiconductor structure. The semiconductor structure includes an isolation structure formed on a substrate, a gate structure formed on the isolation structure and around a plurality of nanosheets, a via electrically coupled to the gate structure, and a buried conductive pad formed within the shallow trench isolation structure and electrically coupled to the via, the buried conductive pad extending in both a horizontal dimension and a vertical dimension within the isolation structure.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims
1. A semiconductor structure, comprising:
- an isolation structure formed on a substrate;
- a gate-all-around transistor structure formed on the isolation structure;
- a via electrically coupled to a gate terminal of the gate-all-around transistor structure; and
- a buried conductive pad formed within the isolation structure and electrically coupled to the via.
2. The semiconductor structure of claim 1, wherein the buried conductive pad extends in both a horizontal dimension and a vertical dimension within the isolation structure.
3. The semiconductor structure device of claim 1, wherein the buried conductive pad extends in two dimensions within the isolation structure.
4. The semiconductor structure of claim 1, wherein the via comprises a first via and the gate-all-around transistor structure comprises a first gate-all-around transistor structure, the semiconductor structure further comprising a second gate-all-around transistor structure and a second via, wherein the second via is electrically coupled to the buried conductive pad and to a gate terminal of the second gate-all-around transistor structure.
5. The semiconductor structure of claim 1, wherein the via comprises a first via, the semiconductor structure further comprising a second via electrically coupled to a source terminal or a drain terminal of the gate-all-around transistor structure and to the buried conductive pad.
6. The semiconductor structure of claim 1, wherein the gate terminal of the gate-all-around transistor structure is formed around a plurality of nanowires.
7. The semiconductor structure of claim 1, wherein the gate terminal of the gate-all-around transistor structure is formed around a plurality of nanosheets.
8. A circuit, comprising:
- a shallow trench isolation structure formed on a substrate;
- a gate structure formed on the shallow trench isolation structure and around a plurality of nanowires;
- a via electrically coupled to the gate structure; and
- a buried conductive pad formed within the shallow trench isolation structure and electrically coupled to the via, the buried conductive pad extending in two dimensions within the shallow trench isolation structure.
9. The circuit of claim 8, wherein the gate structure is formed using polysilicon material and is a gate terminal of a gate-all-around transistor structure.
10. The circuit of claim 8, wherein the via comprises a first via and the gate structure comprises a first gate structure, the circuit further comprising a second via electrically coupled to the buried conductive pad and electrically coupled to a second gate structure.
11. The circuit of claim 8, wherein the via comprises a first via, the circuit further comprising a second via electrically coupled to an epitaxial region and electrically coupled to the buried conductive pad.
12. The circuit of claim 8, wherein the buried conductive pad extends in both a horizontal dimension and a vertical dimension within the isolation structure.
13. The circuit of claim 8, wherein the buried conductive pad comprises both a first section and a second section, the first section extending in one dimension within the shallow trench isolation structure and the second section extending in two dimensions within the shallow trench isolation structure.
14. The circuit of claim 10, further comprising a third via electrically coupled to an epitaxial region and electrically coupled to the buried conductive pad.
15. A semiconductor structure, comprising:
- an isolation structure formed on a substrate;
- a gate structure formed on the isolation structure and around a plurality of nanosheets;
- a via electrically coupled to the gate structure; and
- a buried conductive pad formed within the shallow trench isolation structure and electrically coupled to the via, the buried conductive pad extending in both a horizontal dimension and a vertical dimension within the isolation structure.
16. The semiconductor structure of claim 15, wherein the gate structure is formed using polysilicon material and is a gate terminal of a gate-all-around transistor structure.
17. The semiconductor structure of claim 15, wherein the via comprises a first via and the gate structure comprises a first gate structure, the circuit further comprising a second via electrically coupled to the buried conductive pad and electrically coupled to a second gate structure.
18. The semiconductor structure of claim 17, further comprising a third via electrically coupled to an epitaxial region and electrically coupled to the buried conductive pad.
19. The semiconductor structure of claim 15, wherein the via comprises a first via, the semiconductor structure further comprising a second via electrically coupled to an epitaxial region and electrically coupled to the buried conductive pad.
20. The semiconductor structure of claim 16, wherein the via comprises a first via, the semiconductor structure further comprising a second via electrically coupled to a source terminal or a drain terminal of the gate-all-around transistor structure and to the buried conductive pad.
Type: Application
Filed: May 26, 2021
Publication Date: Dec 1, 2022
Patent Grant number: 12027598
Applicant: Taiwan Semiconductor Manufacturing Company Ltd. (Hsinchu)
Inventors: Guo-Huei Wu (Tainan City), Pochun Wang (Hsinchu City), Chih-Liang Chen (Hsinchu City), Li-Chun Tien (Tainan City)
Application Number: 17/331,356