Photomask manufacturing process and semiconductor integrated circuit device manufacturing process using the photomask

- Hitachi, Ltd.

In order to improve the inspection efficiency of a photomask having a phase shifter pattern, the inspection of the photomask having the phase shifter pattern is divided into three steps, an anomaly extraction step, a first anomaly discrimination step and a second anomaly discrimination step. These inspection steps are performed at different inspection regions. An anomaly extraction station 7 for the anomaly extraction inspects the presence or absence of an anomaly for all the regions of the photomask 1. An anomaly discrimination station 8 for the anomaly discrimination classifies the content of the anomaly. A phase difference measurement station 9 for the anomaly discrimination measures the phase difference error.

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Claims

1. A method of manufacturing a phase shifting mask using one or more phase shifter edges as a part of a circuit pattern for transferring the circuit pattern onto an integrated circuit wafer by optical reduction projection exposure, the mask having a plurality of first transmission regions, each of which has a shifter edge portion therein, the method comprising the steps of:

(a) transforming the edge portion within each of the first transmission regions into a shield region by substituting a virtual shield region of a predetermined width for the edge portion on mask pattern data;
(b) optically capturing a two dimensional image of the phase shifting mask;
(c) comparing the image with the transformed mask pattern data, and thereby extracting defects in a circuit pattern over the mask; and
(d) in accordance with the result of the defect extraction, repairing at least a part of the extracted defects.

2. A method of manufacturing a phase shifting mask using a phase shifter edge as a part of a circuit pattern for transferring the circuit pattern onto an integrated circuit wafer by optical reduction projection exposure, the mask having a plurality of first transmission regions, each of which has a shifter edge portion therein, the method comprising the steps of:

(a) transforming each of the first transmission regions into a pair of divided transmission regions along the shifter edge on mask pattern data;
(b) verifying whether the phases of the pair of regions are inverted from each other with respect to each of the pairs of divided regions on the transformed mask pattern data;
(c) in accordance with the result of the verification, carrying out necessary correction to the verified mask pattern data; and
(d) in accordance with the corrected mask pattern data or mask drawing data transformed therefrom, drawing the circuit pattern over the mask by electron beam exposure.

3. A method of manufacturing a phase shifting mask having a circuit pattern for transferring the circuit pattern onto an integrated circuit wafer by optical reduction projection exposure, the mask having a plurality of transmission regions, the method comprising the steps of:

(a) extracting first defect portions on the circuit pattern over the mask by inspecting the mask;
(b) classifying the extracted first defect portions into a first group to measure each phase value at a separate phase value measuring mask stage and a second group not to measure each phase value at the phase value measuring mask stage;
(c) after step (b), transferring the mask to the phase value measuring mask stage, and then measuring the phase value of each of the defect portions of the first group; and
(d) in accordance with the result of the phase value measurement, repairing at least a part of the defect portions of the first group.

4. A method as recited in claim 3, wherein the classification step is carried out at a separate mask stage with respect to a mask stage at which the extraction step is carried out.

5. A method as recited in claim 4, wherein an inspection optical system of the classification step is substantially confocal.

6. A method as recited in claim 5, wherein the extraction step is carried out by comparing optically detected mask pattern data with mask design data or mask pattern data transformed therefrom.

7. A method as recited in claim 5, wherein the extraction step is carried out by comparing optically detected mask pattern data from a first part of the circuit pattern over the mask to be inspected with optically detected mask pattern data from a second part of the circuit pattern over the mask.

8. A method as recited in claim 4, wherein the extraction step is carried out by comparing optically detected mask pattern data with mask design data or mask pattern data transformed therefrom.

9. A method as recited in claim 4, wherein the extraction step is carried out by comparing optically detected mask pattern data from a first part of the circuit pattern over the mask to be inspected with optically detected mask pattern data from a second part of the circuit pattern over the mask.

10. A method as recited in claim 3, wherein an inspection optical system of the classification step is substantially confocal.

11. A method as recited in claim 10, wherein the extraction step is carried out by comparing optically detected mask pattern data with mask design data or mask pattern data transformed therefrom.

12. A method as recited in claim 10, wherein the extraction step is carried out by comparing optically detected mask pattern data from a first part of the circuit pattern over the mask to be inspected with optically detected mask pattern data from a second part of the circuit pattern over the mask.

13. A method as recited in claim 3, wherein the extraction step is carried out by comparing optically detected mask pattern data with mask design data or mask pattern data transformed therefrom.

14. A method as recited in claim 3, wherein the extraction step is carried out by comparing optically detected mask pattern data from a first part of the circuit pattern over the mask to be inspected with optically detected mask pattern data from a second part of the circuit pattern over the mask.

15. A method of manufacturing a phase shifting mask using one or more phase shifter edges as a part of a circuit pattern for transferring the circuit pattern over the mask onto an integrated circuit wafer by optical reduction projection exposure, the circuit pattern over the mask including a plurality of first transmission regions, each of which has a shifter edge portion therein, a plurality of second transmission regions, each of which has no shifter edge portions therein, and one or more light shield regions defining the first and second transmission regions, the method comprising the steps of:

(a) transforming the edge portion within each of the first transmission regions into a shield region by substituting a virtual shield region of a predetermined width for the edge portion on mask pattern data for mask design or mask fabrication;
(b) optically capturing an image of the circuit pattern of the phase shifting mask;
(c) comparing the image with the transformed mask pattern data, and thereby extracting defects in the circuit pattern over the mask; and
(d) in accordance with the result of the defect extraction, repairing at least a part of the extracted defects.

16. A method as recited in claim 15, wherein steps (b) to (d) are carried out to at least the first and second transmission regions.

17. A method of manufacturing a phase shifting mask using a phase shifter edge as a part of a circuit pattern for transferring the circuit pattern onto an integrated circuit wafer by optical reduction projection exposure, the circuit pattern over the mask including a plurality of first transmission regions, each of which has a shifter edge portion therein, a plurality of second transmission regions, each of which has no shifter edge portions therein, and one or more light shield regions defining the first and second transmission regions, the method comprising the steps of:

(a) transforming each of the first transmission regions into a pair of divided transmission regions along the shifter edge on mask pattern data;
(b) verifying whether the phases of the pair of regions are inverted from each other with respect to each of pairs of the divided regions and second transmission regions, the spacing of which pairs is not larger than a predetermined lower limit value on the transformed mask pattern data;
(c) in accordance with the result of the verification, carrying out necessary correction to the verified mask pattern data; and
(d) in accordance with the corrected mask pattern data or mask drawing data transformed therefrom, drawing the circuit pattern over the mask by electron beam exposure.
Referenced Cited
U.S. Patent Documents
5353116 October 4, 1994 Tanigawa et al.
5481624 January 2, 1996 Kamon
Foreign Patent Documents
62-59296 December 1987 JPX
4-229863 August 1992 JPX
4-321047 November 1992 JPX
4-328549 November 1992 JPX
4-345163 December 1992 JPX
6-35171 February 1994 JPX
Patent History
Patent number: 5786112
Type: Grant
Filed: Jun 17, 1996
Date of Patent: Jul 28, 1998
Assignee: Hitachi, Ltd. (Tokyo)
Inventors: Yoshihiko Okamoto (Kodaira), Yasuhiro Koizumi (Sayama)
Primary Examiner: S. Rosasco
Law Firm: Fay, Sharpe, Beall, Fagan, Minnich & McKee
Application Number: 8/664,865
Classifications
Current U.S. Class: Radiation Mask (430/5); Registration Or Layout Process Other Than Color Proofing (430/22)
International Classification: G03F 900;