Power surface mount light emitting die package

A light emitting die package includes a substrate, a reflector plate, and a lens. The substrate has traces for connecting an external electrical power source to a light emitting diode (LED) at a mounting pad. The reflector plate is coupled to the substrate and substantially surrounds the mounting pad, and includes a reflective surface to direct light from the LED in a desired direction. The lens is free to move relative to the reflector plate and is capable of being raised or lowered by the encapsulant that wets and adheres to it and is placed at an optimal distance from the LED chip(s). Heat generated by the LED during operation is drawn away from the LED by both the substrate (acting as a bottom heat sink) and the reflector plate (acting as a top heat sink).

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Description
PRIORITY

This application is a divisional of and claims domestic priority benefits under 35 U.S.C. §120 and commonly assigned U.S. patent application Ser. No. 10/446,532 to Ban P. Loh, now U.S. Pat. No. 7,264,378, filed May 27, 2003 and entitled “Power Surface Mount Light Emitting Die Package”, the entire contents of which is hereby incorporated by reference herein.

BACKGROUND

Example embodiments in general relate to packaging semiconductor devices which include light emitting diodes.

Light emitting diodes (LEDS) are often packaged within leadframe packages. A leadframe package typically includes a molded or cast plastic body that encapsulates an LED, a lens portion, and thin metal leads connected to the LED and extending outside the body. The metal leads of the leadframe package serve as the conduit to supply the LED with electrical power and, at the same time, may act to draw heat away from the LED. Heat is generated by the LED when power is applied to the LED to produce light. A portion of the leads extends out from the package body for connection to circuits external to the leadframe package.

Some of the heat generated by the LED is dissipated by the plastic package body; however, most of the heat is drawn away from the LED via the metal components of the package. The metal leads are typically very thin and has a small cross section. For this reason, capacity of the metal leads to remove heat from the LED is limited. This limits the amount of power that can be sent to the LED thereby limiting the amount of light that can be generated by the LED.

To increase the capacity of an LED package to dissipate heat, in one LED package design, a heat sink slug is introduced into the package. The heat sink slug draws heat from the LED chip. Hence, it increases the capacity of the LED package to dissipate heat. However, this design introduces empty spaces within the package that is be filled with an encapsulant to protect the LED chip. Furthermore, due to significant differences in CTE (coefficient of thermal expansion) between various components inside the LED package, bubbles tend to form inside the encapsulant or the encapsulant tends to delaminate from various portions within the package. This adversely affects the light output and reliability of the product. In addition, this design includes a pair of flimsy leads which are typically soldered by a hot-iron. This manufacturing process is incompatible with convenient surface mounting technology (SMT) that is popular in the art of electronic board assembly.

In another LED package design, the leads of the leadframe package have differing thicknesses extended (in various shapes and configurations) beyond the immediate edge of the LED package body. A thicker lead is utilized as a heat-spreader and the LED chip is mounted on it. This arrangement allows heat generated by the LED chip to dissipate through the thicker lead which is often connected to an external heat sink. This design is inherently unreliable due to significant difference in coefficient of thermal expansion (CTE) between the plastic body and the leadframe material. When subjected to temperature cycles, its rigid plastic body that adheres to the metal leads experiences high degree of thermal stresses in many directions. This potentially leads to various undesirable results such as cracking of the plastic body, separation of the plastic body from the LED chip, breaking of the bond wires, delaminating of the plastic body at the interfaces where it bonds to various parts, or resulting in a combination of these outcomes. In addition, the extended leads increase the package size and its footprint. For this reason, it is difficult to populate these LED packages in a dense cluster on a printed circuit board (PCB) to generate brighter light.

Another disadvantage of conventional leadframe design is that the thick lead cannot be made or stamped into a fine circuit for flip-chip mounting of a LED—which is commonly used by some manufacturers for cost-effective manufacturing and device performance.

SUMMARY

An example embodiment of the present invention is directed to a semiconductor die package including a substrate having conductive traces on a top surface thereof, and a light emitting diode (LED) mounted to the top surface of the substrate via a mounting pad. The mounting pad is electrically connected to the conductive traces on the substrate top surface. The package includes a reflector plate mechanically coupled to the substrate and substantially surrounding the mounting pad and LED, the reflector plate defining a reflection surface, and a lens substantially covering the mounting pad and LED.

Another example embodiment is directed to a semiconductor die package having a substrate, a light emitting diode (LED) mounted on the substrate via a mounting pad so that the LED is electrically connected to a top surface of the substrate, and a reflector plate coupled to the substrate and substantially surrounding the mounting pad and LED. The reflector plate has an opening there through. A lens is placed in the opening to substantially cover the mounting pad, LED and opening. The package includes an encapsulant covering the LED within at least part of the opening. The lens adheres to the encapsulant so that the lens floats on the encapsulant within the opening.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a perspective view of a semiconductor die package according to one embodiment of the present invention;

FIG. 1B is an exploded perspective view of the semiconductor package of FIG. 1A;

FIG. 2A is a top view of a portion of the semiconductor package of FIG. 1A;

FIG. 2B is a side view of a portion of the semiconductor package of FIG. 1A;

FIG. 2C is a front view of a portion of the semiconductor package of FIG. 1A;

FIG. 2D is a bottom view of a portion of the semiconductor package of FIG. 1A;

FIG. 3 is a cut-away side view of portions of the semiconductor package of FIG. 1A;

FIG. 4 is a side view of the semiconductor package of FIG. 1A with additional elements;

FIG. 5 an exploded perspective view of a semiconductor die package according to another embodiment of the present invention;

FIG. 6A is a top view of a portion of the semiconductor package of FIG. 5;

FIG. 6B is a side view of a portion of the semiconductor package of FIG. 5;

FIG. 6C is a front view of a portion of the semiconductor package of FIG. 5; and

FIG. 6D is a bottom view of a portion of the semiconductor package of FIG. 5.

 DETAILED DESCRIPTION

Example embodiments will now be described with reference to the FIGS. 1 through 6D. As illustrated in the Figures, the sizes of layers or regions are exaggerated for illustrative purposes and, thus, are provided to illustrate the general structures of the present invention. Furthermore, various aspects in the example embodiments are described with reference to a layer or structure being formed on a substrate or other layer or structure. As will be appreciated by those of skill in the art, references to a layer being formed “on” another layer or substrate contemplates that additional layers may intervene. References to a layer being formed on another layer or substrate without an intervening layer are described herein as being formed “directly on” the layer or substrate.

Furthermore, relative terms such as beneath may be used herein to describe one layer or regions relationship to another layer or region as illustrated in the Figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in the Figures is turned over, layers or regions described as “beneath” other layers or regions would now be oriented “above” these other layers or regions. The term “beneath” is intended to encompass both above and beneath in this situation. Like numbers refer to like elements throughout.

As shown in the figures for the purposes of illustration, example embodiments of the present invention are exemplified by a light emitting die package including a bottom heat sink (substrate) having traces for connecting to a light emitting diode at a mounting pad and a top heat sink (reflector plate) substantially surrounding the mounting pad. A lens covers the mounting pad. In effect, an example die package comprises a two part heat sink with the bottom heat sink utilized (in addition to its utility for drawing and dissipating heat) as the substrate on which the LED is mounted and connected, and with the top heat sink utilized (in addition to its utility for drawing and dissipating heat) as a reflector plate to direct light produced by the LED. Because both the bottom and the top heat sinks draw heat away from the LED, more power can be delivered to the LED, and the LED can thereby produce more light.

Further, the body of the die package itself may act as the heat sink removing heat from the LED and dissipating it. For this reason, the example LED die package may not require separate heat sink slugs or leads that extend away from the package. Accordingly, the LED die package may be more compact, more reliable, and less costly to manufacture than die packages of the prior art.

FIG. 1A is a perspective view of a semiconductor die package 10 according to one embodiment of the present invention and FIG. 1B is an exploded perspective view of the semiconductor package of FIG. 1A. Referring to FIGS. 1A and 1B, the light emitting die package 10 of the present invention includes a bottom heat sink 20, a top heat sink 40, and a lens 50.

The bottom heat sink 20 is illustrated in more detail in FIGS. 2A through 2D. FIGS. 2A, 2B, 2C, and 2D provide, respectively, a top view, a side view, a front view, and a bottom view of the bottom heat sink 20 of FIG. 1A. Further, FIG. 2C also shows an LED assembly 60 in addition to the front view of the bottom heat sink 20. The LED assembly 60 is also illustrated in FIG. 1B. Referring to FIGS. 1A through 2D, the bottom heat sink 20 provides support for electrical traces 22 and 24; for solder pads 26, 32, and 34; and for the LED assembly 60. For this reason, the bottom heat sink 20 is also referred to as a substrate 20. In the Figures, to avoid clutter, only representative solder pads 26, 32, and 34 are indicated with reference numbers. The traces 22 and 24 and the solder pads 32, 34, and 36 can be fabricated using conductive material. Further, additional traces and connections can be fabricated on the top, side, or bottom of the substrate 20, or layered within the substrate 20. The traces 22 and 24, the solder pads 32, 34, and 36, and any other connections can be interconnected to each other in any combination using known methods, for example via holes.

The substrate 20 is made of material having high thermal conductivity but is electrically insulating, for example, aluminum nitride (AlN) or alumina (Al2O3). Dimensions of the substrate 20 can vary widely depending on application and processes used to manufacture the die package 10. For example, in the illustrated embodiment, the substrate 20 may have dimensions ranging from fractions of millimeters (mm) to tens of millimeters. Although the present invention is not limited to particular dimensions, one specific embodiment of the die package 10 of the present invention is illustrated in Figures with the dimensions denoted therein. All dimensions shown in the Figures are in millimeters (for lengths, widths, heights, and radii) and degrees (for angles) except as otherwise designated in the Figures, in the Specification herein, or both.

The substrate 20 has a top surface 21, the top surface 21 including the electrical traces 22 and 24. The traces 22 and 24 provide electrical connections from the solder pads (for example top solder pads 26) to a mounting pad 28. The top solder pads 26 are portions of the traces 22 and 24 generally proximal to sides of the substrate 20. The top solder pads 26 are electrically connected to side solder pads 32. The mounting pad 28 is a portion of the top surface (including portions of the trace 22, the trace 24, or both) where the LED assembly 60 is mounted. Typically the mounting pad 28 is generally located proximal to center of the top surface 21. In alternative embodiments of the present invention, the LED assembly 60 can be replaced by other semiconductor circuits or chips.

The traces 22 and 24 provide electrical routes to allow the LED assembly 60 to electrically connect to the solder pads 26, 32, or 34. Accordingly, some of the traces are referred to as first traces 22 while other traces are referred to as second traces 24. In the illustrated embodiment, the mounting pad 28 includes portions of both the first traces 22 and the second traces 24. In the illustrated example, the LED assembly 60 is placed on the first trace 22 portion of the mounting pad 28 thereby making contact with the first trace 22. In the illustrated embodiment, a top of the LED assembly 60 and the second traces 24 are connected to each other via a bond wire 62. Depending on the construction and orientation of LED assembly 60, first traces 22 may provide anode (positive) connections and second traces 24 may comprise cathode (negative) connections for the LED assembly 60 (or vice versa).

The LED assembly 60 can include additional elements. For example, in FIGS. 1B and 2C, the LED assembly 60 is illustrated including an LED bond wire 62, an LED subassembly 64, and a light emitting diode (LED) 66. Such an LED subassembly 64 is known in the art and is illustrated for the purposes of discussing the invention and is not meant to be a limitation of the present invention. In the Figures, the LED assembly 60 is shown die-attached to the substrate 20. In alternative embodiments, the mounting pad 28 can be configured to allow flip-chip attachment of the LED assembly 60. Additionally, multiple LED assemblies can be mounted on the mounting pad 28. In alternative embodiments, the LED assembly 60 can be mounted over multiple traces. This is especially true if flip-chip technology is used.

The topology of the traces 22 and 24 can vary widely from the topology illustrated in the Figures while still remaining within the scope of the example embodiments of the present invention. In the Figures, three separate cathode (negative) traces 24 are shown to illustrate that three LED assemblies can be placed on the mounting pad 28, each connected to a different cathode (negative) trace; thus, the three LED assemblies may be separately electrically controllable. The traces 22 and 24 are made of conductive material such as gold, silver, tin, or other metals. The traces 22 and 24 can have dimensions as illustrated in the Figures and are of a thickness on the order of microns or tens of microns, depending on application. In an example, the traces 22 and 24 can be 15 microns thick. FIGS. 1A and 2A illustrate an orientation marking 27. Such markings can be used to identify the proper orientation of the die package 10 even after assembling the die package 10. The traces 22 and 24, as illustrated, can extend from the mounting pad 28 to sides of the substrate 20.

Continuing to refer to FIGS. 1A through 2D, the substrate 20 defines semi-cylindrical spaces 23 and quarter-cylindrical spaces 25 proximal to its sides. In the Figures, to avoid clutter, only representative spaces 23 and 25 are indicated with reference numbers. The semi-cylindrical spaces 23 and the quarter-cylindrical spaces 25 provide spaces for solder to flow-through and solidify-in when the die package 10 is attached to a printed circuit board (PCB) or another apparatus (not shown) to which the die package 10 is a component thereof. Moreover, the semi-cylindrical spaces 23 and the quarter-cylindrical spaces 25 provide convenient delineation and break points during the manufacturing process.

The substrate 20 can be manufactured as one individual section of a strip or a plate having a plurality of adjacent sections, each section being a substrate 20. Alternatively, the substrate 20 can be manufactured as one individual section of an array of sections, the array having multiple rows and columns of adjacent sections. In this configuration, the semi-cylindrical spaces 23 and quarter-cylindrical spaces 25 can be utilized as tooling holes for the strip, the plate, or the array during the manufacturing process.

Furthermore, the semi-cylindrical spaces 23 and the quarter-cylindrical spaces 25, combined with scribed grooves or other etchings between the sections, assist in separating each individual substrate from the strip, the plate, or the wafer. The separation can be accomplished by introducing physical stress to the perforation (semi through holes at a close pitch) or scribe lines made by laser, or premolded, or etched lines (crossing the semi-cylindrical spaces 23 and the quarter-cylindrical spaces 25) by bending the strip, the plate, or the wafer. These features simplify the manufacturing process and thus reduce costs by eliminating the need for special carrier fixtures to handle individual unit of the substrate 20 during the manufacturing process. Furthermore, the semi-cylindrical spaces 23 and the quarter-cylindrical spaces 25 serve as via holes connecting the top solder pads 26, the side solder pads 32, and the bottom solder pads 34.

The substrate 20 has a bottom surface 29 including a thermal contact pad 36. The thermal contact pad 36 can be fabricated using a material having a high thermally and electrically conductive properties such as gold, silver, tin, or another material including but not limited to precious metals.

FIG. 3 illustrates a cut-away side view of portions of the semiconductor package of FIGS. 1A and 1B. In particular, the FIG. 3 illustrates a cut-away side view of the top heat sink 40 and the lens 50. Referring to FIGS. 1A, 1B, and 3, the top heat sink 40 is made from a material having high thermal conductivity such as aluminum, copper, ceramics, plastics, composites, or a combination of these materials. A high temperature, mechanically tough, dielectric material can be used to overcoat the traces 22 and 24 (with the exception of the central die-attach area) to seal the traces 22 and 24 and provide protection from physical and environmental harm such as scratches and oxidation. The overcoating process can be a part of the substrate manufacturing process. The overcoat, when used, may insulate the substrate 20 from the top heat sink 40. The overcoat may then be covered with a high temperature adhesive such as thermal interface material manufactured by THERMOSET that bonds the substrate 20 to the top heat sink 40.

The top heat sink 40 may include a reflective surface 42 substantially surrounding the LED assembly 60 mounted on the mounting pad 28 (of FIGS. 2A and 2C). When the top heat sink 40 is used to dissipate heat generated by the LED in the die package 10, it can be “top-mounted” directly onto an external heat sink by an adhesive or solder joint to dissipate heat efficiently. In another embodiment, if heat has to be dissipated by either a compressible or non-compressible medium such as air or cooling fluid, the top heat sink 40 may be equipped with cooling fins or any feature that will enhance heat transfer between the top heat sink 40 and the cooling medium. In both of these embodiments, the electrical terminals and the bottom heat sink 20 of the die package 10 can still be connected to its application printed circuit board (PCB) using, for example, the normal surface-mount-technology (SMT) method.

The reflective surface 42 reflects portions of light from the LED assembly 60 as illustrated by sample light rays 63. Other portions of the light are not reflected by the reflective surface 42 as illustrated by sample light ray 61. Illustrative light rays 61 and 63 are not meant to represent light traces often use in the optical arts. For efficient reflection of the light, the top heat sink 40 is preferably made from material that can be polished, coined, molded, or any combination of these. Alternatively, to achieve high reflectivity, the optical reflective surface 42 or the entire heat sink 40 can be plated or deposited with high reflective material such as silver, aluminum, or any substance that serves the purpose. For this reason, the top heat sink 40 is also referred to as a reflector plate 40. The reflector plate 40 is made of material having high thermal conductivity if and when required by the thermal performance of the package 10. In the illustrated embodiment, the reflective surface 42 is illustrated as a flat surface at an angle, for example 45 degrees, relative to the reflective plate's horizontal plane. The example embodiments are not limited to the illustrated embodiment. For example, the reflective surface 42 can be at a different angle relative to the reflective plate's horizontal plane. Alternatively, the reflective plate can have a parabolic, toroid or any other shape that helps to meet the desired spectral luminous performance of the package.

The reflective plate 40 includes a ledge 44 for supporting and coupling with the lens 50. The LED assembly 60 is encapsulated within the die package 10 (of FIGS. 1A and 1B) using encapsulation material 46 such as, for example only, soft and elastic silicones or polymers. The encapsulation material 46 can be a high temperature polymer with high light transmissivity and refractive index that matches or closely matches refractive index of the lens 50, for example. The encapsulant 46 is not affected by most wavelengths that alter its light transmissivity or clarity.

The lens 50 is made from material having high light transmissivity such as, for example only, glass, quartz, high temperature and transparent plastic, or a combination of these materials. The lens 50 is placed on top of and adheres to the encapsulation material 46. The lens 50 is not rigidly bonded to the reflector 40. This “floating lens” design enables the encapsulant 46 to expand and contract under high and low temperature conditions without difficulty. For instance, when the die package 10 is operating or being subjected to a high temperature environment, the encapsulant 46 experiences greater volumetric expansion than the cavity space that contains it. By allowing the lens 50 to float up somewhat freely on top of the encapsulant 46, no encapsulant will be squeezed out of its cavity space. Likewise, when the die package 10 is subjected to a cold temperature, the encapsulant 46 will contract more than the other components that make up the cavity space for the encapsulant 46; the lens will float freely on top of the encapsulant 46 as the latter shrinks and its level drops. Hence, the reliability of the die package 10 is maintained over relatively large temperature ranges as the thermal stresses induced on the encapsulant 46 is reduced by the floating lens design.

In some embodiments, the lens 50 defines a recess 52 (See FIG. 3) having a curved, hemispherical, or other geometry, which can be filled with optical materials intended to influence or change the nature of the light emitted by the LED chip(s) before it leaves the die package 10. Examples of one type of optical materials include luminescence converting phosphors, dyes, fluorescent polymers or other materials which absorb some of the light emitted by the chip(s) and re-emit light of different wavelengths. Examples of another type of optical materials include light diffusants such as calcium carbonate, scattering particles (such as Titanium oxides) or voids which disperse or scatter light. Any one or a combination of the above materials can be applied on the lens 50 to obtain certain spectral luminous performance.

FIG. 4 illustrates the die package 10 coupled to an external heat sink 70. Referring to FIG. 4, the thermal contact pad 36 can be attached to the external heat sink 70 using epoxy, solder, or any other thermally conductive adhesive, electrically conductive adhesive, or thermally and electrically conductive adhesive 74. The external heat sink 70 can be a printed circuit board (PCB) or other structure that draws heat from the die package 10. The external heat sink can include circuit elements (not shown) or heat dissipation fins 72 in various configurations.

An example embodiment having an alternate configuration is shown in FIGS. 5 through 6D. Portions of this second embodiment are similar to corresponding portions of the first embodiment illustrated in FIGS. 1A through 4. For convenience, portions of the second embodiment as illustrated in FIGS. 5 through 6D that are similar to portions of the first embodiment are assigned the same reference numerals, analogous but changed portions are assigned the same reference numerals accompanied by letter “a,” and different portions are assigned different reference numerals.

FIG. 5 is an exploded perspective view of an LED die package 10a in accordance with other embodiments of the present invention. Referring to FIG. 5, the light emitting die package 10a of the present invention includes a bottom heat sink (substrate) 20a, a top heat sink (reflector plate) 40a, and a lens 50.

FIGS. 6A, 6B, 6C, and 6D, provide, respectively, a top view, a side view, a front view, and a bottom view of the substrate 20a of FIG. 5. Referring to FIGS. 5 through 6D, the substrate 20a includes one first trace 22a and four second traces 24a. Traces 22a and 24a are configured differently than traces 22 and 24 of FIG. 2A. The substrate 20a includes flanges 31 that define latch spaces 33 for reception of legs 35 of the reflector plate 40a, thereby mechanically engaging the reflector plate 40a with the substrate 20a.

The example embodiments of the present invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the exemplary embodiments of the present invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.

Claims

1. A semiconductor die package, comprising:

a substrate comprising conductive traces on a top surface thereof,
a light emitting diode (LED) mounted to the top surface of the substrate via a mounting pad, the mounting pad electrically connected to the conductive traces on the substrate top surface,
a reflector coupled to the substrate and substantially surrounding the mounting pad and LED, the reflector defining a reflection surface and the reflector comprising a ledge formed therein, and
a lens substantially covering the mounting pad and LED and being supported by the ledge of the reflector.

2. The semiconductor die package of claim 1, wherein the LED is encapsulated within an encapsulant.

3. The semiconductor die package of claim 2, wherein the encapsulant comprises an elastic material.

4. The semiconductor die package of claim 1, wherein the substrate comprises an electrically insulating material having high thermal conductivity.

5. The semiconductor die package of claim 1, wherein at least one trace extends from a top surface of the substrate to a side of the substrate.

6. The semiconductor die package of claim 1, further comprising an external heat sink coupled to the substrate.

7. The semiconductor die package of claim 6, wherein the substrate comprises a bottom side with a thermal contact pad for coupling with the external heat sink.

8. The semiconductor die package of claim 1, wherein the lens is composed of a high transparent plastic material.

9. The semiconductor die package of claim 1, wherein the reflector and substrate serve as corresponding top and bottom heat sinks for removing heat away from the LED during package operation.

10. The semiconductor die package of claim 1, wherein the substrate comprises flanges along at least one side thereof for mechanically engaging the reflector.

11. The semiconductor die package of claim 1, wherein the reflector is composed of a material having high thermal conductivity.

12. The semiconductor die package of claim 1, wherein the reflector comprises legs mechanically engaging the substrate for increased thermal contact area.

13. The semiconductor die package of claim 1, wherein the lens is composed of a material selected from a group consisting of glass, quartz, and a high temperature plastic material.

14. The semiconductor die package of claim 1, wherein the lens comprises luminescence converting phosphors.

15. The semiconductor die package of claim 1, wherein the lens comprises an optical diffusant.

16. The semiconductor die package of claim 1, wherein the lens comprises a phosphor.

17. The semiconductor die package of claim 1, wherein the lens comprises a material selected from a group consisting of glass and quartz.

18. The semiconductor die package of claim 1, wherein the reflector surrounds the mounting pad while leaving other portions of the top surface of the substrate and portions of the conductive traces exposed with the reflector partially defining an optical cavity.

19. A semiconductor die package, comprising:

a substrate comprising conductive traces on a top surface thereof,
a light emitting diode (LED) mounted to the top surface of the substrate via a mounting pad, the mounting pad electrically connected to the conductive traces on the substrate top surface,
a reflector coupled to the substrate and substantially surrounding the mounting pad and LED, the reflector defining a reflection surface and the LED being encapsulated within an encapsulant, and
a lens substantially covering the mounting pad and LED, wherein the lens is placed over and adheres to the encapsulant so that the lens floats on the encapsulant.

20. The semiconductor die package of claim 19, wherein the reflector surrounds the mounting pad while leaving other portions of the top surface of the substrate and portions of the conductive traces exposed with the reflector partially defining an optical cavity.

Referenced Cited
U.S. Patent Documents
3443140 May 1969 Jensen
3760237 September 1973 Jaffe
3875456 April 1975 Kano et al.
4152618 May 1, 1979 Abe et al.
4168102 September 18, 1979 Chida
4267559 May 12, 1981 Johnson et al.
4603496 August 5, 1986 Latz et al.
5119174 June 2, 1992 Chen
5173839 December 22, 1992 Metz, Jr.
5649757 July 22, 1997 Aleman
5785418 July 28, 1998 Hochstein
5789772 August 4, 1998 Jiang
5835661 November 10, 1998 Tai
5841177 November 24, 1998 Komoto et al.
5847507 December 8, 1998 Butterworth
5849396 December 15, 1998 Ali et al.
5857767 January 12, 1999 Hochstein
5869883 February 9, 1999 Mehringer et al.
5907151 May 25, 1999 Gramann et al.
5959316 September 28, 1999 Lowery
5982090 November 9, 1999 Kalmanash
5998925 December 7, 1999 Shimizu et al.
6060729 May 9, 2000 Suzuki et al.
6124635 September 26, 2000 Kuwabara
6155699 December 5, 2000 Miller et al.
6159033 December 12, 2000 Oka
6180962 January 30, 2001 Ishinaga
6238599 May 29, 2001 Gelorme et al.
6274924 August 14, 2001 Carey et al.
6281435 August 28, 2001 Maekawa
6307272 October 23, 2001 Takahashi et al.
6318886 November 20, 2001 Stopa et al.
6329706 December 11, 2001 Nam
6331063 December 18, 2001 Kamada et al.
6335548 January 1, 2002 Roberts et al.
6362964 March 26, 2002 Dubhashi et al.
RE37707 May 21, 2002 Bozzini et al.
6429513 August 6, 2002 Shermer, IV et al.
6444498 September 3, 2002 Huang et al.
6456766 September 24, 2002 Shaw et al.
6457645 October 1, 2002 Gardner, Jr.
6468821 October 22, 2002 Maeda et al.
6469322 October 22, 2002 Srivastava et al.
D465207 November 5, 2002 Williams et al.
6480389 November 12, 2002 Shie et al.
6492725 December 10, 2002 Loh et al.
6501103 December 31, 2002 Jory et al.
6525386 February 25, 2003 Mills
6531328 March 11, 2003 Chen
6541800 April 1, 2003 Barnett et al.
6559525 May 6, 2003 Huang
6610563 August 26, 2003 Waitl et al.
6614103 September 2, 2003 Durocher et al.
6672734 January 6, 2004 Lammers
6680491 January 20, 2004 Nakanishi et al.
6680568 January 20, 2004 Fujiwara et al.
6707069 March 16, 2004 Song et al.
6710544 March 23, 2004 Schliep
6759803 July 6, 2004 Sorg
6768525 July 27, 2004 Paolini et al.
6791259 September 14, 2004 Stokes et al.
6809347 October 26, 2004 Tasch et al.
6844903 January 18, 2005 Mueller-Mach et al.
6874910 April 5, 2005 Sugimoto et al.
6897486 May 24, 2005 Loh
6943380 September 13, 2005 Ota et al.
7044620 May 16, 2006 Van Duyn
7078728 July 18, 2006 Ishii et al.
7118262 October 10, 2006 Negley
7244965 July 17, 2007 Andrews et al.
7264378 September 4, 2007 Loh
7280288 October 9, 2007 Loh et al.
7456499 November 25, 2008 Loh et al.
20020084462 July 4, 2002 Tamai et al.
20020113244 August 22, 2002 Barnett et al.
20030057573 March 27, 2003 Sekine et al.
20030067264 April 10, 2003 Takekuma
20030168670 September 11, 2003 Roberts et al.
20030168720 September 11, 2003 Kamada
20030189829 October 9, 2003 Shimizu et al.
20030193080 October 16, 2003 Cabahug et al.
20030193083 October 16, 2003 Isoda
20030201451 October 30, 2003 Suehiro
20040004435 January 8, 2004 Hsu
20040079957 April 29, 2004 Andrews et al.
20040126913 July 1, 2004 Loh
20040173804 September 9, 2004 Yu
20040190304 September 30, 2004 Sugimoto et al.
20060083017 April 20, 2006 Wang
20060263545 November 23, 2006 Coenjarts
Foreign Patent Documents
199 45 919 March 2000 DE
0965493 December 1999 EP
1 059 678 December 2000 EP
1 087 447 March 2001 EP
1 179 858 February 2002 EP
1179858 February 2002 EP
1416219 May 2004 EP
1418628 May 2004 EP
JP 2003-124528 May 2004 EP
1680816 September 2009 EP
H09-083018 March 1997 JP
09274454 October 1997 JP
H10-321909 December 1998 JP
2001-177136 July 1999 JP
2000-13962 January 2000 JP
DE 19945919 March 2000 JP
2000-236116 August 2000 JP
EP 1059678 December 2000 JP
2001-036148 February 2001 JP
EP 1087447 March 2001 JP
2001-144333 May 2001 JP
2002319711 October 2002 JP
TW 517402 January 2003 JP
2003-110146 April 2003 JP
2003-124525 April 2003 JP
TW 533604 May 2003 JP
2003-197974 July 2003 JP
2002103977 October 2003 JP
2003298117 October 2003 JP
2003-318448 November 2003 JP
518775 January 2003 TW
WO 99/31737 June 1999 WO
WO2004023522 March 2004 WO
WO2005043627 May 2005 WO
Other references
  • Non-final Office Action for U.S. Appl. No. 11/689,868 dated Jan. 26, 2009.
  • Supplemental European Search Report dated Aug. 22, 2006.
  • United States Provisional Application entitled, “LED Package with a Long Stem Body as Heat-Spreader and a Small Footprint.” U.S. Appl. No. 60/431,501. Inventor: Ban Poh Loh. Filing date: Dec. 6, 2002. 10 pages.
  • United States Provisional Application entitled, “Leadframe Based LED or Semiconductor Package with Improved Heat Spreading.” U.S. Appl. No. 60/431,523. Inventor: Ban Poh Loh. Filing date: Dec. 6, 2002.
  • United States Patent Application Entitled: Power surface mount light emitting die package U.S. Appl. No. 10/692,351 Inventor(s): Peter Scott Andrews, Ban P. Loh, Durham filed Oct. 22, 2003 Published date: Apr. 29, 2004.
  • United States Patent Application Entitled: Composite leadframe LED package and method of making the same U.S. Appl. No. 10/721,654 Inventor(s): Ban P. Loh filed Nov. 25, 2003 Published date: Jul. 1, 2004.
  • United States Patent Application Entitled: LED package die having a small footprint U.S. Appl. No. 10/721,641 Inventor(s): Ban P. Loh filed Nov. 25, 2003 Published date: Jul. 1, 2004.
  • United States Patent Application Entitled: Power light emitting die package with reflecting lens and the method of making the same U.S. Appl. No. 10/861,929 Inventor(s): Ban P. Loh, Gerald H. Negley filed Jun. 4, 2004 Published date: Not yet published.
  • United States Patent Application Entitled: Composite optical lens with an integrated reflector U.S. Appl. No. 10/861,639 Inventor(s): Ban P. Loh, Gerald H. Negley filed Jun. 4, 2004 Published date: Not yet published.
  • Chinese Office Action with English translation dated Dec. 12, 2008.
  • International Search Report dated Feb. 27, 2007.
  • European Office Action for EP Appl. No. 08157294.3 dated Mar. 16, 2009.
  • Communication Under Rule 71(3) EPC (with enclosures) dated Apr. 24, 2009 regarding intent to grant European patent for Application No. 04795871.5-222.
  • Communication dated May 13, 2009 regarding no Opposition for European Application No. 03794564.9-2222 / Patent No. 1537603.
  • Office Action (with English Summary) dated Apr. 28, 2009 regarding Japanese Patent Application No. 2004-534428.
  • EPO Notice of Patent Grant dated Jun. 12, 2008.
  • Chinese Office Action with English translation dated Jul. 6, 2007.
  • European Search Report and Written Opinion dated Aug. 2, 2008.
  • Issued Chinese Patent dated Aug. 27, 2008.
  • Non-final Office Action for U.S. Appl. No. 11/694,046 dated Dec. 1, 2008.
  • Chinese Office Action (English Translation) dated Aug. 4, 2008.
  • European Examination Report dated Nov. 12, 2007.
  • Chinese Office Action dated Jul. 4, 2008.
  • European Notice of Publication dated Jul. 14, 2008.
  • Office Action with Restriction/Election Requirement dated Oct. 20, 2008 for U.S. Appl. No. 11/689,868.
  • Notice of Allowance dated Jul. 24, 2009 regarding U.S. Appl. No. 11/694,046.
  • Office Action dated Jul. 17, 2009 regarding U.S. Appl. No. 11/689,868.
  • International Search Report for PCT/US03/27421 dated Nov. 10, 2004.
  • International Search Report for PCT/US04/34768 dated Apr. 21, 2005.
  • Japanese Office Action for JP 2006-536764 (with English translation) dated Jun. 9, 2009.
  • Decision to Grant from European Patent Office for EP 1,680,816 dated Sep. 3, 2009.
  • Taiwan Office Action and Search Report dated Sep. 11, 2009 (English translation).
  • Chinese Office Action for CN 2004800309433 dated Sep. 25, 2009 (with English Translation).
  • Office Action for U.S. Appl. No. 11/153,724 dated Nov. 9, 2009.
  • European Search Report dated Nov. 23, 2009 for EP Application No. 09171045.9.
  • Japanese Office Action (English translation only) dated Feb. 2, 2010 for JP 2006-536764.
  • Japanese Office Action (with English translation) dated Feb. 23, 2010 for JP 2004-534428.
Patent History
Patent number: 7775685
Type: Grant
Filed: Feb 8, 2007
Date of Patent: Aug 17, 2010
Patent Publication Number: 20070138497
Assignee: Cree, Inc. (Durham, NC)
Inventor: Ban P. Loh (Durham, NC)
Primary Examiner: Ali Alavi
Attorney: Jenkins, Wilson, Taylor & Hunt, P.A.
Application Number: 11/703,721