With Provision For Cooling The Housing Or Its Contents Patents (Class 257/712)
  • Patent number: 10847448
    Abstract: A semiconductor device includes a semiconductor element, a first conductor bonded to an upper surface of the semiconductor element via a first solder layer, and a second conductor bonded to an upper surface of the first conductor via a second solder layer. The first conductor includes at least one groove formed in a stacking direction of the semiconductor element, the first conductor, and the second conductor on a side surface adjacent to the upper surface of the first conductor.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: November 24, 2020
    Assignee: DENSO CORPORATION
    Inventors: Keita Hatasa, Hiroyuki Takeda, Satoshi Takahagi
  • Patent number: 10847485
    Abstract: A method for forming a chip package structure is provided. The method includes bonding a chip to a first surface of a first substrate. The method includes forming a bump and a dummy bump over a second surface of the first substrate. The dummy bump is close to a first corner of the first substrate, and the dummy bump is wider than the bump. The method includes bonding the first substrate to a second substrate through the bump. The dummy bump is electrically insulated from the chip and the second substrate. The method includes forming a protective layer between the first substrate and the second substrate. The protective layer surrounds the dummy bump and the bump, and the protective layer is between the dummy bump and the second substrate.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: November 24, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shang-Yun Hou
  • Patent number: 10834848
    Abstract: Techniques that facilitate two-phase liquid cooling of an electronic device are provided. In one example, an apparatus, such as a cold plate device, comprises a first stackable layer and a second stackable layer. The first stackable layer comprises a first channel formed within the first stackable layer. The first channel comprises a first channel width and the first channel receives a coolant fluid via an inlet port of the apparatus. The second stackable layer comprises a second channel that provides a path for the coolant fluid to flow between the first channel and an outlet port of the apparatus. A width of the second channel increases along a flow direction of the coolant fluid that flows between the inlet port and the outlet port.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy Joseph Chainer, Pritish Ranjan Parida, Fanghao Yang
  • Patent number: 10826270
    Abstract: Systems and methods are described herein to thermally regulate laser diodes. During operation, the structure of a laser diode may generate heat, which will affect the stability and accuracy of the output wavelength of the laser diode. During an OFF stage, the structure of the laser diode will then lose heat, creating a thermal gradient as the laser diode is switched between operation and an OFF state. The systems and methods provide constant average heat and a stable thermal gradient by integrating a laser diode power-coupled supply and a heater onto a heatspreader, such that the output wavelength of a coupled laser diode may be stabilized.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: November 3, 2020
    Assignee: Automotive Coalition for Traffic Safety, Inc.
    Inventors: Derek Treese, Nicolas Koslowski, Michael Legge, Wolfgang Zeller
  • Patent number: 10825751
    Abstract: In semiconductor device, a substrate unit includes an insulating substrate, a first conductor substrate and a second conductor substrate which are disposed on one main surface of the insulating substrate and spaced apart from each other, and a third conductor substrate which is disposed on the other main surface opposite to the one main surface of the insulating substrate. A terminal is connected to a surface of a semiconductor element opposite to the first conductor substrate. The terminal extends from a region above the semiconductor element to a region above the second conductor substrate while being connected to the second conductor substrate. At least a part of the terminal, the substrate unit and the semiconductor element is sealed by a resin. The third conductor substrate is exposed from the resin.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: November 3, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yosuke Nakata, Tatsuya Kawase, Mikio Ishihara, Noboru Miyamoto
  • Patent number: 10818605
    Abstract: The circuit comprises at least one electronic chip (MT, MD), a laminated substrate and heat sink means, the chip being implanted in the substrate and the heat sink means being secured to opposing faces of the substrate. According to the invention, the heat sink means comprise heat-sink-forming bus-bars (BBH, BBL) mounted on the opposing faces of the substrate, each of said bus-bars being formed by a plurality of metal segments (BB1H, BB2H, BB3H, BB4H; BB1L, BB2L, BB3L) secured at spaced-apart positions and interconnected with one another and with a contact face of the electronic chip (MT, MD) by means of a metal layer (MEH, MEL).
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: October 27, 2020
    Assignees: INSTITUT VEDECOM, ELVIA PCB
    Inventors: Friedbald Kiel, Olivier Belnoue
  • Patent number: 10811335
    Abstract: A high efficiency satellite transmitter comprises an RF amplifier chip in thermal contact with a radiant cooling element via a heat conducting element. The RF amplifier chip comprises an active layer disposed on a high thermal conductivity substrate having a thermal conductivity greater than about 1000 W/mK, maximizing heat conduction out of the RF amplifier chip and ultimately into outer space when the chip is operating within a satellite under normal transmission conditions. In one embodiment, the active layer comprises materials selected from the group consisting of GaN, InGaN, AlGaN, and InGaAlN alloys. In one embodiment, the high thermal conductivity substrate comprises synthetic diamond.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: October 20, 2020
    Assignee: Akash Systems, Inc.
    Inventors: Felix Ejeckam, Tyrone D. Mitchell, Jr., Paul Saunier
  • Patent number: 10785863
    Abstract: A MMIC support and cooling structure having a three-dimensional, thermally conductive support structure having a plurality of surfaces and a circuit having a plurality of heat generating electrical components disposed on a first portion of the surfaces and interconnected by microwave transmission lines disposed on a second portion of the plurality of surfaces of the thermally conductive support structure.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: September 22, 2020
    Assignee: Raytheon Company
    Inventors: Susan C. Trulli, Christopher M. Laighton
  • Patent number: 10763253
    Abstract: A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hui-Yu Lee, Chi-Wen Chang, Jui-Feng Kuan, Yi-Kan Cheng
  • Patent number: 10756011
    Abstract: In a power semiconductor module, a first conductive layer including first to fourth electrodes are formed on one of principal surfaces of an insulating layer, and a conductive substrate functioning as a second conductive layer is formed on the other one of principal surfaces. Current paths are switched by controlling switching of a first transistor and a second transistor disposed on a surface of the first conductive layer thereby performing a power conversion. A capacitor is connected, in a region, between the first electrode and the second electrode. When a current flows in the region through the second conductive layer, a charging/discharging current occurs in the capacitor, which results in magnetic field cancellation.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: August 25, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tomotoshi Satoh, Hiroyuki Komeda, Kenichi Tanaka, Koichiro Fujita
  • Patent number: 10748833
    Abstract: A fan-out semiconductor package includes a semiconductor chip having an active surface on which connection pads are disposed and an inactive surface opposing the active surface, a heat dissipation member attached to the inactive surface of the semiconductor chip and having a thickness greater than a thickness of the semiconductor chip, an encapsulant encapsulating at least a portion of each of the semiconductor chip and the heat dissipation member, and a connection member disposed on the active surface of the semiconductor chip and including redistribution layers electrically connected to the connection pads, wherein the heat dissipation member is a complex of carbon and a metal.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: August 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seong Chan Park, Sang Hyun Kwon, Han Kim, Hye Lee Kim, Seung On Kang
  • Patent number: 10734302
    Abstract: A thermal electrical (TE) interface comprises a primary fiber thermal interface (FTI) having a first side configured to contact a heatsink, and a second side. The primary fiber thermal interface has a thickness ranging from 0.3 mm to 4 mm. A secondary fiber thermal interface (FTI) has a first side configured to contact the second side of the primary FTI, a second side configured to contact circuit components to dissipate heat from the circuit components through the first side of the primary FTI. The secondary fiber thermal interface has a thickness equal to or greater than the primary FTI.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: August 4, 2020
    Assignee: KULR TECHNOLOGY CORPORATION
    Inventors: Mysore Purushotham Divakar, Juergen Mueller, Michael Mo
  • Patent number: 10727199
    Abstract: An electronic device includes a circuit board, a semiconductor device package mounted on the circuit board, the semiconductor device package including a package substrate connected to the circuit board, a first semiconductor device and a second semiconductor device mounted side by side on the package substrate, and a molding surrounding a sidewall of the first semiconductor device and a sidewall of the second semiconductor device, the molding not covering a top surface of the first semiconductor device, and a heat dissipation structure on the semiconductor device package, the top surface of the first semiconductor device being in contact with the heat dissipation structure.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: July 28, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-hoon Kim, Kil-soo Kim, Kyung-suk Oh, Tae-joo Hwang
  • Patent number: 10714405
    Abstract: A semiconductor package may include a first semiconductor chip, a second semiconductor chip, and a thermal redistribution pattern which are disposed on a package substrate. The thermal redistribution pattern may include a first end portion disposed in a high temperature region adjacent to the first semiconductor chip, a second end portion disposed in a low temperature region adjacent to the second semiconductor chip, and an extension portion connecting the first end portion to the second end portion.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: July 14, 2020
    Assignee: SK hynix Inc.
    Inventor: Dae Woong Lee
  • Patent number: 10707193
    Abstract: According to one embodiment, a semiconductor device of an embodiment includes a substrate, a metal plate having a main portion having a first width in a first direction and a second width in a second direction orthogonal to the first direction, a first semiconductor chip located between the metal plate and the substrate, the first semiconductor chip having a third width in the first direction and a fourth width in the second direction, and a second semiconductor chip located between the first semiconductor chip and the substrate, wherein the first width is smaller than the third width, and the second width is smaller than the fourth width.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: July 7, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Tsukiyama, Hideo Aoki, Yoshiaki Goto
  • Patent number: 10707642
    Abstract: A housing for an electronic component, in particular for a laser diode, is provided. The housing includes a mounting area for the electronic component and has a lateral wall provided with a feedthrough for a light guide. The base wall of a basic body of the housing has both a heat sink for a thermoelectric cooler and a plurality of feedthroughs for pins for electrically connecting the electronic component.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: July 7, 2020
    Assignee: SCHOTT AG
    Inventors: Robert Hettler, Michelle Fang
  • Patent number: 10699978
    Abstract: A package encloses a power semiconductor die and has a package body with a package top side, package footprint side and package sidewalls. The die has first and second load terminals for blocking a blocking voltage. A lead frame structure electrically and mechanically couples the package to a support and includes an outside terminal extending out of the package footprint side and/or the sidewalls, and is electrically connected with the first load terminal. A top layer arranged at the package top side is electrically connected with the second load terminal. A creepage length between the electrical potential of the outside terminal and the electrical potential of the top layer is defined by a package body surface contour. The surface contour is formed at least by the package top side and package sidewall. At least one structural feature also forms the surface contour is configured to increase the creepage length.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: June 30, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Amirul Afiq Hud, Teck Sim Lee, Xaver Schloegel, Bernd Schmoelzer
  • Patent number: 10687447
    Abstract: Disclosed are exemplary embodiments of board level shields including thermal interface materials. Also disclosed are methods of applying thermal interface materials to board level shields.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: June 16, 2020
    Assignee: Laird Technologies, Inc.
    Inventors: Sri Talpallikar, Jason L. Strader
  • Patent number: 10679914
    Abstract: The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: June 9, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chieh-Lung Lai, Cheng-Yi Chen, Chun-Hung Lu, Mao-Hua Yeh
  • Patent number: 10672690
    Abstract: A method for manufacturing an electronic assembly features a semiconductor device with a first side and a second side opposite the first side to facilitate enhanced thermal dissipation. The first side has a first conductive pad. The second side has a primary metallic surface. By heating the assembly once, a first substrate (e.g. lead frame) is bonded to a first conductive pad via first metallic bonding layer; and second substrate (e.g., heat sinking circuit board) is bonded to a primary metallic surface via a second metallic bonding layer. In one configuration the second metallic bonding layer is composed of solder and copper, for example.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: June 2, 2020
    Assignee: DEERE & COMPANY
    Inventors: Robert K. Kinyanjui, Thomas J. Roan, Michael J. Zurn, Brad G. Palmer, Brij N. Singh
  • Patent number: 10663158
    Abstract: A lighting device or a lamp bulb (100, 200) with a smooth appearance comprises at least one light source (101); a heat sink component (104, 204), having a bottom (1043) and a side wall (1044) extending from the bottom (1044), wherein the bottom (1043) comprises a protrusion (1041) and wherein the at least one light source (101) thermally contacts the protrusion (1041) of the heat sink component (104, 204); and a cover provided on the sidewall (1044) opposite to the bottom (1043), thereby defining an air chamber (1051, 2051) between the cover, the side wall (1044), the bottom (1043) and the protrusion (1041).
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: May 26, 2020
    Assignee: SIGNIFY HOLDING B.V.
    Inventors: Theodoor Cornelis Treurniet, Yan Xiong, Simon Eme Kadijk, Howard Jiang, Robert Zou, Guangliang Guo
  • Patent number: 10667440
    Abstract: Provided herein are a heat sink module of an inverter module to power an electric vehicle. The heats sink module can include a heat sink body having a plurality of mounting holes, a fluid inlet and a fluid outlet. The heats sink module can include a cooling channel that can be fluidly coupled with the fluid inlet and the fluid outlet. The heats sink module can include an insulator plate having a first surface and a second surface. The second surface of the insulator plate can couple with a joining surface of the heat sink body to seal the cooling channel. The heats sink module can include a heat sink lid disposed over the insulator plate. The heat sink lid can have a plurality of mounting feet to couple with the mounting holes of the heat sink body to secure the heat sink lid to the heat sink body.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: May 26, 2020
    Assignee: SF MOTORS, INC.
    Inventors: Yunan Song, Colin Haag, Zhong Nie, Duanyang Wang, Yifan Tang
  • Patent number: 10665560
    Abstract: A semiconductor package includes an interconnect structure having a first surface and a second surface opposite to the first surface, at least one optical chip over the first surface of the interconnect structure and electrically coupled to the interconnect structure, an insulating layer contacting the second surface of the interconnect structure, and a molding compound over the first surface of the interconnect structure. The insulating layer includes a third surface facing the second surface of the interconnect structure and a fourth surface opposite to the third surface. At least an edge of the optical chip is covered by the molding compound.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: May 26, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chuei-Tang Wang, Chih-Chieh Chang, Yu-Kuang Liao, Hsing-Kuo Hsia, Chih-Yuan Chang, Jeng-Shien Hsieh, Chen-Hua Yu
  • Patent number: 10658304
    Abstract: A semiconductor device includes an electroconductive shielding layer, an isolation layer formed with a frame-shaped opening, a wiring layer on the isolation layer to be surrounded by the opening, a semiconductor element on the wiring layer with its back surface facing the wiring layer, electroconductive pillars spaced apart from the semiconductor element and standing on the wiring layer, and an electroconductive frame standing on an exposed region of the shielding layer through the opening, with the frame surrounding the semiconductor element and the electroconductive pillars. The semiconductor device further includes an electrically insulating sealing resin that covers the wiring layer and the semiconductor element, and the frame is configured to be electrically connected to an external ground terminal.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: May 19, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Hideaki Yanagida
  • Patent number: 10654709
    Abstract: A shielded semiconductor device is assembled using a lead frame having a die receiving area, leads disposed around the die receiving area, and a bendable strip formed in the die receiving area. Each lead has an inner lead end that is spaced from but near to one of the sides of the die receiving area and an outer lead end that is distal to that side of the die receiving area. An IC die is attached to the die receiving area and electrically connected to the inner lead ends of the leads. An encapsulant is formed over the die and the electrical connections and forms a body. The strip is bent to extend vertically to a top side of the body. A lid is formed on the top side of the body and is in contact with a distal end of the vertical strip.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: May 19, 2020
    Assignee: NXP USA, Inc.
    Inventors: Lee Fee Ngion, Zi-Song Poh, Michael B. Vincent
  • Patent number: 10626311
    Abstract: A curable thermally conductive grease 1a contains a curable liquid polymer, a thermally conductive filler (A) having an average particle diameter of less than 10 ?m, and a thermally conductive filler (B) having an average particle diameter of 10 ?m or more, the ratio by volume of the thermally conductive filler (A) to the thermally conductive filler (B), i.e., (A)/(B), being 0.65 to 3.02, and the curable thermally conductive grease having a viscosity of 700 Pa·s to 2070 Pa·s, in which after the curable thermally conductive grease is applied to the heat-generating body or the heat-dissipating body to a thickness of 5 mm, the curable thermally conductive grease has slump resistance in which the curable thermally conductive grease does not flow down when the heat-generating body or the heat-dissipating body is vertically arranged.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: April 21, 2020
    Assignee: SEKISUI POLYMATECH CO., LTD.
    Inventors: Gaku Kitada, Yasuyoshi Watanabe
  • Patent number: 10627174
    Abstract: Substantially aligned boron nitride nano-element arrays prepared by contacting a carbon nano-element array with a source of boron and nitrogen; methods for preparing such arrays and methods for their use including use as a heat sink or as a thermally conductivity interface in microelectronic devices.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: April 21, 2020
    Assignee: The Boeing Company
    Inventor: Robert W. Cumberland
  • Patent number: 10607914
    Abstract: A semiconductor package includes a first semiconductor package including a core member having a through-hole, a first semiconductor chip disposed in the through-hole and having an active surface with a connection pad disposed thereon, a first encapsulant for encapsulating at least a portion of the first semiconductor chip, and a connection member disposed on the active surface of the first semiconductor chip and including a redistribution layer electrically connected to the connection pad of the first semiconductor chip, a second semiconductor package disposed on the first semiconductor package and including a wiring substrate electrically connected to the connection member, at least one second semiconductor chip disposed on the wiring substrate, and a second encapsulant for encapsulating at least a portion of the second semiconductor chip, and a heat dissipation member covering a lateral surface of the second semiconductor package and exposing an upper surface of the second encapsulant.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: March 31, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae Hyun Lim, Han Kim, Yoon Seok Seo, Sang Jong Lee
  • Patent number: 10600759
    Abstract: In one or more embodiments, a semiconductor device includes a substrate, a first dielectric layer and a first conductive layer. The substrate includes a first surface and a second surface opposite the first surface. The first dielectric layer is on the first surface of the substrate. The first conductive layer is on the first surface of the substrate and includes a first portion on the first dielectric layer and a second portion surrounded by the first dielectric layer. The second portion of the first conductive layer extends from the first portion of the first conductive layer through the first dielectric layer to contact the first surface of the substrate.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: March 24, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chih-Pin Hung, Ying-Te Ou, Pao-Nan Lee
  • Patent number: 10559518
    Abstract: A method of forming metallic pillars between a fluid inlet and outlet for two-phase fluid cooling. The method may include; forming an arrangement of metallic pillars between two structures, the metallic pillars are electrically connected to metallic connecting lines that run through each of the two structures, the arrangement of metallic pillars located between a fluid inlet and a fluid channel, the fluid channel having channel walls running between arrangements of the metallic pillars and a fluid outlet, whereby a fluid passes through the arrangement of metallic pillars to flow into the fluid channel.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: February 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Timothy J. Chainer, Pritish R. Parida, Fanghao Yang
  • Patent number: 10542616
    Abstract: Provided are interconnect circuits for combined electrical and thermal energy transfer to devices connected to these circuits. Also provided are methods of fabricating such interconnect circuits. An interconnect circuit may include an electro-thermal conductor and at least one insulator providing support to different portions of the conductor with respect to each other. The insulator may include one or more openings for electrical connections and/or heat exchange with the electro-thermal conductor. The portions of the conductor may be electrically isolated from each other in the final circuit. Initially, these portions may be formed from the same conductive sheet, such as a metal foil having a thickness of at least about 50 micrometers. This thickness ensures sufficient thermal transfer in addition to providing excellent electrical conductance. In some embodiments, the conductor may include a surface coating to protect its base material from oxidation, enhancing electrical connections, and/or other purposes.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: January 21, 2020
    Assignee: CELLINK CORPORATION
    Inventors: Kevin Michael Coakley, Malcolm Brown
  • Patent number: 10534413
    Abstract: A heat conductor of electronic device 1 includes a heat conductive rubber having elasticity, a heat conductive plate having elasticity so as to be bending deformable, and heat conductive support members, which are disposed between a bottom face of a housing and a CPU in order in a direction from the CPU to the bottom face so as to abut the bottom face and the CPU. The heat conductive support members are configured to abut the heat conductive plate at a plurality of positions separated away from the heat conductive rubber in a surface direction. The heat conductive plate bending-deformed toward the bottom face is supported by the heat conductive rubber and the heat conductive support members.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: January 14, 2020
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Kazuhiro Shiraga
  • Patent number: 10529677
    Abstract: Various chip stack power delivery circuits are disclosed. In one aspect, an apparatus is provided that includes a stack of semiconductor chips that has an uppermost semiconductor chip and a lowermost semiconductor chip. A heat spreader is positioned on the uppermost semiconductor chip. A power transfer circuit is configured to transfer electric power from the heat spreader to the uppermost semiconductor chip.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: January 7, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Dmitri Yudanov
  • Patent number: 10515867
    Abstract: The present disclosure provides a semiconductor structure including a substrate, a first die over the substrate, a second die over the first die, a heat spreader having a sidewall facing toward and proximal to a sidewall of the first die, and a thermal interface material (TIM) between the sidewall of the first die and the sidewall of the heat spreader. A thermal conductivity of the heat spreader is higher than a thermal conductivity of the TIM.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chi-Hsi Wu, Wensen Hung, Tsung-Shu Lin, Shih-Chang Ku, Tsung-Yu Chen, Hung-Chi Li
  • Patent number: 10501031
    Abstract: Provided is a highly reliable electronic control device which has not only an effect of reducing costs but also an effect of facilitating a manufacturing process. To include a control board; a connector including a terminal connected to the control board; and a housing case to which the control board and the connector are fixed. The control board has a part sealed with a sealing resin. The connector is disposed at a position facing another part of the control board, being isolated from the sealing resin by the control board and the housing case.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: December 10, 2019
    Assignee: HITACHI AUTOMOTIVE SYSTEMS
    Inventors: Yujiro Kaneko, Yoshio Kawai
  • Patent number: 10490492
    Abstract: Some embodiments relate to a semiconductor package. The package includes a substrate having an upper surface and a lower surface. A first chip is disposed over a first portion of the upper surface of the substrate. A second chip is disposed over a second portion of the upper surface of the substrate. A first plurality of carbon nano material pillars are disposed over an uppermost surface of the first chip, and a second plurality of carbon nano material pillars are disposed over an uppermost surface of the second chip. A molding compound is disposed above the substrate, and encapsulates the first chip, the first plurality of carbon nano material pillars, the second chip, and the second plurality of carbon nano material pillars.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: November 26, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hao Tseng, Ying-Hao Kuo, Kuo-Chung Yee
  • Patent number: 10483132
    Abstract: A semiconductor device includes a passivation layer formed on a semiconductor substrate, a protective layer overlying the passivation layer and having an opening, an interconnect structure formed in the opening of the protective layer, a bump formed on the interconnect structure, and a molding compound layer overlying the interconnect structure and being in physical contact with a lower portion of the bump.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: November 19, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jen Lin, Tsung-Ding Wang, Chien-Hsun Lee
  • Patent number: 10481653
    Abstract: Provided herein are compositions made from a matrix and encapsulated phase change material particles dispersed therein, and electronic devices assembled therewith.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: November 19, 2019
    Assignee: Henkel IP & Holding GmbH
    Inventors: My N. Nguyen, Jason Brandi, Emilie Barriau
  • Patent number: 10475720
    Abstract: An integrated circuit architecture that provides a path having relatively low thermal resistance between one or more electronic devices and one or more thermal structures formed on an insulator layer on a substrate. Independent parallel thermal conduction paths are provided through the insulator layer, such as a buried oxide (“BOX”) layer, to allow heat to flow from the substrate layer to a collector column having a portion in common with a thermal structure disposed upon the BOX layer. In some cases, the substrate is a silicon substrate layer supporting the thermal structure and the collector column and a heat source, such as an electronic device (e.g., power amplifier, transistor, diode, resistor, etc.).
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: November 12, 2019
    Assignee: pSemi Corporation
    Inventors: Tero Tapio Ranta, Simon Edward Willard
  • Patent number: 10468379
    Abstract: A 3DIC structure includes a first die and a second die on a substrate and a bonding die. The boding die is electrically bonded to the first die and the second die. The bonding die covers a portion of a top surface of a scribe region between the first die and the second die.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: November 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzuan-Horng Liu, Hsien-Wei Chen, Jiun-Heng Wang, Ming-Fa Chen
  • Patent number: 10461013
    Abstract: A heat sink may include: a flat plate portion; a first protruding portion which is formed on an outer peripheral portion of the flat plate portion so as to surround a central portion of the flat plate portion and which protrudes in a thickness direction of the flat plate portion; an extending portion which extends outward from the flat plate portion; and a second protruding portion which is formed on the extending portion such that the first protruding portion is positioned between the second protruding portion and the central portion of the flat plate and which protrudes in the thickness direction of the flat plate portion.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: October 29, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Takuya Kurosawa
  • Patent number: 10461067
    Abstract: A method of reducing heat flow between IC chips and the resulting device are provided. Embodiments include attaching plural IC chips to an upper surface of a substrate; forming a lid over the IC chips; and forming a slit through the lid at a boundary between adjacent IC chips.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: October 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Janak Patel, Subramanian Srikanteswara Iyer, Daniel Berger
  • Patent number: 10461062
    Abstract: A semiconductor device has a first board (10) having a first electrically conducting layer (11) and a first electronic element (12) that is provided on the first electrically conducting layer (11); and an intermediate layer (20) being provided on the first board (10), and having a plurality of connectors and a resin board section, in which the plurality of connectors are fixed. The connector is exposed from the resin board section on the first board (10) side, and connected with the first electrically conducting layer (11) or the first electronic element (12).
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: October 29, 2019
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventor: Kosuke Ikeda
  • Patent number: 10454349
    Abstract: An inverter drive assembly includes a first array of inverters, a second array of inverters spaced from the first array of inverters and defining a plenum therebetween, and a crossover bus bar spanning the plenum and electrically connecting the first array of inverters to the second array of inverters. The crossover bus bar includes a first laminated bus section electrically connected to the first array of inverters, a second laminated bus section electrically connected to the second array of inverters, and a solid bus connection interconnecting the first laminated bus section with the second laminated bus section.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: October 22, 2019
    Assignee: GE GLOBAL SOURCING LLC
    Inventors: Sarit Ratadiya, Jacob Alan Hubbell, Ajith Kuttannair Kumar, Mark Murphy, Shreenath Shekar Perlaguri
  • Patent number: 10453776
    Abstract: A semiconductor device includes a semiconductor module including a semiconductor element, a passive element, a cooling member, a first conductive member and a second conductive member. The cooling member is disposed between the semiconductor module and the passive element. And a first conductive member and a second conductive member electrically connect the semiconductor module and the passive element. Furthermore, two or more aspects of at least one of the first conductive member and the second conductive member face the cooling member.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: October 22, 2019
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Ryosuke Usui, Tetsuzo Ueda
  • Patent number: 10448459
    Abstract: In some examples, a heating apparatus includes a light emitting diode (LED) array comprising an LED to heat a target object, and a heat sink thermally coupled to the LED array, to dissipate heat from the LED array, the heat sink comprising a plurality of refrigerant paths to pass a refrigerant through the heat sink in a plurality of different directions.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: October 15, 2019
    Assignee: HP SCITEX LTD.
    Inventor: Alex Veis
  • Patent number: 10446194
    Abstract: A memory module may include a module substrate having first and second surfaces facing away from each other, a plurality of first memories mounted over one or more of the first and second surfaces, one or more second memories and a controller each mounted over one of the first and second surfaces of the module substrate, and a plurality of batteries mounted over one or more of the first and second surfaces of the module substrate.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: October 15, 2019
    Assignee: SK hynix Inc.
    Inventors: Sang Kug Lym, Jong Bum Park
  • Patent number: 10424495
    Abstract: Semiconductor die assemblies having high efficiency thermal paths and molded underfill material. In one embodiment, a semiconductor die assembly comprises a first die and a plurality of second dies. The first die has a first functionality, a lateral region, and a stacking site. The second dies have a different functionality than the first die, and the second dies are in a die stack including a bottom second die mounted to the stacking site of the first die and a top second die defining a top surface of the die stack. A thermal transfer structure is attached to at least the lateral region of the first die and has a cavity in which the second dies are positioned. An underfill material is in the cavity between the second dies and the thermal transfer structure, and the underfill material covers the top surface of the die stack.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: September 24, 2019
    Assignee: Micron Technology, Inc.
    Inventors: David R. Hembree, William R. Stephenson
  • Patent number: 10418302
    Abstract: Provided are a heat dissipation substrate capable of improving heat dissipation properties of an electronic component, and an electric power steering device. In the heat dissipation substrate, a plurality of thermal vias are disposed at least in an electronic component projection region in which a region of a bottom surface portion of the electronic component is projected to a mounting surface in a direction perpendicular to the mounting surface, and a surface density of the thermal vias which occupy the mounting surface per unit area is at least partially different. The plurality of thermal vias are disposed so that the surface density of the thermal vias becomes the greatest in a dense region on an inner side of an edge portion of the electronic component projection region.
    Type: Grant
    Filed: November 24, 2016
    Date of Patent: September 17, 2019
    Assignee: NSK LTD.
    Inventor: Shigeru Shimakawa
  • Patent number: 10418306
    Abstract: A thermal interface for positioning between an electronics packaging and a target object includes a pad having a first side facing one of the electronics packaging and the target object and a second side. Carbon fibers having varying lengths extend from the second side towards the other of the electronics packaging and the target object.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: September 17, 2019
    Assignee: TRW AUTOMOTIVE U.S. LLC
    Inventor: Darryl Edwards