Abstract: Various embodiments include a heat sink comprising: a base plate with an assembly surface for an electronic component; and a cooling structure bonded to the base plate increasing a surface area of the heat sink. The base plate comprises a metal-ceramic composite with a ceramic phase and a metallic phase. The cooling structure comprises a metal. A bond between the cooling structure and the base plate consists of a purely metallic bond between the cooling structure and the metallic phase of the base plate.

Abstract: Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader.

Abstract: Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader.

Abstract: A power module, including: a first conductor, disposed at a first reference plane; a second conductor, disposed at a second reference plane, wherein projections of the first and second conductors on the first reference plane have a first overlap area; a third conductor, disposed at a third reference plane; a plurality of first switches and a plurality of second switches, wherein at least one of the first switches and at least one of the second switches that are located on a left side are alternatively disposed, at least one of the first switches and at least one of the second switches that are located on a right side are alternately disposed, and the left side and the right side of the first overlap area are oppositely disposed. Heat sources of the power module are evenly distributed and its parasitic inductance is low.

Abstract: A method of fabricating a semiconductor package structure is provided. The structure is configured to include a base substrate, a die placed on the base substrate, the die including a semiconductor device, a solder bump placed on one surface of the die to exhaust heat generated in the die to an outside; and a solder ball placed on other surface of the die facing the one surface to transmit a signal, which is produced by the semiconductor device of the die, to an external device.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.

Abstract: One or more die stacks are disposed on a redistribution layer (RDL) to make an electronic package. The die stacks include a die and one or more Through Silicon Via (TSV) dies. Other components and/or layers, e.g. interposes layers, can be included in the structure. An epoxy layer disposed on the RDL top surface and surrounds and attached to all the TSV die sides and all the die sides. Testing circuitry is located in various locations in some embodiments. Locations including in the handler, die, TSV dies, interposes, etc. Testing methods are disclosed, Methods of making including “die first” and “die last” methods are also disclosed. Methods of making heterogenous integrated structure and the resulting structures are also disclosed, particularly for large scale, e.g. wafer and panel size, applications.

Abstract: A semiconductor package includes a first substrate, a first chip structure and a second chip structure spaced apart from each other on the first substrate, a gap region being defined between the first and second chip structures, and a heat dissipation member covering the first chip structure, the second chip structure, and the first substrate, the heat dissipation member including a first trench in an inner top surface of the heat dissipation member, wherein the first trench vertically overlaps with the gap region and has a width greater than a width of the gap region, and wherein the first trench vertically overlaps with at least a portion of a top surface of the first chip structure or a portion of a top surface of the second chip structure.

Abstract: A metal member-equipped circuit board 21 includes: a printed circuit board 22 including a through hole 25; a metal member 30 including a shaft portion 31 that is inserted into the through hole 25, and a head portion 32 that is arranged outside the through hole 25, the head portion 32 having a diameter larger than a diameter A1 of the through hole 25, and a conductive bonding material 35 for bonding the shaft portion 31 and an inner wall of the through hole 25 to each other.

Abstract: The present disclosure relates to an MIMO antenna apparatus, and in particular, includes a PCB having at least one heat-generation element provided on one surface thereof, a first heat-dissipation part disposed to cover one surface of the PCB, having a through hole formed in a portion corresponding to the position provided with the heat-generation element, and having a plurality of vertical heat-dissipation fins formed to be extended in a direction perpendicular to the outside surface thereof, and a second heat-dissipation part detachably coupled to the through hole to contact one surface of the heat-generation element to receive heat from the heat-generation element and to dissipate heat at a long distance father than the first heat-dissipation part, thereby enhancing heat-dissipation performance and expanding universality of a product.

Abstract: A semiconductor device, the device including: a first silicon layer including a first single crystal silicon; a first metal layer disposed over the first silicon layer; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the plurality of transistors include a second single crystal silicon; a third metal layer disposed over the first level; a fourth metal layer disposed over the third metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 40 nm alignment error; and a via disposed through the first level, where the first level thickness is less than two microns.

Abstract: A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.

Abstract: Microelectronic assemblies that include a cooling channel, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a surface, a die having a surface, and a fluidic channel between the surface of the die and the surface of the package substrate, wherein a top surface of the fluidic channel is defined by the surface of the die and a bottom surface of the fluidic channel is defined by the surface of the package substrate. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a surface; and an interposer having a fluidic channel between the surface of the die and the surface of the package substrate.

Abstract: An integrated circuit assembly including a first die including a device side and a backside opposite the device side; and a second die including a plurality of fluidly accessible channels therein, wherein the second die is coupled to a backside of the first die. A method of fabricating an integrated circuit assembly including coupling a first die to a second die, wherein the first die includes a device side and an opposite backside, wherein the device side includes a plurality of integrated circuits and wherein the second die includes a plurality of fluidly accessible channels therein.

Abstract: A semiconductor device includes a substrate having a plurality of pads on a surface of the substrate, a semiconductor chip that includes a plurality of metal bumps connected to corresponding pads on the substrate, a first resin layer between the surface of the substrate and the semiconductor chip, a second resin layer between the substrate and the semiconductor chip and between the first resin layer and at least one of the metal bumps, and a third resin layer on the substrate and above the semiconductor chip.

Abstract: The invention relates to a combined pump-sensor arrangement having a substrate having a first main surface and an opposite second main surface. A package lid which defines a package having a measuring cavity is arranged on the first main surface of the substrate. Additionally, the pump-sensor arrangement has a micropump having a pump inlet and a pump outlet, the micropump being configured to suck in an analyte fluid present in the measuring cavity through the pump inlet and eject the same to an environment outside the measuring cavity via the pump outlet. Furthermore, the pump-sensor arrangement has a sensor for detecting at least one component of the analyte fluid present within the measuring cavity and movable by means of the micropump. In accordance with the invention, both the sensor and the micropump are commonly arranged on the first main surface of the substrate and within the measuring cavity.

Abstract: The subject disclosure relates to 3D microelectronic chip packages with embedded coolant channels. The disclosed 3D microelectronic chip packages provide a complete and practical mechanism for introducing cooling channels within the 3D chip stack while maintaining the electrical connection through the chip stack. According to an embodiment, a microelectronic package is provided that comprises a first silicon chip comprising first coolant channels interspersed between first thru-silicon-vias (TSVs). The microelectronic chip package further comprises a silicon cap attached to a first surface of the first silicon chip, the silicon cap comprising second TSVs that connect to the first TSVs. A second silicon chip comprising second coolant channels can further be attached to the silicon cap via interconnects formed between a first surface of the second silicon chip and the silicon cap, wherein the interconnects connect to the second TSVs.

Abstract: In one example, a method for redistribution layer (RDL) process is described. A substrate is provided. A dielectric layer is deposited on top of the substrate. The dielectric layer is patterned. A barrier and copper seed layer are deposited on top of the dielectric layer. A photoresist layer is applied on top of the barrier and copper seed layer. The photoresist layer is patterned to correspond with the dielectric layer pattern. Copper is electrodepositing in the patterned regions exposed by the photoresist layer. The photoresist layer is removed. The copper and seed barrier are etched.

Abstract: A semiconductor package substrate, a method for fabricating the same, and an electronic package having the same are provided. The method includes: providing a circuit structure having a first solder pad and a second solder pad; forming on the circuit structure a metal sheet having a first hole, from which the first solder pad is exposed, and a second hole, from which the second solder pad is exposed; and forming an insulation layer on the metal sheet and a hole wall of the second hole. A first conductive element that is to be grounded is disposed in the first hole and is in contact with the metal sheet and the first solder pad. Therefore, heat generated in a signal transmission process is dissipated by the metal sheet and the first conductive element.

Abstract: A package-on-package type package includes a lower semiconductor package and an upper semiconductor package. The lower semiconductor package includes a first semiconductor device including a through electrode, a second semiconductor device disposed on the first semiconductor device and including a second through electrode electrically connected to the first through electrode, a first molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device, a second molding member covering a sidewall of the first molding member, and an upper redistribution layer disposed on the second semiconductor device and electrically connected to the second through electrode.

Abstract: The present invention improves the performance of a thermoelectric conversion material and a thermoelectric conversion module. A thermoelectric conversion material has a mother phase containing a chimney ladder type compound comprising a first element of groups 4 to 9 and a second element of groups 13 to 15 and an additive phase existing at a grain boundary of the mother phase, the mother phase contains a third element to change a lattice constant of the chimney ladder type compound, and the additive phase contains the second element.

Abstract: A thermal interface material (TIM) structure for directing heat in a three-dimensional space including a TIM sheet. The TIM sheet includes a lower portion along a lower plane; a first side portion along a first side plane; a first upper portion along an upper plane; a first fold between the lower portion and the first side portion positioning the first side portion substantially perpendicular to the lower portion; and a second fold between the first side portion and the first upper portion positioning the first upper portion substantially perpendicular to the first side portion and substantially parallel to the lower portion.

Abstract: A semiconductor package according to an exemplary embodiment of the present disclosure may comprise a semiconductor chip comprising a chip pad; a redistribution layer electrically connected to the chip pad of the semiconductor chip; an external connection terminal electrically connected to the redistribution layer; a sealing material covering the semiconductor chip and configured to fix the semiconductor chip and the redistribution layer; an adhesive film positioned on the upper surface of the sealing material; and a heat sink formed on the upper surface of the adhesive film and having a stepped portion at the periphery thereof.

Abstract: A device includes a device layer comprising a first transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure includes a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a conductive line electrically connected to the source/drain region of the first transistor through the contact; and a thermal dissipation path thermally connected to the device layer, the thermal dissipation path extending to a surface of the second interconnect structure opposite the device layer. The thermal dissipation path comprises a dummy via.

Abstract: While the use of 2.5D/3D packaging technology results in a compact IC package, it also raises challenges with respect to thermal management. Integrated component packages according to the present disclosure provide a thermal management solution for 2.5D/3D IC packages that include a high-power component integrated with multiple lower-power components. The thermal solution provided by the present disclosure includes a mix of passive cooling by traditional heatsink or cold plate and active cooling by thermoelectric cooling (TEC) elements. Certain methods according to the present disclosure include controlling a temperature during normal operation in an IC package that includes a plurality of lower-power components located adjacent to a high-power component in which the high-power component generates a greater amount of heat relative to each of the lower-power components during normal operation.

Abstract: A power module, including: a first conductor, disposed at a first reference plane; a second conductor, disposed at a second reference plane, wherein projections of the first and second conductors on the first reference plane have a first overlap area; a third conductor, disposed at a third reference plane; a plurality of first switches, first ends of which are coupled to the first conductor; and a plurality of second switches, first ends of which are coupled to second ends of the first switches through the third conductor, and second ends of the second switches are coupled to the second conductor, wherein projections of minimum envelope areas of the first and second switches on the first reference plane have a second overlap area, and the first and second overlap areas have an overlap region. Heat sources of the power module are evenly distributed and its parasitic inductance is low.

Abstract: A circuit board structure includes a carrier and a patterned circuit layer. The patterned circuit layer is disposed on the carrier, and the patterned circuit layer has at least one fluid channel therein. The fluid channel has a heat absorption section and a heat dissipation section relative to the heat absorption section. A heat source is electrically connected to the patterned circuit layer, and the heat absorption section is adjacent to the heat source. The heat generated by the heat source is transferred from the patterned circuit layer to the heat absorption section of the fluid channel, and is transferred from the heat absorption section to the heat dissipation section for heat dissipation.

Abstract: A semiconductor package includes a first chip, a plurality of through vias and an encapsulant. The first chip has a first via and a protection layer thereon. The first via is disposed in the protection layer. The through vias are disposed aside the first chip. The encapsulant encapsulates the first chip and the plurality of through vias. A surface of the encapsulant is substantially coplanar with surfaces of the protection layer and the plurality of through vias.

Abstract: A semiconductor module includes: a first insulating plate; a second insulating plate is arranged above the first insulating plate; a first semiconductor device provided on an upper surface of the first insulating plate; a second semiconductor device provided on a lower surface of the second insulating plate; an insulating substrate including a third insulating plate arranged between the first insulating plate and the second insulating plate, and a conductor provided on the third insulating plate and connected to the first and second semiconductor devices; and sealing resin sealing the first and second semiconductor devices and the insulating substrate, wherein a withstand voltage of the third insulating plate is lower than withstand voltages of the first and second insulating plates.

Abstract: An electronic-component-mounted module has an electronic component, a first silver-sintered bonding layer bonded on one surface of the electronic component, a circuit layer made of copper or copper alloy and bonded on the first silver-sintered bonding layer, and a ceramic substrate board bonded on the circuit layer, and further has an insulation circuit substrate board with smaller linear expansion coefficient than the electronic component, a second silver-sintered bonding layer bonded on the other surface of the electronic component, and a lead frame with smaller linear expansion coefficient than the electronic component bonded on the second silver-sintered bonding layer; and a difference in the linear expansion coefficient between the insulation circuit substrate board and the lead frame is not more than 5 ppm/° C.

Abstract: An external connection terminal of a semiconductor module is provided. The external connection terminal includes a conductor having an upper surface and a lower surface; a plated layer configured to cover the upper surface of the conductor; and a nut provided on the lower surface-side of the conductor for receiving a screw penetrating the conductor. The plated layer includes a low contact resistance region overlapping a region in which the nut is provided, and a high contact resistance region that is a region except the low contact resistance region, as seen from above, and the plated layer includes a convex portion and a concave portion on a surface in the high contact resistance region.

Abstract: A method of fabricating a semiconductor package structure is provided. The structure is configured to include a base substrate, a die placed on the base substrate, the die including a semiconductor device, a solder bump placed on one surface of the die to exhaust heat generated in the die to an outside; and a solder ball placed on other surface of the die facing the one surface to transmit a signal, which is produced by the semiconductor device of the die, to an external device.

Abstract: A packaged semiconductor device includes a package substrate, a first semiconductor device on the package substrate, and at least one second semiconductor device that extends on and partially covers the first semiconductor device. A heat dissipating insulation layer is provided as a coating on the first and second semiconductor devices. A conductive heat dissipation member is provided, which extends upwardly from the heat dissipating insulation layer and on portions of the first and second semiconductor devices. A protective member is provided on the package substrate, to cover the first and second semiconductor devices and the conductive heat dissipation member. This protective member includes a first covering portion, which covers an upper surface of the conductive heat dissipation member.

Abstract: A method of fabricating a thermal management device. The method includes depositing a seed layer, using a seed layer depositing technique, on a side of a support base; growing a heat sink base layer on a side of the seed layer; depositing a hard mask on a side of the support base directly opposite that containing the seed and heat sink base layers; patterning the hard mask with a photoresist mask; etching the patterned hard mask with an etching technique, wherein the etching creates trenches in the underlying support base, exposing the seed layer; removing the hard mask with a hard mask removal technique; depositing a layer of photoresist on the heat sink base layer; growing heat sinks using a heat sink growth technique on the exposed seed layer; removing the photoresist layer with a photoresist layer removal technique; and removing the support base with a support base removal technique.

Abstract: An integrated circuit structure may be formed having a first integrated circuit device, a second integrated circuit device electrically coupled to the first integrated circuit device with a plurality of device-to-device interconnects, and at least one jumping drops vapor chamber between the first integrated circuit device and the second integrated circuit device wherein at least one device-to-device interconnect of the plurality of device-to-device interconnects extends through the jumping drops vapor chamber. In one embodiment, the integrated circuit structure may include three or more integrated circuit devices with at least two jumping drops vapor chambers disposed between the three or more integrated circuit devices. In a further embodiment, the two jumping drops chambers may be in fluid communication with one another.

Abstract: A method of forming a package assembly includes forming a first dielectric layer over a carrier substrate; forming a conductive through-via over the first dielectric layer; treating the conductive through-via with a first chemical, thereby roughening surfaces of the conductive through-via; and molding a device die and the conductive through-via in a molding material.

Abstract: A flip chip ball grid array (FCBGA) comprises a substrate, a cavity forming ring stiffener, an external heat sink, and a thermal interface material. The cavity forming ring stiffener is disposed on the substrate. The cavity forming ring stiffener has a segment which forms a cavity with the substrate, and exposes a top of the silicon chip. The external heat sink is disposed on the silicon chip and the segment of the cavity forming ring stiffener. A thermal interface material separates the segment of the cavity forming ring stiffener and the top of the silicon chip from the external heat sink and conducts heat from the silicon chip to the external heat sink.

Abstract: A semiconductor device of embodiments includes a substrate; a semiconductor chip provided above the substrate; a first ultrasonic bonding portion provided between the substrate and the semiconductor chip; a first terminal plate electrically connected to the semiconductor chip via the first ultrasonic bonding portion, the first ultrasonic bonding portion being provided on the substrate, and the first terminal plate having a first surface facing the semiconductor chip; and a first adhesive layer provided on the first surface, and the first adhesive layer containing a first adhesive.

Abstract: A main ceramic circuit board on which a semiconductor element is arranged is separate from a sub-ceramic circuit board on which a connection terminal is arranged. Accordingly, heat generated by the semiconductor element is conducted via the main ceramic circuit board and a base plate arranged thereunder and the sub-ceramic circuit board to the connection terminal. That is to say, it is difficult to conduct heat from the semiconductor element to the connection terminal, compared with a case where the connection terminal and the semiconductor element are arranged over the same ceramic circuit board.

Abstract: A cold plate structure, wherein a thermally active region includes fins metal injection molded in a single piece with a fin base sufficiently thin so that the active region mechanically conforms to the heat generating device that the cold plate cools. The fin base is formed as a common structure with a bottom wall of the cold plate, reducing thermal resistance between the device and the fins and also enhancing mechanical flexibility. Another cold plate structure can include multiple thermally active regions, with flexible outer walls and a reduced thickness between active regions, allowing for position variation between multiple heat generation devices that are cooled by the common cold plate. A common base having multiple physically separate active regions can be metal injection molded in a single step, or bases of multiple active regions can be formed individually and joined later to form a common single cold plate structure.

Abstract: An object of the present invention is to improve assemblability of a power semiconductor device. A power semiconductor device includes a plurality of submodules that includes a semiconductor element interposed between a source conductor and a drain conductor, a sense wiring that transmits a sense signal of the semiconductor element, and an insulating portion at which the sense wiring and the sense conductor are arranged, and a source outer conductor that is formed to surround the source conductor and is joined to the source conductor in each of the plurality of submodules. Each source conductor included in the plurality of submodules includes protrusion portions that are formed toward the sensor wiring from the source conductor, are connected to the sense wiring, and define a distance between the sense wiring and the source outer conductor.

Abstract: The present disclosure is directed to systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A thermally conductive member that includes at least one thermally conductive member may be disposed between the first semiconductor package and the second semiconductor package. The thermally conductive member may include: a single thermally conductive element; multiple thermally conductive elements; or a core that includes at least one thermally conductive element. The thermally conductive elements are thermally conductively coupled to an upper surface of the first semiconductor package and to the lower surface of the second semiconductor package to facilitate the transfer of heat from the first semiconductor package to the second semiconductor package.

Abstract: The Invention pertains to a heat sink comprising a substantially planar solid slab, provided with a plurality of fluid flow channels, said plurality of fluid flow channels being formed so as to channel a coolant from an inlet to an outlet of said slab, wherein said plurality of channels includes at least two main channels interconnected by at least a plurality of bridging channels that do not branch out further between their respective points of attachment to said main channels, wherein said bridging channels have a cross section that locally increases in the direction of flow, and wherein said bridging channels have a cross section that locally decreases in the direction of flow, downstream of said local increase in cross section. The invention also pertains to a method for producing a heat sink.

Abstract: A single and multi-layer flat glass-sensor structure and method of making the flat glass-sensor structure. The flat glass sensor structure comprises at least one flat glass layer, a sensor and a heater. The flat glass layer has a plurality of cutouts that are configured to “suspend” the sensor on top of or in plane with the flat glass layer. The sensor is an electrochemical wafer with at least one sensory element and flat glass connectors. Each flat glass connector is in minimal contact with at least one sensory sub-area. The heater is a resistive heating element that is on top of or in plane with the flat glass layer configured to heat the sensor. The flat glass connectors are configured to provide support for electrical leads to the heater and membrane. The flat glass connectors are also configured to provide temperature insulation of the suspended sensor.

Abstract: A power module substrate includes an insulating substrate and a metal plate. The metal plate is joined to the insulating substrate with a brazing material in between. As to surface roughness of a lateral surface of the metal plate in a thickness direction, the surface roughness of at least a corner part farthest from a center of the metal plate in plan view is larger than the surface roughness of plane parts sandwiching the corner part.

Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.

Abstract: A power conversion apparatus includes a semiconductor element, a plurality of lead frames, a flow-passage formation body, an insulating portion, a metal joining material, and a resin sealing portion. The plurality of lead frames are electrically connected to the semiconductor element. The flow-passage formation body forms a coolant flow passage in which a coolant flows. The insulating portion is arranged between the lead frame and the flow-passage formation body to provide insulation between the lead frame and the flow-passage formation body. The metal joining material joins the insulating portion and the flow-passage formation body. The resin sealing portion seals the semiconductor element and the lead frames. The semiconductor element and the lead frames are integrated with the flow-passage formation body to form a semiconductor cooling assembly by the resin sealing portion.

Abstract: Electronic assemblies for thermoelectric generation are disclosed. In one embodiment, an electronic assembly includes a substrate having a first surface and a second surface, and a conductive plane and a plurality of thermal guide traces position on the first surface of the substrate. The conductive plane includes a plurality of arms radially extending from a central region. The plurality of thermal guide traces surrounds the conductive plane, and is shaped and positioned to guide heat flux present on or within the substrate toward the central region of the conductive plane. The electronic assembly may also include a thermoelectric generator device thermally coupled to the central region of the conductive plane, and a plurality of heat generating devices coupled to the second surface of the substrate.

Abstract: A pyrolytic graphite (PG) substrate and laser diode package includes a substrate body having a PG crystalline structure with a basal plane oriented at a pre-determined orientation angle as measured from a longitudinal axis of a heat generating material, such as a laser diode, mounted on a surface of the PG substrate, so that a coefficient of thermal expansion (CTE) of the PG substrate is substantially matched with a CTE of the material.

Abstract: Embodiments provide a light emitting device package including a package body having a through-hole; a radiator disposed in the through-hole and including an alloy layer having Cu; and a light emitting device disposed on the radiator, wherein the alloy layer includes at least one of W or Mo, and wherein the package body includes cavity including a sidewall and a bottom surface, and wherein the through-hole is formed in the bottom surface.