With Provision For Cooling The Housing Or Its Contents Patents (Class 257/712)
  • Patent number: 11521914
    Abstract: Microelectronic assemblies that include a cooling channel, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a surface, a die having a surface, and a fluidic channel between the surface of the die and the surface of the package substrate, wherein a top surface of the fluidic channel is defined by the surface of the die and a bottom surface of the fluidic channel is defined by the surface of the package substrate. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a surface; and an interposer having a fluidic channel between the surface of the die and the surface of the package substrate.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: December 6, 2022
    Assignee: Intel Corporation
    Inventors: Zhimin Wan, Cheng Xu, Yikang Deng, Junnan Zhao, Ying Wang, Chong Zhang, Kyu Oh Lee, Chandra Mohan Jha, Chia-Pin Chiu
  • Patent number: 11508645
    Abstract: An integrated circuit assembly including a first die including a device side and a backside opposite the device side; and a second die including a plurality of fluidly accessible channels therein, wherein the second die is coupled to a backside of the first die. A method of fabricating an integrated circuit assembly including coupling a first die to a second die, wherein the first die includes a device side and an opposite backside, wherein the device side includes a plurality of integrated circuits and wherein the second die includes a plurality of fluidly accessible channels therein.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: November 22, 2022
    Assignee: Intel Corporation
    Inventors: Chandra M. Jha, Je-Young Chang
  • Patent number: 11502057
    Abstract: A semiconductor device includes a substrate having a plurality of pads on a surface of the substrate, a semiconductor chip that includes a plurality of metal bumps connected to corresponding pads on the substrate, a first resin layer between the surface of the substrate and the semiconductor chip, a second resin layer between the substrate and the semiconductor chip and between the first resin layer and at least one of the metal bumps, and a third resin layer on the substrate and above the semiconductor chip.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: November 15, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Soichi Homma
  • Patent number: 11486381
    Abstract: The invention relates to a combined pump-sensor arrangement having a substrate having a first main surface and an opposite second main surface. A package lid which defines a package having a measuring cavity is arranged on the first main surface of the substrate. Additionally, the pump-sensor arrangement has a micropump having a pump inlet and a pump outlet, the micropump being configured to suck in an analyte fluid present in the measuring cavity through the pump inlet and eject the same to an environment outside the measuring cavity via the pump outlet. Furthermore, the pump-sensor arrangement has a sensor for detecting at least one component of the analyte fluid present within the measuring cavity and movable by means of the micropump. In accordance with the invention, both the sensor and the micropump are commonly arranged on the first main surface of the substrate and within the measuring cavity.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: November 1, 2022
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Christoph Kutter, Yuecel Congar, Siegfried Roehl, Martin Richter
  • Patent number: 11462512
    Abstract: The subject disclosure relates to 3D microelectronic chip packages with embedded coolant channels. The disclosed 3D microelectronic chip packages provide a complete and practical mechanism for introducing cooling channels within the 3D chip stack while maintaining the electrical connection through the chip stack. According to an embodiment, a microelectronic package is provided that comprises a first silicon chip comprising first coolant channels interspersed between first thru-silicon-vias (TSVs). The microelectronic chip package further comprises a silicon cap attached to a first surface of the first silicon chip, the silicon cap comprising second TSVs that connect to the first TSVs. A second silicon chip comprising second coolant channels can further be attached to the silicon cap via interconnects formed between a first surface of the second silicon chip and the silicon cap, wherein the interconnects connect to the second TSVs.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: October 4, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kamal K. Sikka, Fee Li Lie, Kevin Winstel, Ravi K. Bonam, Iqbal Rashid Saraf, Dario Goldfarb, Daniel Corliss, Dinesh Gupta
  • Patent number: 11450597
    Abstract: A semiconductor package substrate, a method for fabricating the same, and an electronic package having the same are provided. The method includes: providing a circuit structure having a first solder pad and a second solder pad; forming on the circuit structure a metal sheet having a first hole, from which the first solder pad is exposed, and a second hole, from which the second solder pad is exposed; and forming an insulation layer on the metal sheet and a hole wall of the second hole. A first conductive element that is to be grounded is disposed in the first hole and is in contact with the metal sheet and the first solder pad. Therefore, heat generated in a signal transmission process is dissipated by the metal sheet and the first conductive element.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: September 20, 2022
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Pao-Hung Chou, Chun-Hsien Yu, Shih-Ping Hsu
  • Patent number: 11450631
    Abstract: In one example, a method for redistribution layer (RDL) process is described. A substrate is provided. A dielectric layer is deposited on top of the substrate. The dielectric layer is patterned. A barrier and copper seed layer are deposited on top of the dielectric layer. A photoresist layer is applied on top of the barrier and copper seed layer. The photoresist layer is patterned to correspond with the dielectric layer pattern. Copper is electrodepositing in the patterned regions exposed by the photoresist layer. The photoresist layer is removed. The copper and seed barrier are etched.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: September 20, 2022
    Assignee: Lam Research Corporation
    Inventors: Justin Oberst, Bryan L. Buckalew, Stephen J. Banik
  • Patent number: 11444060
    Abstract: A package-on-package type package includes a lower semiconductor package and an upper semiconductor package. The lower semiconductor package includes a first semiconductor device including a through electrode, a second semiconductor device disposed on the first semiconductor device and including a second through electrode electrically connected to the first through electrode, a first molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device, a second molding member covering a sidewall of the first molding member, and an upper redistribution layer disposed on the second semiconductor device and electrically connected to the second through electrode.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: September 13, 2022
    Inventors: Sanguk Han, Chajea Jo, Hyoeun Kim, Sunkyoung Seo
  • Patent number: 11424398
    Abstract: The present invention improves the performance of a thermoelectric conversion material and a thermoelectric conversion module. A thermoelectric conversion material has a mother phase containing a chimney ladder type compound comprising a first element of groups 4 to 9 and a second element of groups 13 to 15 and an additive phase existing at a grain boundary of the mother phase, the mother phase contains a third element to change a lattice constant of the chimney ladder type compound, and the additive phase contains the second element.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: August 23, 2022
    Assignee: Hitachi, Ltd.
    Inventors: Yosuke Kurosaki, Shin Yabuuchi, Jun Hayakawa, Yuzuru Miyazaki, Tomohisa Takamatsu, Kei Hayashi
  • Patent number: 11416045
    Abstract: A thermal interface material (TIM) structure for directing heat in a three-dimensional space including a TIM sheet. The TIM sheet includes a lower portion along a lower plane; a first side portion along a first side plane; a first upper portion along an upper plane; a first fold between the lower portion and the first side portion positioning the first side portion substantially perpendicular to the lower portion; and a second fold between the first side portion and the first upper portion positioning the first upper portion substantially perpendicular to the first side portion and substantially parallel to the lower portion.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: August 16, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark K. Hoffmeyer, Christopher M. Marroquin, Eric J. Campbell, Sarah K. Czaplewski-Campbell, Phillip V. Mann
  • Patent number: 11404347
    Abstract: A semiconductor package according to an exemplary embodiment of the present disclosure may comprise a semiconductor chip comprising a chip pad; a redistribution layer electrically connected to the chip pad of the semiconductor chip; an external connection terminal electrically connected to the redistribution layer; a sealing material covering the semiconductor chip and configured to fix the semiconductor chip and the redistribution layer; an adhesive film positioned on the upper surface of the sealing material; and a heat sink formed on the upper surface of the adhesive film and having a stepped portion at the periphery thereof.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: August 2, 2022
    Assignee: NEPES CO., LTD.
    Inventors: Nam Chul Kim, Jong Heon Kim, Eung Ju Lee, Yong Woon Yeo, Chang Woo Lee
  • Patent number: 11355410
    Abstract: A device includes a device layer comprising a first transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure includes a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a conductive line electrically connected to the source/drain region of the first transistor through the contact; and a thermal dissipation path thermally connected to the device layer, the thermal dissipation path extending to a surface of the second interconnect structure opposite the device layer. The thermal dissipation path comprises a dummy via.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Sheh Huang, Yu-Hsiang Chen, Chii-Ping Chen
  • Patent number: 11348859
    Abstract: While the use of 2.5D/3D packaging technology results in a compact IC package, it also raises challenges with respect to thermal management. Integrated component packages according to the present disclosure provide a thermal management solution for 2.5D/3D IC packages that include a high-power component integrated with multiple lower-power components. The thermal solution provided by the present disclosure includes a mix of passive cooling by traditional heatsink or cold plate and active cooling by thermoelectric cooling (TEC) elements. Certain methods according to the present disclosure include controlling a temperature during normal operation in an IC package that includes a plurality of lower-power components located adjacent to a high-power component in which the high-power component generates a greater amount of heat relative to each of the lower-power components during normal operation.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: May 31, 2022
    Assignee: Google LLC
    Inventors: Melanie Beauchemin, Madhusudan Iyengar, Christopher Malone, Gregory Imwalle
  • Patent number: 11342241
    Abstract: A power module, including: a first conductor, disposed at a first reference plane; a second conductor, disposed at a second reference plane, wherein projections of the first and second conductors on the first reference plane have a first overlap area; a third conductor, disposed at a third reference plane; a plurality of first switches, first ends of which are coupled to the first conductor; and a plurality of second switches, first ends of which are coupled to second ends of the first switches through the third conductor, and second ends of the second switches are coupled to the second conductor, wherein projections of minimum envelope areas of the first and second switches on the first reference plane have a second overlap area, and the first and second overlap areas have an overlap region. Heat sources of the power module are evenly distributed and its parasitic inductance is low.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: May 24, 2022
    Assignee: Delta Electronics (Shanghai) CO., LTD
    Inventors: Wei Cheng, Shouyu Hong, Dongfang Lian, Tao Wang, Zhenqing Zhao
  • Patent number: 11337303
    Abstract: A circuit board structure includes a carrier and a patterned circuit layer. The patterned circuit layer is disposed on the carrier, and the patterned circuit layer has at least one fluid channel therein. The fluid channel has a heat absorption section and a heat dissipation section relative to the heat absorption section. A heat source is electrically connected to the patterned circuit layer, and the heat absorption section is adjacent to the heat source. The heat generated by the heat source is transferred from the patterned circuit layer to the heat absorption section of the fluid channel, and is transferred from the heat absorption section to the heat dissipation section for heat dissipation.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: May 17, 2022
    Assignee: Unimicron Technology Corp.
    Inventors: Ra-Min Tain, Chi-Chun Po, Po-Hsiang Wang
  • Patent number: 11322479
    Abstract: A semiconductor package includes a first chip, a plurality of through vias and an encapsulant. The first chip has a first via and a protection layer thereon. The first via is disposed in the protection layer. The through vias are disposed aside the first chip. The encapsulant encapsulates the first chip and the plurality of through vias. A surface of the encapsulant is substantially coplanar with surfaces of the protection layer and the plurality of through vias.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zi-Jheng Liu, Chen-Cheng Kuo, Hung-Jui Kuo
  • Patent number: 11322452
    Abstract: A semiconductor module includes: a first insulating plate; a second insulating plate is arranged above the first insulating plate; a first semiconductor device provided on an upper surface of the first insulating plate; a second semiconductor device provided on a lower surface of the second insulating plate; an insulating substrate including a third insulating plate arranged between the first insulating plate and the second insulating plate, and a conductor provided on the third insulating plate and connected to the first and second semiconductor devices; and sealing resin sealing the first and second semiconductor devices and the insulating substrate, wherein a withstand voltage of the third insulating plate is lower than withstand voltages of the first and second insulating plates.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: May 3, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yusuke Ishiyama
  • Patent number: 11315851
    Abstract: A method of fabricating a semiconductor package structure is provided. The structure is configured to include a base substrate, a die placed on the base substrate, the die including a semiconductor device, a solder bump placed on one surface of the die to exhaust heat generated in the die to an outside; and a solder ball placed on other surface of the die facing the one surface to transmit a signal, which is produced by the semiconductor device of the die, to an external device.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: April 26, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youngho Kim, Hwanpil Park
  • Patent number: 11315868
    Abstract: An electronic-component-mounted module has an electronic component, a first silver-sintered bonding layer bonded on one surface of the electronic component, a circuit layer made of copper or copper alloy and bonded on the first silver-sintered bonding layer, and a ceramic substrate board bonded on the circuit layer, and further has an insulation circuit substrate board with smaller linear expansion coefficient than the electronic component, a second silver-sintered bonding layer bonded on the other surface of the electronic component, and a lead frame with smaller linear expansion coefficient than the electronic component bonded on the second silver-sintered bonding layer; and a difference in the linear expansion coefficient between the insulation circuit substrate board and the lead frame is not more than 5 ppm/° C.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: April 26, 2022
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Tomoya Oohiraki, Sotaro Oi
  • Patent number: 11315867
    Abstract: An external connection terminal of a semiconductor module is provided. The external connection terminal includes a conductor having an upper surface and a lower surface; a plated layer configured to cover the upper surface of the conductor; and a nut provided on the lower surface-side of the conductor for receiving a screw penetrating the conductor. The plated layer includes a low contact resistance region overlapping a region in which the nut is provided, and a high contact resistance region that is a region except the low contact resistance region, as seen from above, and the plated layer includes a convex portion and a concave portion on a surface in the high contact resistance region.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: April 26, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Hayato Nakano
  • Patent number: 11309228
    Abstract: A packaged semiconductor device includes a package substrate, a first semiconductor device on the package substrate, and at least one second semiconductor device that extends on and partially covers the first semiconductor device. A heat dissipating insulation layer is provided as a coating on the first and second semiconductor devices. A conductive heat dissipation member is provided, which extends upwardly from the heat dissipating insulation layer and on portions of the first and second semiconductor devices. A protective member is provided on the package substrate, to cover the first and second semiconductor devices and the conductive heat dissipation member. This protective member includes a first covering portion, which covers an upper surface of the conductive heat dissipation member.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: April 19, 2022
    Inventors: Sunchul Kim, Taehun Kim, Pyoungwan Kim
  • Patent number: 11295963
    Abstract: A method of fabricating a thermal management device. The method includes depositing a seed layer, using a seed layer depositing technique, on a side of a support base; growing a heat sink base layer on a side of the seed layer; depositing a hard mask on a side of the support base directly opposite that containing the seed and heat sink base layers; patterning the hard mask with a photoresist mask; etching the patterned hard mask with an etching technique, wherein the etching creates trenches in the underlying support base, exposing the seed layer; removing the hard mask with a hard mask removal technique; depositing a layer of photoresist on the heat sink base layer; growing heat sinks using a heat sink growth technique on the exposed seed layer; removing the photoresist layer with a photoresist layer removal technique; and removing the support base with a support base removal technique.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: April 5, 2022
    Assignee: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Mohamed Tarek Ghoneim, Muhammad Mustafa Hussain
  • Patent number: 11282762
    Abstract: A flip chip ball grid array (FCBGA) comprises a substrate, a cavity forming ring stiffener, an external heat sink, and a thermal interface material. The cavity forming ring stiffener is disposed on the substrate. The cavity forming ring stiffener has a segment which forms a cavity with the substrate, and exposes a top of the silicon chip. The external heat sink is disposed on the silicon chip and the segment of the cavity forming ring stiffener. A thermal interface material separates the segment of the cavity forming ring stiffener and the top of the silicon chip from the external heat sink and conducts heat from the silicon chip to the external heat sink.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: March 22, 2022
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Huahung Kao, Chenglin Liu
  • Patent number: 11282812
    Abstract: An integrated circuit structure may be formed having a first integrated circuit device, a second integrated circuit device electrically coupled to the first integrated circuit device with a plurality of device-to-device interconnects, and at least one jumping drops vapor chamber between the first integrated circuit device and the second integrated circuit device wherein at least one device-to-device interconnect of the plurality of device-to-device interconnects extends through the jumping drops vapor chamber. In one embodiment, the integrated circuit structure may include three or more integrated circuit devices with at least two jumping drops vapor chambers disposed between the three or more integrated circuit devices. In a further embodiment, the two jumping drops chambers may be in fluid communication with one another.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: March 22, 2022
    Assignee: Intel Corporation
    Inventors: Adel Elsherbini, Feras Eid, Johanna Swan
  • Patent number: 11282793
    Abstract: A method of forming a package assembly includes forming a first dielectric layer over a carrier substrate; forming a conductive through-via over the first dielectric layer; treating the conductive through-via with a first chemical, thereby roughening surfaces of the conductive through-via; and molding a device die and the conductive through-via in a molding material.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: March 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih Ting Lin, Szu-Wei Lu, Jing-Cheng Lin, Chen-Hua Yu
  • Patent number: 11264348
    Abstract: A semiconductor device of embodiments includes a substrate; a semiconductor chip provided above the substrate; a first ultrasonic bonding portion provided between the substrate and the semiconductor chip; a first terminal plate electrically connected to the semiconductor chip via the first ultrasonic bonding portion, the first ultrasonic bonding portion being provided on the substrate, and the first terminal plate having a first surface facing the semiconductor chip; and a first adhesive layer provided on the first surface, and the first adhesive layer containing a first adhesive.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: March 1, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Fumiyoshi Kawashiro
  • Patent number: 11251101
    Abstract: A main ceramic circuit board on which a semiconductor element is arranged is separate from a sub-ceramic circuit board on which a connection terminal is arranged. Accordingly, heat generated by the semiconductor element is conducted via the main ceramic circuit board and a base plate arranged thereunder and the sub-ceramic circuit board to the connection terminal. That is to say, it is difficult to conduct heat from the semiconductor element to the connection terminal, compared with a case where the connection terminal and the semiconductor element are arranged over the same ceramic circuit board.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: February 15, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Taichi Itoh
  • Patent number: 11243034
    Abstract: A cold plate structure, wherein a thermally active region includes fins metal injection molded in a single piece with a fin base sufficiently thin so that the active region mechanically conforms to the heat generating device that the cold plate cools. The fin base is formed as a common structure with a bottom wall of the cold plate, reducing thermal resistance between the device and the fins and also enhancing mechanical flexibility. Another cold plate structure can include multiple thermally active regions, with flexible outer walls and a reduced thickness between active regions, allowing for position variation between multiple heat generation devices that are cooled by the common cold plate. A common base having multiple physically separate active regions can be metal injection molded in a single step, or bases of multiple active regions can be formed individually and joined later to form a common single cold plate structure.
    Type: Grant
    Filed: July 11, 2020
    Date of Patent: February 8, 2022
    Assignee: International Business Machines Corporation
    Inventors: Todd E. Takken, Shurong Tian
  • Patent number: 11233011
    Abstract: An object of the present invention is to improve assemblability of a power semiconductor device. A power semiconductor device includes a plurality of submodules that includes a semiconductor element interposed between a source conductor and a drain conductor, a sense wiring that transmits a sense signal of the semiconductor element, and an insulating portion at which the sense wiring and the sense conductor are arranged, and a source outer conductor that is formed to surround the source conductor and is joined to the source conductor in each of the plurality of submodules. Each source conductor included in the plurality of submodules includes protrusion portions that are formed toward the sensor wiring from the source conductor, are connected to the sense wiring, and define a distance between the sense wiring and the source outer conductor.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: January 25, 2022
    Assignee: HITACHI ASTEMO, LTD.
    Inventors: Takashi Hirao, Haruka Shimizu
  • Patent number: 11222877
    Abstract: The present disclosure is directed to systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A thermally conductive member that includes at least one thermally conductive member may be disposed between the first semiconductor package and the second semiconductor package. The thermally conductive member may include: a single thermally conductive element; multiple thermally conductive elements; or a core that includes at least one thermally conductive element. The thermally conductive elements are thermally conductively coupled to an upper surface of the first semiconductor package and to the lower surface of the second semiconductor package to facilitate the transfer of heat from the first semiconductor package to the second semiconductor package.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: January 11, 2022
    Assignee: Intel Corporation
    Inventors: Omkar Karhade, Robert L. Sankman, Nitin A. Deshpande, Mitul Modi, Thomas J. De Bonis, Robert M. Nickerson, Zhimin Wan, Haifa Hariri, Sri Chaitra J. Chavali, Nazmiye Acikgoz Akbay, Fadi Y. Hafez, Christopher L. Rumer
  • Patent number: 11204205
    Abstract: The Invention pertains to a heat sink comprising a substantially planar solid slab, provided with a plurality of fluid flow channels, said plurality of fluid flow channels being formed so as to channel a coolant from an inlet to an outlet of said slab, wherein said plurality of channels includes at least two main channels interconnected by at least a plurality of bridging channels that do not branch out further between their respective points of attachment to said main channels, wherein said bridging channels have a cross section that locally increases in the direction of flow, and wherein said bridging channels have a cross section that locally decreases in the direction of flow, downstream of said local increase in cross section. The invention also pertains to a method for producing a heat sink.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: December 21, 2021
    Assignee: DIABATIX NV
    Inventors: Joris Coddé, Lieven Vervecken
  • Patent number: 11203183
    Abstract: A single and multi-layer flat glass-sensor structure and method of making the flat glass-sensor structure. The flat glass sensor structure comprises at least one flat glass layer, a sensor and a heater. The flat glass layer has a plurality of cutouts that are configured to “suspend” the sensor on top of or in plane with the flat glass layer. The sensor is an electrochemical wafer with at least one sensory element and flat glass connectors. Each flat glass connector is in minimal contact with at least one sensory sub-area. The heater is a resistive heating element that is on top of or in plane with the flat glass layer configured to heat the sensor. The flat glass connectors are configured to provide support for electrical leads to the heater and membrane. The flat glass connectors are also configured to provide temperature insulation of the suspended sensor.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: December 21, 2021
    Assignee: VAON, LLC
    Inventors: Henry Steen, Quentin Lineberry, Vladimir Dobrokhotov
  • Patent number: 11195776
    Abstract: A power module substrate includes an insulating substrate and a metal plate. The metal plate is joined to the insulating substrate with a brazing material in between. As to surface roughness of a lateral surface of the metal plate in a thickness direction, the surface roughness of at least a corner part farthest from a center of the metal plate in plan view is larger than the surface roughness of plane parts sandwiching the corner part.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: December 7, 2021
    Assignee: KYOCERA CORPORATION
    Inventor: Yoshitada Konishi
  • Patent number: 11189544
    Abstract: A power conversion apparatus includes a semiconductor element, a plurality of lead frames, a flow-passage formation body, an insulating portion, a metal joining material, and a resin sealing portion. The plurality of lead frames are electrically connected to the semiconductor element. The flow-passage formation body forms a coolant flow passage in which a coolant flows. The insulating portion is arranged between the lead frame and the flow-passage formation body to provide insulation between the lead frame and the flow-passage formation body. The metal joining material joins the insulating portion and the flow-passage formation body. The resin sealing portion seals the semiconductor element and the lead frames. The semiconductor element and the lead frames are integrated with the flow-passage formation body to form a semiconductor cooling assembly by the resin sealing portion.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: November 30, 2021
    Assignee: DENSO CORPORATION
    Inventors: Hiroki Matsuzawa, Bahman Hossini Soltani
  • Patent number: 11189596
    Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: November 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Hsien-Wen Liu, Shin-Puu Jeng, Hsiao-Wen Lee
  • Patent number: 11183624
    Abstract: Electronic assemblies for thermoelectric generation are disclosed. In one embodiment, an electronic assembly includes a substrate having a first surface and a second surface, and a conductive plane and a plurality of thermal guide traces position on the first surface of the substrate. The conductive plane includes a plurality of arms radially extending from a central region. The plurality of thermal guide traces surrounds the conductive plane, and is shaped and positioned to guide heat flux present on or within the substrate toward the central region of the conductive plane. The electronic assembly may also include a thermoelectric generator device thermally coupled to the central region of the conductive plane, and a plurality of heat generating devices coupled to the second surface of the substrate.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: November 23, 2021
    Assignee: TOYOTA MOTOR ENGINEERING & MANUFACTURING NORTH AMERICA, INC.
    Inventor: Ercan Mehmet Dede
  • Patent number: 11177626
    Abstract: A pyrolytic graphite (PG) substrate and laser diode package includes a substrate body having a PG crystalline structure with a basal plane oriented at a pre-determined orientation angle as measured from a longitudinal axis of a heat generating material, such as a laser diode, mounted on a surface of the PG substrate, so that a coefficient of thermal expansion (CTE) of the PG substrate is substantially matched with a CTE of the material.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: November 16, 2021
    Assignee: Lawrence Liveremore National Security, LLC
    Inventors: Susant Patra, Robert J. Deri, John W. Elmer
  • Patent number: 11172594
    Abstract: A heat dissipation structure applied to a substrate with a heat generating element is provided. The heat dissipation structure includes a heat dissipation body and an elastomer. The heat dissipation body includes a connecting portion, where the connecting portion includes a central area and a peripheral area, and the central area is configured to contact with the heat generating element. The elastomer is disposed between the peripheral area and the heat generating element, to form a sealed space, and the sealed space is configured to accommodate a heat-conducting medium.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: November 9, 2021
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Chun-Chieh Wong, Cheng-Yu Wang
  • Patent number: 11158614
    Abstract: An embodiment device includes a first die, a second die electrically connected to the first die, and a heat dissipation surface on a surface of the second die. The device further includes a package substrate electrically connected to the first die. The package substrate includes a through-hole, and the second die is at least partially disposed in the through hole.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: October 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung Wei Cheng, Tsung-Ding Wang, Mirng-Ji Lii, Chien-Hsun Lee
  • Patent number: 11158586
    Abstract: The present disclosure relates to a semiconductor structure and a method of manufacturing the semiconductor structure. The semiconductor structure includes a substrate including a first surface and a conductive trace extending over the substrate; a die disposed over the first surface of the substrate; a molding disposed over the first surface of the substrate and covering the die; and a metallic layer surrounding the molding and the substrate, wherein the metallic layer is electrically connected to at least a portion of the conductive trace exposed through the substrate.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: October 26, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chang-Chun Hsieh, Wu-Der Yang, Ching-Feng Chen
  • Patent number: 11152278
    Abstract: A heat sink for an integrated circuit chip. The heat sink includes a base plate and a plurality of fins connected to the base plate. The base plate includes a first segment, a second segment, and a third segment that are sequentially connected; and the first segment and the third segment extend obliquely upward relative to the second segment.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: October 19, 2021
    Assignee: Bitmain Technologies Inc.
    Inventors: Tong Zou, Micree Zhan, Wenjie Cheng
  • Patent number: 11152312
    Abstract: A package structure includes an interposer, a die over and bonded to the interposer, and a Printed Circuit Board (PCB) underlying and bonded to the interposer. The interposer is free from transistors therein (add transistor), and includes a semiconductor substrate, an interconnect structure over the semiconductor substrate, through-vias in the silicon substrate, and redistribution lines on a backside of the silicon substrate. The interconnect structure and the redistribution lines are electrically coupled through the through-vias.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sao-Ling Chiu, Kuo-Ching Hsu, Wei-Cheng Wu, Ping-Kang Huang, Shang-Yun Hou, Shin-Puu Jeng, Chen-Hua Yu
  • Patent number: 11133242
    Abstract: A method of manufacturing semiconductor devices such as integrated circuits comprises: providing one or more semiconductor chips having first and second opposed surfaces, coupling the semiconductor chip or chips with a support substrate with the second surface towards the support substrate, embedding the semiconductor chip or chips coupled with the support substrate in electrically-insulating packaging material by providing in the packaging material electrically-conductive passageways. The electrically-conductive passageways comprise: electrically-conductive chip passageways towards the first surface of the at least one semiconductor chip, and/or electrically-conductive substrate passageways towards the support substrate.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: September 28, 2021
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Michele Derai, Federico Giovanni Ziglioli
  • Patent number: 11125508
    Abstract: A thin heat pipe structure includes a main body having a chamber. The chamber has a wick structure and a working fluid provided therein, and internally defines an evaporating section and at least one condensing section. The condensing section is extended towards at least one or two ends of the evaporating section. The wick structure is provided with at least one groove. The groove is extended through the wick structure along a thickness direction of the main body to connect to two opposite wall surfaces of the chamber, and also extended along a length direction of the main body to communicate with the condensing section and the evaporating section. With these arrangements, the thin heat pipe structure has an extremely small overall thickness and is flexible.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: September 21, 2021
    Assignee: Asia Vital Components Co., Ltd.
    Inventor: Chun-Ming Wu
  • Patent number: 11122717
    Abstract: To obtain, in an on-board control device, a shield effect against noise radiated from an electronic component. The present invention includes: an electronic component 103; a metal housing 101 which covers at least a part of the electronic component 103; a metal portion 105 which is provided so that the electronic component 103 is disposed between the metal portion 105 and the metal housing 101; and a shield structure which shields radiation noise from the electronic component 103 by electrostatic capacitive coupling formed between the metal portion 105 and the metal housing 101.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: September 14, 2021
    Assignee: HITACHI AUTOMOTIVE SYSTEMS, LTD.
    Inventors: Yoko Ohkubo, Hideyuki Sakamoto, Yusaku Katsube
  • Patent number: 11114364
    Abstract: Disclosed is a semiconductor package comprising first and second semiconductor structures spaced apart on a first substrate, a heat sink covering the first and second semiconductor structure and the first substrate, and a thermal interface material layer between the heat sink and the first and second semiconductor structures. The first semiconductor structure includes a first sidewall adjacent to the second semiconductor structure and a second sidewall opposite the first sidewall. The thermal interface material layer includes a first segment between the first and second semiconductor structures and a second segment protruding beyond the second sidewall. A first distance from a top surface of the first substrate to a lowest point of a bottom surface of the first segment is less than a second distance from the top surface of the first substrate to a lowest point of a bottom surface of the second segment.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: September 7, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hee-Jeong Kim, Juhyun Lyu, Un-Byoung Kang, Jongho Lee
  • Patent number: 11114416
    Abstract: A three-dimensional stacked integrated circuit (3D SIC) having a non-volatile memory die, a volatile memory die, a logic die, and a thermal management component. The non-volatile memory die, the volatile memory die, the logic die, and the thermal management component are stacked. The thermal management component can be stacked in between the non-volatile memory die and the logic die, stacked in between the volatile memory die and the logic die, or both.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: September 7, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Tony M. Brewer
  • Patent number: 11101193
    Abstract: A power electronics module includes an electrically-conductive substrate including a base portion defining a plurality of orifices that extend through the base portion, the plurality of orifices defining a plurality of jet paths extending along and outward from the plurality of orifices, and a plurality of posts extending outward from the base portion, where individual posts of the plurality of posts are positioned between individual orifices of the plurality of orifices, and a power electronics device coupled to the plurality of posts opposite the base portion, the power electronics device defining a bottom surface that is oriented transverse to the plurality of jet paths.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: August 24, 2021
    Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventors: Shailesh N. Joshi, Naoya Take, Ercan Mehmet Dede
  • Patent number: 11094683
    Abstract: A method of producing a bonded chip stack is described. A first nanofluidic device chip having a first through-wafer via is formed. A second nanofluidic device chip having a second through-wafer via is formed. The first nanofluidic device chip and the second nanofluidic device chip are washed with a detergent solution. A first surface of the first nanofluidic device chip and a second surface of the second nanofluidic device chip are activated by treating the first surface and the second surface with an activation solution. The first nanofluidic device chip and the second nanofluidic device chip are arranged in a stack. The first through-wafer via is aligned with the second through-wafer via in a substantially straight line. The stack of first and second nanofluidic device chips is subjected to annealing conditions.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: August 17, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin Wunsch, Joshua T. Smith, Stacey Gifford, Michael Albert Pereira
  • Patent number: RE48858
    Abstract: Embodiments provide a light emitting device package including a package body having a through-hole; a radiator disposed in the through-hole and including an alloy layer having Cu; and a light emitting device disposed on the radiator, wherein the alloy layer includes at least one of W or Mo, and wherein the package body includes cavity including a sidewall and a bottom surface, and wherein the through-hole is formed in the bottom surface.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: December 21, 2021
    Assignee: SUZHOU LEKIN SEMICONDUCTOR CO., LTD.
    Inventors: Su Jung Jung, Yon Tae Moon, Young Jun Cho, Son Kyo Hwang, Byung Mok Kim, Seo Yeon Kwon