Capacitor of nonvolatile memory device
The capacitor of a nonvolatile memory device includes first and second electrodes formed in the capacitor region of a semiconductor substrate to respectively have consecutive concave and convex shape of side surfaces formed along each other and a dielectric layer formed between the first and the second electrodes.
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Priority to Korean patent application number 10-2010-0139179 filed on Dec. 30, 2010, the entire disclosure of which is incorporated by reference herein, is claimed.
BACKGROUNDAn exemplary embodiment relates to the capacitor of a nonvolatile memory device and, more particularly, to the capacitor of a nonvolatile memory device for increasing capacitance.
A nonvolatile memory device includes a pump circuit for generating voltages for a program operation, a read operation, and an erase operation. The pump circuit may include a plurality of capacitors for pumping operations.
Referring to
The capacitors of the conventional nonvolatile memory device may be formed when memory cells are fabricated. The conductive layer 14 for a control gate and the conductive layer 12 for a floating gate are electrically coupled to form a capacitor structure.
In order to increase capacitance of the capacitor, the area of the conductive layer 12 may be increased. In this case, however, the degree of integration of nonvolatile memory devices may be adversely affected.
BRIEF SUMMARYAn exemplary embodiment relates to the capacitor of a nonvolatile memory device having increased capacitance.
A capacitor of a nonvolatile memory device according to an aspect of the present disclosure includes first and second electrodes formed in a capacitor region of a semiconductor substrate to respectively have consecutive concave and convex shape of side surfaces formed along each other, and a dielectric layer formed between the first and second electrodes.
A capacitor of a nonvolatile memory device according to another aspect of the present disclosure includes first and second lower electrodes formed in a capacitor region of a semiconductor substrate to each have a rake structure, wherein fingers of each rake structure alternate with the fingers of the other rake structure, a first dielectric layer formed between the first and second lower electrodes and over the first and second lower electrodes, first and second upper electrodes formed on the first dielectric layer to each have a rake structure, wherein fingers of each rake structure alternate with the fingers of the other rake structure, and a second dielectric layer formed between the first and the second upper electrodes.
Hereinafter, an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. The figures are provided to enable those of ordinary skill in the art to make and use the embodiment of the disclosure.
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Next, a second interlayer dielectric layer 116 is formed on the entire structure including the first electrode line 114. Next, contact holes are formed by etching the first interlayer dielectric layer 112, the first dielectric layer 106, the second dielectric layer 108, and the tunnel insulating layer 102 such that part of the top surface of an outermost pattern of the second lower electrode patterns 104B, part of the top surface of an outermost pattern of the second upper electrode patterns 108B, and parts of the semiconductor substrate 100 are exposed. The contact holes are filled with a conductive material and are coupled to form a second electrode line 118. Here, it is preferred that junctions 120 be formed in the semiconductor substrate, exposed through the contact holes, by performing an ion implantation process after forming the contact holes.
According to the capacitor formation method, the first lower electrode patterns 104A and the second lower electrode patterns 104B are formed using the conductive layer 104 for a floating gate and have the concave and convex () structure in order to increase the contact areas. Accordingly, capacitance of the capacitor can be increased. Furthermore, the second upper electrode patterns 108B and the first upper electrode patterns 108A are formed over the first lower electrode patterns 104A and the second lower electrode patterns 104B, respectively, using the conductive layer 108 for a control gate. Accordingly, capacitance of the capacitor can be further increased. Furthermore, the electrode line is coupled to the semiconductor substrate, thereby generating capacitance between the semiconductor substrate and the first lower electrode patterns 104A. Accordingly, capacitance can be further increased.
According to the exemplary embodiment of this disclosure, the first and the second electrodes having a concave and convex () shape opposite to each other are formed by using the conductive layer for a floating gate of a memory cell. Accordingly, the contact areas between the first and second electrodes can be optimized/maximized, and capacitance of a capacitor can be increased.
Claims
1. A capacitor of a nonvolatile memory device, comprising:
- first and second lower electrodes formed in a capacitor region of a semiconductor substrate to each have a rake structure, wherein fingers of each rake structure alternate with the fingers of the other rake structure;
- a first dielectric layer formed between the first and second lower electrodes and over the first and second lower electrodes;
- first and second upper electrodes formed over the first dielectric layer to each have a rake structure, wherein fingers of each rake structure alternate with the fingers of the other rake structure have a crossing finger structure;
- a second dielectric layer formed between the first and the second upper electrodes;
- a first electrode line coupling the first upper electrode to the first lower electrode; and
- a second electrode line coupling the second upper electrode to the second lower electrode,
- wherein the first upper electrode is formed over the second lower electrode, and the second upper electrode is formed over the first lower electrode.
2. The capacitor of claim 1, wherein a concave portion and a convex portion of the side of the first lower electrode are formed to face a convex portion and concave portion of the side of the second lower electrode, respectively.
3. The capacitor of claim 1, wherein:
- a convex portion of the side of the second lower electrode is formed in a concave portion of the side of the first lower electrode, and
- a convex portion of the side of the first lower electrode is formed in a concave portion of the side of the second lower electrode.
4. The capacitor of claim 1, further comprising an insulating layer formed at an interface between the first and second lower electrodes and the semiconductor substrate.
5. The capacitor of claim 4, further comprising electrode lines coupling the semiconductor substrate to the second lower electrode.
6. The capacitor of claim 1, wherein the first and the second lower electrodes are formed of a conductive layer for a floating gate.
7. The capacitor of claim 1, wherein the first and the second upper electrodes are formed of a conductive layer for a control gate.
6819542 | November 16, 2004 | Tsai et al. |
11-135361 | May 1999 | JP |
- Notice of Preliminary Rejection issued from the Korean Intellectual Property Office on Jan. 5, 2012.
Type: Grant
Filed: Nov 3, 2011
Date of Patent: Oct 7, 2014
Patent Publication Number: 20120168905
Assignee: SK Hynix Inc. (Gyeonggi-do)
Inventor: Je il Ryu (Seoul)
Primary Examiner: Laura Menz
Application Number: 13/288,399
International Classification: H01L 21/00 (20060101); H01L 27/115 (20060101); H01L 29/94 (20060101); H01L 49/02 (20060101);