Abstract: A semiconductor device includes conductive pillars on a semiconductor substrate, a first support pattern that contacts first portions of lateral surfaces of the conductive pillars and connects the conductive pillars to each other, the first support pattern including first support holes that expose second portions of the lateral surfaces of the conductive pillars, a capping conductive pattern that contacts the second portions of the lateral surfaces of the conductive pillars and exposes the first support pattern, the second portions of the lateral surfaces of the conductive pillars being in no contact with the first support pattern, and a dielectric layer that covers the first support pattern and the capping conductive pattern, the dielectric layer being spaced apart from the conductive pillars.

Abstract: An interconnect structure for use in coupling transistors in an integrated circuit is disclosed, including various configurations in which ferroelectric capacitors exhibiting negative capacitance are coupled in series with dielectric capacitors. In one embodiment, the negative capacitor includes a dielectric/ferroelectric bi-layer. When a negative capacitor is electrically coupled in series with a conventional dielectric capacitor, the series combination behaves like a stable ferroelectric capacitor for which the overall capacitance can be measured experimentally, and tuned to a desired value. The composite capacitance of a dielectric capacitor and a ferroelectric capacitor having negative capacitance coupled in series is, in theory, infinite, and in practice, very large. A series combination of positive and negative capacitors within a microelectronic interconnect structure can be used to make high capacity DRAM memory cells.

Abstract: A semiconductor device includes a plurality of capacitors with MIM structure disposed in an interconnection layer on a substrate. Each capacitor includes a first electrode and a second electrode provided by any two interconnection parts of the interconnection layer, in which the first electrode is one of the two interconnection parts located adjacent to the substrate and the second electrode is the other located opposite to the substrate with respect to the first electrode. One of the first and second electrode of each capacitor is provided by the same interconnection part as a subject electrode, and a distance between the first electrode and the second electrode is different among the plurality of capacitors to have different capacitances. The subject electrodes provided by the same interconnection part are covered with an insulating film of the interconnection layer, and have ends on a same plane.

Abstract: A display apparatus includes a substrate. A first buffer layer is disposed over the substrate. The first buffer layer includes silicon nitride and has an atomic percentage of hydrogen bonded to silicon of about 0.36 to about 1.01. A thin film transistor is disposed over the first buffer layer. The thin film transistor includes an active layer. A display element is electrically connected to the thin film transistor.

Abstract: Stability of a current-voltage conversion circuit is increased in a solid-state imaging element that converts photocurrent to a voltage signal. A photodiode photoelectrically converts incident light and generates photocurrent. A conversion transistor converts photocurrent to a voltage signal and outputs the voltage signal from a gate. A current source transistor supplies predetermined constant current to an output signal line connected to the gate. A voltage supply transistor supplies a certain voltage corresponding to the predetermined constant current from the output signal line to a source of the conversion transistor. A capacitance is connected between the gate and the source of the conversion transistor.

Abstract: A multilayer ceramic capacitor includes a body including a dielectric layer and first and second internal electrodes disposed with the dielectric layer interposed therebetween and disposed in point-symmetry with each other; first and second connection electrodes penetrating the body in a direction perpendicular to the dielectric layer and connected to the first internal electrode; third and fourth connection electrodes penetrating the body in a direction perpendicular to the dielectric layer and connected to the second internal electrode; first and second external electrodes disposed on both surfaces of the body and connected to the first and second connection electrodes; and third and fourth external electrodes spaced apart from the first and second external electrodes and connected to the third and fourth connection electrodes, and the first and second internal electrodes include a region in which an electrode is not disposed.

Abstract: A vertical memory device including: a circuit pattern on a first substrate; an insulating interlayer on the first substrate, the insulating interlayer covering the circuit pattern; a bending prevention layer on the insulating interlayer, the bending prevention layer extending in a first direction substantially parallel to an upper surface of the first substrate; a second substrate on the bending prevention layer; gate electrodes spaced apart from each other in a second direction on the second substrate, the second direction being substantially perpendicular to the upper surface of the first substrate; and a channel extending through the gate electrodes in the second direction.

Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a molding layer and a first capacitor. The first capacitor includes a first vertical conductive structure within the molding layer, a second vertical conductive structure within the molding layer, and a first high-k dielectric material between the first vertical conductive structure and the second vertical conductive structure.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first palm portion positioned above a substrate; a second palm portion positioned above the substrate and opposite to the first palm portion; a first finger portion arranged substantially in parallel with a main surface of the substrate, positioned between the first palm portion and the second palm portion, and connecting to the first palm portion; a second finger portion arranged substantially in parallel with the first finger portion, positioned between the first palm portion and the second palm portion, and connecting to the second palm portion; a capacitor insulation layer positioned between the first finger portion and the second finger portion; a first spacer positioned between the first palm portion and second finger portion; and a second spacer positioned between the second palm portion and the first finger portion.

Abstract: A deep trench is formed in a substrate, and a layer stack including at least three metallic electrode plates interlaced with at least two node dielectric layers is formed in, and over, the deep trench. A contact-level dielectric material layer over the layer stack, and contact via cavities are formed therethrough. The depths of the contact via cavities are differentiated by selectively increasing the depth of a respective subset of the contact via cavities by performing at least twice a combination of processing steps that includes an etch mask formation process and an etch process. A combination of a dielectric contact via liner and a plate contact via structure can be formed within each of the contact via cavities. Plate contact via structures that extend through any metallic electrode plate can be electrically isolated from such a metallic electrode plate by a respective dielectric contact via liner.

Abstract: An integrated circuit device including a lower electrode on a substrate, the lower electrode including a first lower electrode portion extending in a first direction perpendicular to a top surface of the substrate and including a first main region and a first top region, and a second lower electrode portion extending in the first direction on the first lower electrode portion and including a second main region and a second top region; a first top supporting pattern surrounding at least a portion of a side wall of the first top region of the first lower electrode portion; and a second top supporting pattern surrounding at least a portion of a side wall of the second top region of the second lower electrode portion, and the second lower electrode portion includes a protrusion protruding outward to the second top supporting pattern.

Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first substrate and a second substrate. The first substrate has a first surface and a second surface opposite to the first surface of the first substrate. The second substrate has a first surface facing the first substrate and a second surface opposite to the first surface of the second substrate. The semiconductor device package also includes a first electronic component disposed on the first surface of the second substrate and electrically connected to the first surface of the second substrate. The semiconductor device package also includes a first encapsulant and a second encapsulant between the first substrate and the second substrate. The first encapsulant is different from the second encapsulant. A method of manufacturing a semiconductor device package is also disclosed.

Abstract: A capacitive element is located in an active region of the substrate and on a front face of the substrate. The capacitive element includes a first electrode and a second electrode. The first electrode is formed by a first conductive region and the active region. The second electrode is formed by a second conductive region and a monolithic conductive region having one part covering a surface of said front face and at least one part extending into the active region perpendicularly to said front face. The first conductive region is located between and is insulated from the monolithic conductive region and a second conductive region.

Abstract: A semiconductor memory device includes a device isolation pattern on a substrate to define an active region, a word line in the substrate, to intersect the active region, a first dopant region in the active region as at a first side of the word line, a second dopant region in the active region at a second side of the word line, a bit line connected to the first dopant region and intersecting the word line, a bit line contact connecting the bit line to the first dopant region, a landing pad on the second dopant region, and a storage node contact connecting the landing pad to the second dopant region, the storage node contact including a first portion in contact with the second dopant region, the first portion including a single-crystal silicon, and a second portion on the first portion and including a poly-silicon.

Abstract: Provided is a semiconductor device, including a substrate including a pixel region, a gate structure on the substrate in the pixel region, wherein the gate structure comprises a gate dielectric layer and a gate conductive layer on the gate dielectric layer; a dielectric layer located over the substrate and the gate structure; and a contact located in the dielectric layer and electrically connected to the gate conductive layer. The contact includes a doped polysilicon layer in contact with the gate conductive layer; a metal layer located on the doped polysilicon layer, wherein a part of the metal layer is embedded in the doped polysilicon layer; a barrier layer located between the metal layer and the doped polysilicon layer; and a metal silicide layer located between the barrier layer and the doped polysilicon layer.

Abstract: A process of smoothing a top surface of a bit line metal of a memory structure to decrease resistance of a bit line stack. The process includes depositing titanium layer of approximately 30 angstroms to 50 angstroms on polysilicon layer on a substrate, depositing first titanium nitride layer of approximately 15 angstroms to approximately 40 angstroms on titanium layer, annealing substrate at a temperature of approximately 700 degrees Celsius to approximately 850 degrees Celsius, depositing second titanium nitride layer of approximately 15 angstroms to approximately 40 angstroms on first titanium nitride layer after annealing, depositing a bit line metal layer of ruthenium on second titanium nitride layer, annealing bit line metal layer at temperature of approximately 550 degrees Celsius to approximately 650 degrees Celsius, and soaking bit line metal layer in hydrogen-based ambient for approximately 3 minutes to approximately 6 minutes during annealing.

Abstract: Certain aspects of the present disclosure are generally directed to techniques and apparatus for adjusting capacitance in one or more metal-insulator-metal (MIM) capacitors in an effort to reduce capacitance variation between semiconductor devices and improve yield during fabrication. One example method for fabricating a semiconductor device generally includes measuring a capacitance value of a MIM capacitor of the semiconductor device, determining the measured capacitance value of the MIM capacitor is above a target capacitance value for the MIM capacitor, and selectively rupturing a set of connections in the MIM capacitor based on the measured capacitance value. Selectively rupturing the set of connections in the MIM capacitor may reduce the capacitance value of the MIM capacitor to a value approximately that of the target capacitance value.

Abstract: A semiconductor device includes a plurality of lower electrode structures disposed on a substrate, and a supporter pattern disposed between pairs of lower electrode structures of the plurality of lower electrode structures. The semiconductor device further includes a capacitor dielectric layer disposed on surfaces of each of the plurality of lower electrode structures and the supporter pattern, and an upper electrode disposed on the capacitor dielectric layer. The plurality of lower electrode structures includes a first lower electrode and a second lower electrode disposed on the first lower electrode and having a cylindrical shape. The first lower electrode has a pillar shape. The first lower electrode includes an insulating core. The insulating core is disposed in the first lower electrode. An outer side surface of the first lower electrode and an outer side surface of the second lower electrode are coplanar.

Abstract: A method for forming a semiconductor device includes forming a metal layer and a spacer adjacent to the metal layer. The spacer includes a composite-dielectric layer including a composite-dielectric material. A composition of the composite-dielectric material is a mixture of a composition of a first dielectric material and a composition of a second dielectric material different from the first dielectric material.

Abstract: The present disclosure provides a capacitor, a semiconductor device, and a method for preparing a capacitor. The semiconductor device includes a plurality of memory cells, at least one of the memory cells including a capacitor. The capacitor includes a first electrode comprising titanium nitride and disposed on a substrate, a dielectric film disposed on the first electrode, a multilayer film disposed on the dielectric film, and a second electrode comprising titanium nitride and disposed on the multilayer film. The method for preparing the capacitor includes forming the first electrode comprising titanium nitride on the substrate, forming a dielectric film on the first electrode, forming the multilayer film on the dielectric film, and forming the second electrode comprising titanium nitride on the multilayer film.

Abstract: A semiconductor well of a non-volatile memory houses memory cells. The memory cells each have a floating gate and a control gate. Erasing of the memory cells includes biasing the semiconductor well with a first erase voltage having an absolute value greater than a breakdown voltage level of bipolar junctions of a control gate switching circuit of the memory. An absolute value of the first erase voltage is based on a comparison of a value of an indication of wear of the memory cells to a wear threshold value.

Abstract: A method for fabricating a semiconductor device is provided and includes the following steps: providing a substrate; forming a lower electrode on the substrate; forming at least one sub-dielectric layer on the lower electrode; patterning the dielectric layer to form an intermediate dielectric layer, where the intermediate dielectric layer exposes a portion of the at least one sub-dielectric layer; forming a hole by etching the portion of the at least one sub-dielectric layer not covered by the intermediate dielectric layer; filling at least one plug into the hole; and forming an upper electrode on the intermediate dielectric layer.

Abstract: The present application discloses a semiconductor device with capacitors having a shared electrode and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first capacitor unit, a second capacitor unit, and a connection structure. The first capacitor unit includes a bottom conductive structure inwardly positioned in the substrate, and a shared conductive layer positioned above the bottom conductive structure with a first insulating layer interposed therebetween. The second capacitor unit includes the shared conductive layer, a top conductive layer positioned above the shared conductive layer with a second insulating layer interposed therebetween. The connection structure electrically connects the bottom conductive structure and the top conductive layer such that the first capacitor unit and the second capacitor unit are in parallel.

Abstract: A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first capacitor electrode, and comprises a portion above the first capacitor electrode. Ferroelectric material is laterally between the walls of the first capacitor electrode and laterally between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material. A parallel current leakage path is between an elevationally-inner surface of the portion of the second capacitor electrode that is above the first capacitor electrode and at least one of the individual top surfaces of the laterally-spaced walls of the first capacitor electrode.

Abstract: Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory device comprises a capacitor that includes a bottom electrode, a top electrode opposite to the bottom electrode across a dielectric layer, and an interface layer between the bottom electrode and the dielectric layer. The interface layer includes a combination of niobium (Nb), titanium (Ti), oxygen (O), and nitrogen (N), and further includes a constituent of the dielectric layer.

Abstract: Some embodiments include an integrated assembly having a source structure, and having a stack of alternating conductive levels and insulative levels over the source structure. Cell-material-pillars pass through the stack. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. The cell-material-pillars include channel material which is electrically coupled with the source structure. Memory cells are along the conductive levels and include regions of the cell-material-pillars. A panel is between the first and second memory-block-regions. The panel has a first material configured as a container shape. The container shape defines opposing sides and a bottom of a cavity. The panel has a second material within the cavity. The second material is compositionally different from the first material. Some embodiments include methods of forming integrated assemblies.

Abstract: Various embodiments of the present disclosure are directed towards a ferroelectric memory device. The ferroelectric memory device includes a pair of source/drain regions disposed in a semiconductor substrate. A gate dielectric is disposed over the semiconductor substrate and between the source/drain regions. A first conductive structure is disposed on the gate dielectric. A ferroelectric structure is disposed on the first conductive structure. A second conductive structure is disposed on the ferroelectric structure, where both the first conductive structure and the second conductive structure have an overall electronegativity that is greater than or equal to an overall electronegativity of the ferroelectric structure.

Abstract: Embodiments of the present invention are directed to a back-end-of-line (BEOL) compatible metal-insulator-metal on-chip decoupling capacitor (MIMCAP). This BEOL compatible process includes a thermal treatment for inducing an amorphous-to-cubic phase change in the insulating layer of the MIM stack prior to forming the top electrode. In a non-limiting embodiment of the invention, a bottom electrode layer is formed, and an insulator layer is formed on a surface of the bottom electrode layer. The insulator layer can include an amorphous dielectric material. The insulator layer is thermally treated such that the amorphous dielectric material undergoes a cubic phase transition, thereby forming a cubic phase dielectric material. A top electrode layer is formed on a surface of the cubic phase dielectric material of the insulator layer.

Abstract: A capacitor structure includes a plurality of bottom electrodes horizontally spaced apart from each other, a support structure covering sidewalls of the bottom electrodes, a top electrode surrounding the support structure and the bottom electrodes, and a dielectric layer interposed between the support structure and the top electrode, and between the top electrode and each of the bottom electrodes. An uppermost surface of the support structure is positioned at a higher level than an uppermost surface of each of the bottom electrodes.

Abstract: A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures.

Abstract: Metal-insulator-metal (MIM) capacitor, an integrated semiconductor device having a MIM capacitor and methods of making. The MIM capacitor includes a first metal layer, a second metal layer and a dielectric layer located between the second metal layer and the first metal layer. The first metal layer, the second metal layer and the dielectric layer may be formed in a comb structure, wherein the comb structure include a first tine structure and at least a second tine structure.

Abstract: A method of forming a semiconductor device includes: depositing a first conductive plate and a second conductive plate adjacent to the first conductive plate; depositing a first insulating plate on the first conductive plate and the second conductive plate; depositing a third conductive plate on the first insulating plate; depositing a second insulating plate on the third conductive plate; forming a fourth conductive plate on the second insulating plate; forming a first conductive via penetrating the fourth conductive plate, the second insulating plate, the first insulating plate, and the first conductive plate; and forming a second conductive via penetrating the second insulating plate, the third conductive plate, the first insulating plate, and the second conductive plate.

Abstract: A semiconductor memory device includes a substrate including a cell area and a peripheral area, a plurality of capacitors including a plurality of lower electrodes arranged in the cell area, a plurality of capacitor dielectric layers covering the plurality of lower electrodes, and an upper electrode on the plurality of capacitor dielectric layers, an etch stop layer covering the upper electrode, a filling insulation layer covering the etch stop layer and arranged in the cell area and the peripheral area, a plurality of wiring lines on the filling insulation layer, and a first wiring contact plug electrically connecting at least one of the plurality of wiring lines to the upper electrode. The upper electrode includes a first upper electrode layer covering the plurality of capacitor dielectric layers and including a semiconductor material and a second upper electrode layer covering the first upper electrode layer and including a metallic material.

Abstract: Various embodiments may provide a semiconductor package. The semiconductor package may include a semiconductor chip, a first mold compound layer at least partially covering the semiconductor chip, and a redistribution layer over the first mold compound layer, the redistribution layer including one or more electrically conductive lines in electrical connection with the semiconductor chip. The semiconductor package may additionally include a second mold compound layer over the redistribution layer, and an antenna array over the second mold compound layer, the antenna array configured to be coupled to the one or more electrically conductive lines.

Abstract: Semiconductor devices having multiple substrates and die stacks, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor device includes a package substrate, and a first die stack mounted on the package substrate and including a plurality of first memory dies. The device can include a substrate mounted on the first die stack, the substrate including a plurality of routing elements. The device can also include a second die stack mounted on the substrate, the second die stack including a plurality of second memory dies. The device can further include a controller die mounted on the substrate. The controller die can be configured to communicate with the second die stack via the routing elements of the substrate. The device can include a mold material encapsulating the first die stack, the second die stack, the substrate, and the controller die.

Abstract: A semiconductor memory device includes a transistor having a gate, a source and a drain and a metal-insulator-semiconductor (MIS) structure. The transistor and the MIS structure are disposed on a common substrate. The MIS structure includes a dielectric layer disposed on a semiconductor region, and an electrode electrically disposed on the dielectric layer and coupled to the drain of the transistor. The electrode includes a bulk portion and a high-resistance portion, both disposed on the dielectric layer. The high-resistance portion has a resistance value in a range from 1.0×10?4 ?cm to 1.0×104 ?cm or a sheet resistance in a range from 1.0×102?/? to 1.0×1010?/?.

Abstract: Electronic device package technology is disclosed. In one example, an electronic device comprises a die (18) having a bond pad (22); and a decoupling capacitor (14) mounted on the die (18) and electrically coupled to the die (18). A method for making an electronic device comprises mounting a decoupling capacitor (14) on a die (18); and electrically coupling the decoupling capacitor (14) to the die (18).

Abstract: The present application discloses a method for fabricating a semiconductor device. The method includes providing a substrate comprising a central array area and a marginal array area surrounding the central array area; concurrently forming a first bit line above the central array area and a first dummy bit line above the marginal array area; and concurrently forming a second bit line above the central array area and a second dummy bit line above the marginal array area. The second bit line is higher than and offset from the first bit line and the second dummy bit line is directly above the first dummy bit line.

Abstract: Various embodiments of the present application are directed towards a semiconductor packaging device including a shield structure configured to block magnetic and/or electric fields from a first electronic component and a second electronic component. The first and second electronic components may, for example, be inductors or some other suitable electronic components. In some embodiments, a first IC chip overlies a second IC chip. The first IC chip includes a first substrate and a first interconnect structure overlying the first substrate. The second IC chip includes a second substrate and a second interconnect structure overlying the second substrate. The first and second electronic components are respectively in the first and second interconnect structures. The shield structure is directly between the first and second electronic components.

Abstract: An integrated circuit structure includes a metal-insulator-metal (MIM) capacitor and a thin-film resistor (TFR) formed concurrently, using components of shared material layers. A first metal layer may be patterned to form lower components of an interconnect structure, MIM capacitor, and TFR, and a second metal layer may be patterned to form upper components of the interconnect structure, MIM capacitor, and TFR. A via layer may be deposited to form interconnect vias, a cup-shaped bottom electrode component of the MIM capacitor, and a pair of TFR contact vias for the TFR. An insulator layer may be patterned to form both an insulator for the MIM capacitor and an insulator cap over the TFR element.

Abstract: A semiconductor device in a first area includes first non-planar semiconductor structures separated with a first distance, and a first isolation region including a first layer and a second layer that collectively embed a lower portion of each of the first non-planar semiconductor structures. At least one of the first layer or second layer of the first isolation region is in a cured state. The semiconductor device in a second area includes second non-planar semiconductor structures separated with a second distance, and a second isolation region including a first layer and a second layer that collectively embed a lower portion of each of the second non-planar semiconductor structures. At least one of the first or second layer of the second isolation region is in a cured state.

Abstract: A microelectronic device includes a PNP transistor and NPN transistor arranged vertically in a P-type doped semiconductor substrate. The PNP and NPN transistors are manufactured by: forming an N+ doped isolating well for the PNP transistor in the semiconductor substrate; forming a P+ doped region in the N+ doped isolating well; epitaxially growing a first semiconductor layer on the semiconductor substrate; forming an N+ doped well for the NPN transistor, where at least part of the N+ doped well extends into the first semiconductor layer; then epitaxially growing a second semiconductor layer on the first semiconductor layer; forming a P doped region forming the collector of the PNP transistor in the second semiconductor layer and in electrical contact with the P+ doped region; and forming an N doped region forming the collector of the NPN transistor in the second semiconductor layer and in electrical contact with the N+ doped well.

Abstract: A semiconductor structure includes a first substrate, a first semiconductor die, a second semiconductor die, and a multi-terminal multi-capacitor structure. The first substrate includes a wiring structure. The first semiconductor die and the second semiconductor die are disposed on the first substrate. The multi-terminal multi-capacitor structure is disposed on the first substrate and includes a second substrate, an insulating layer, a first multi-terminal capacitor, and a second multi-terminal capacitor. The insulating layer is disposed over the second substrate. The first multi-terminal capacitor is disposed over the insulating layer and electrically coupled to the first semiconductor die through the wiring structure.

Abstract: A semiconductor device of an embodiment includes: a plurality of power lines extending in a first direction; and a plurality of cells arrayed along the first direction and a second direction intersecting the first direction and having a cell height of an integer multiple of a distance between the power lines adjacent to each other in the second direction, the cell height being a dimension in the second direction, wherein the plurality of cells include: a functional cell that contributes to a function of the semiconductor device; and a capacitance cell including a diffusion region of a first conductivity type and a gate electrode stacked above the diffusion region, and functioning as a decoupling capacitor, the capacitance cell is configured as a multi-height cell having a cell height of two or more times the distance, the capacitance cell includes a plurality of overlapping regions that are regions of the gate electrode overlapping the diffusion region in a stacking direction, the overlapping regions being al

Abstract: A semiconductor device according to the present disclosure includes a first interconnect structure, a first transistor over the first interconnect structure, a second transistor over the first transistor, and a second interconnect structure over the second transistor. The first transistor includes first nanostructures and a first source region adjoining the first nanostructures. The second transistor includes second nanostructures and a second source region adjoining the second nanostructures. The first source region is coupled to a first power rail in the first interconnect structure, and the second source region is coupled to a second power rail in the second interconnect structure.

Abstract: A digital integrated circuit includes first areas of a substrate which incorporate digital functions and second areas of the substrate which are filler between first areas. A capacitance is provided by interdigitated metal-insulator-metal structures formed from a metallization level above the substrate. The structures of the capacitance are vertically aligned with one or more of the second areas.

Abstract: The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor package. In one embodiment, a glass or silicon substrate is structured by micro-blasting or laser ablation to form structures for formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor package with embedded dies therein.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatus includes a first conductive contact; a second conductive contact; levels of conductive materials stacked over one another and located over the first and second conductive contacts; levels of dielectric materials interleaved with the levels of the conductive materials, the levels of conductive materials and the levels of dielectric materials formed a stack of materials; a first conductive structure located on a first side of the stack of materials and contacting the first conductive contact and a first level of conductive material of the levels of conductive materials; and a second conductive structure located on a second side of the stack of materials and contacting the second conductive contact and a second level of conductive material of the levels of conductive materials.

Abstract: A MIMO communication system is provided. The system may include a first antenna comprising a first cavity, a first plurality of RF ports for generating a feed wave within the first cavity, and a first plurality of sub-wavelength artificially structured material elements as arranged on a surface of the first cavity as RF radiators. The first antenna is configured to generate a plurality of radiation patterns respectively corresponding to the first plurality of ports. The system may also include a second antenna comprising a second cavity and a second plurality of sub-wavelength artificially structured material elements arranged on a surface of the second cavity.

Abstract: A multilayer capacitor includes: a capacitor body including first and second internal electrodes alternately stacked with a dielectric layer interposed therebetween, and having first to six surfaces, the first internal electrode being exposed through the third, fifth, and sixth surfaces, the second internal electrode being exposed through the fourth, fifth, and sixth surfaces; first and second side portions disposed on the fifth and sixth surfaces of the capacitor body; and first and second external electrodes. The capacitor body includes upper and lower cover portions disposed on an upper surface of an uppermost internal electrode and a lower surfaces of a lowermost internal electrode, respectively, in a stacking direction of the first and second internal electrodes. The first and second side portions and the upper and lower cover portions include zirconium (Zr).