Including Capacitor Component Patents (Class 257/532)
  • Patent number: 11189686
    Abstract: A package that includes a substrate, an integrated device coupled to the substrate, and a capacitor structure located between the substrate and the integrated device. The capacitor structure includes a capacitor substrate comprising a first trench, a first electrically conductive layer located in the first trench, a dielectric layer located over the first electrically conductive layer, and a second electrically conductive layer located over the dielectric layer. The first electrically conductive layer over the first trench, the dielectric layer and the second electrically conductive layer are configured as a first capacitor.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: November 30, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Jonghae Kim, Milind Shah, Periannan Chidambaram
  • Patent number: 11177395
    Abstract: A semiconductor device includes a semiconductor substrate SUB, a semiconductor layer EP formed on the semiconductor substrate SUB, a buried layer PBL formed between the semiconductor layer EP and the semiconductor substrate SUB, an isolation layer PiSO formed in the semiconductor layer EP so as to be in contact with the buried layer PBL, and a conductive film FG formed over the isolation layer PiSO via an insulating film IF, whereby a first capacitive element including the conductive film FG as an upper electrode, the insulating film IF as a capacitive insulating film, and the isolation layer PiSO as a lower electrode, is formed over the semiconductor substrate SUB.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: November 16, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Eisuke Kodama
  • Patent number: 11171199
    Abstract: The present disclosure relates to an apparatus that includes a bottom electrode and a dielectric structure. The dielectric structure includes a first dielectric layer on the bottom electrode and the first dielectric layer has a first thickness. The apparatus also includes a blocking layer on the first dielectric layer and a second dielectric layer on the blocking layer. The second dielectric layer has a second thickness that is less than the first thickness. The apparatus further includes a top electrode over the dielectric structure.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: November 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Ting Chen, Tsung-Han Tsai, Kun-Tsang Chuang, Po-Jen Wang, Ying-Hao Chen, Chien-Cheng Huang
  • Patent number: 11164862
    Abstract: An integrated resistor-capacitor (RC) structure (400) is disclosed. The integrated RC structure includes a vertical capacitor (302,402,306) and a resistive element (308,310) disposed above the capacitor. The integrated RC structure uses a low ohmic substrate (302) to ensure a good ground return path for the capacitor. Further, a resistivity of the substrate is configured such that a top plate (306) of the capacitor provides a reference ground above a predefined frequency. The impedance of the resistive element (308,310) is matched, relative to the reference ground, to a predetermined resistance. As such, the resistance of the resistive element (308,310) can be controlled to provide an impedance controlled RC structure over a range of operating frequencies.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: November 2, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Nicolas Normand, Stéphane Bouvier
  • Patent number: 11164699
    Abstract: An electronic component includes a body, a pair of external electrodes, disposed on both ends of the body in a first direction, respectively, containing at least one of copper and nickel, while not containing a noble metal, a pair of metal frames connected to the pair of external electrodes, respectively, and a pair of conductive bonding layers, disposed between the external electrode and the metal frame, respectively, containing the same metal component as the external electrode.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: November 2, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Beom Joon Cho, Ki Young Kim, Woo Chul Shin, Sang Soo Park
  • Patent number: 11158590
    Abstract: A capacitor interposer layer (CIL) in a die-to-wafer three dimensional integrated circuit (3DIC) and methods of forming the same are disclosed. A CIL is formed in a wafer under a power distribution network (PDN) die area of a chip. Electrical connections between the wafer and the chip are formed using a copper-to-copper bond. This placement allows the capacitor to be close to the PDN die area within the chip to reduce equivalent series resistance (ESR) and equivalent series inductance (ESL), while permitting a relatively low profile device with reduced PDN voltage droop.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: October 26, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Je-Hsiung Lan, Jonghae Kim, Jinseong Kim, Periannan Chidambaram
  • Patent number: 11152458
    Abstract: A metal capacitor provided includes a first metal layer and a second metal layer disposed above a substrate. The first metal layer includes a first electrode sheet and a second electrode sheet, and the second metal layer includes a third electrode sheet and a fourth electrode sheet. The first electrode sheet and the second electrode sheet collectively form a first coplanar capacitor. The third electrode sheet and the fourth electrode sheet collectively form a second coplanar capacitor. At least a portion of the fourth electrode sheet is arranged above the first electrode sheet, and the first electrode sheet and the fourth electrode sheet collectively form a first vertical capacitor. At least a portion of the third electrode sheet is arranged above the second electrode sheet, and the second electrode sheet and the third electrode sheet collectively form a second vertical capacitor.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: October 19, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chung-Kuang Chen, Chia-Ching Li, Chien-Fu Huang, Chia-Ming Hu
  • Patent number: 11152368
    Abstract: A semiconductor device includes a substrate, a storage node electrode disposed on the substrate, a dielectric layer at least partially covering the storage node electrode, and a plate electrode dispose on the dielectric layer. The storage node electrode has a pillar shape, and includes a seam disposed therein. The storage node electrode includes a concave side surface disposed at a higher level than the seam.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: October 19, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoonyoung Choi, Byunghyun Lee, Seungjin Kim, Byeongjoo Ku, Sangjae Park, Hangeol Lee
  • Patent number: 11145465
    Abstract: Dielectric patterns may be additionally disposed in margin portions, and thicknesses of the dielectric patterns may be controlled to improve the reliability of a capacitor component.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: October 12, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Young Hoon Song, Byung Yong Wang, Tae Hyeong Kim, Dong Kyu Lee
  • Patent number: 11145593
    Abstract: A method of manufacturing a semiconductor structure includes: providing a substrate; forming a first conductive layer having a first opening over the substrate; depositing a first dielectric layer over the first conductive layer and covering the first opening; forming a second conductive layer having a second opening over the first dielectric layer; depositing a second dielectric layer over the second conductive layer and covering the second opening; performing an etching operation through the second dielectric layer at the second opening and the first dielectric layer at the first opening to form a first via; and forming a first conductive structure in the first via.
    Type: Grant
    Filed: July 3, 2020
    Date of Patent: October 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Chung-Yen Chou
  • Patent number: 11145592
    Abstract: Semiconductor devices and methods of forming the same are provided. A method according to an embodiment includes receiving a substrate including a lower contact feature, depositing a first dielectric layer over a substrate, forming a metal-insulator-metal (MIM) structure over the first dielectric layer, depositing a second dielectric layer over the MIM structure, performing a first etch process to form an opening that extends through the second dielectric layer to expose the MIM structure, performing a second etch process to extend the opening through the MIM structure to expose the first dielectric layer; and performing a third etch process to further extend the opening through the first dielectric layer to expose the lower contact feature. Etchants of the first etch process and the third etch process include fluorine while the etchant of the second etch process is free of fluorine.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: October 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsiang-Ku Shen, Jian-Ming Huang, Han-Yi Chen, Ecko Lu, Hsiang-Yu Tsai, Chih-Hung Lu, Wen-Tung Chen
  • Patent number: 11145509
    Abstract: In an embodiment, a method for forming features for semiconductor processing. A first mandrel and a second mandrel are formed on a substrate. A first spacer is formed along a first sidewall of the first mandrel, and a second spacer is formed along a second sidewall of the second mandrel. A gap is defined between the first spacer and the second spacer. The gap is filled by a gap-filling material. In some examples, the gap-filling material includes a doped silicon material. In some examples, the first spacer and the second spacer each include a doped silicon material.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: October 12, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Takehito Koshizawa, Rui Cheng, Tejinder Singh, Hidetaka Oshio
  • Patent number: 11139286
    Abstract: According to an example embodiment of the present inventive concept, a semiconductor device includes a substrate. A first insulating layer is disposed on the substrate. A thin-film resistor is disposed in the first insulating layer. A capacitor structure is disposed on the first insulating layer and includes a first electrode pattern, a first dielectric pattern, a second electrode pattern, a second dielectric pattern and a third electrode pattern sequentially stacked. A first via is connected to the first electrode pattern and the third electrode pattern. A part of the first via is disposed in the first insulating layer. A second via is connected to the second electrode pattern, and a third via is connected to the thin-film resistor.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: October 5, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Shaofeng Ding
  • Patent number: 11139206
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure passing through the substrate. The semiconductor device structure includes a conductive shielding structure passing through the substrate and surrounding the first insulating layer. The semiconductor device structure includes a second insulating layer passing through the substrate and surrounding the conductive shielding structure. The semiconductor device structure includes a second conductive structure passing through the substrate. The semiconductor device structure includes a third insulating layer passing through the substrate and surrounding the second conductive structure. The semiconductor device structure includes a conductive layer passing through the first insulating layer.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: October 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Hua Yu, Chuei-Tang Wang
  • Patent number: 11130673
    Abstract: A packaging method and a packaging structure are provided. The packaging method includes providing a cap wafer including a groove; forming a sacrificial layer in the groove and a first device on the sacrificial layer; providing a substrate wafer and a second device formed on the substrate wafer; bonding a surface of the cap wafer having the first device formed thereon with a surface of the substrate wafer having the second device formed thereon, to form an electrical connection between the first device and the second device; and removing the sacrificial layer from a side of the cap wafer away from the substrate wafer, to form a cavity. The first device is located in the cavity.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: September 28, 2021
    Assignee: Ningbo Semiconductor International Corporation
    Inventor: Tianlun Yang
  • Patent number: 11127736
    Abstract: A method of making MIM capacitors includes: forming well regions in a semiconductor substrate, forming a gate dielectric layer on the semiconductor substrate, forming a polysilicon gate structure on a surface of the well region, forming a dummy gate on the gate dielectric layer and removing the dummy gate to expose the gate dielectric layer, and forming a metal gate structure on the exposed gate dielectric layer, wherein the metal gate structure comprises an electrode barrier layer on the gate dielectric layer and a metal gate on the gate dielectric layer. A lower electrode plate of the MIM capacitor is formed in the process of forming the metal gate structure, forming a capacitor dielectric layer above the lower electrode plate, and forming an upper electrode plate on the capacitor dielectric layer. Manufacturing of the MIM capacitor can be integrated in the process of manufacturing the semiconductor integrated circuit.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: September 21, 2021
    Assignee: Shanghai Huali Integrated Circuit Corporation
    Inventor: Yongji Mao
  • Patent number: 11119369
    Abstract: Disclosed is an array substrate including a first substrate, a first conductive layer, a first passivation layer, a second conductive layer, a second passivation layer, a first electrode layer, a liquid crystal layer, a second electrode layer, and a second substrate in order from bottom to top. The first conductive layer includes a plurality of first traces, the second conductive layer includes a plurality of second traces, and the respective plurality of first traces are connected to the corresponding plurality of second traces through traces of the first electrode layer. Each of the plurality of first traces is provided with a target area and a projection of each of the plurality of second traces on a corresponding connected first trace is located in a corresponding target area to reduce a load of a gate drive circuit and a capacitance between panels.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: September 14, 2021
    Assignee: HKC CORPORATION LIMITED
    Inventor: Yunqin Hu
  • Patent number: 11121109
    Abstract: An integrated circuit includes a package substrate that includes first and second electrical traces. The integrated circuit includes first, second, third, and fourth configurable dies, which are mounted on the package substrate. The first and second configurable dies are arranged in a first row. The third and fourth configurable dies are arranged in a second row, which is approximately parallel to the first row. The first and third configurable dies are arranged in a first column. The second and fourth configurable dies are arranged in a second column, which is approximately parallel to the first column. The first electrical trace couples the first and third configurable dies, and the second electrical trace couples the second and third configurable dies. The second electrical trace is oblique with respect to the first electrical trace. The oblique trace improves the latency of signals transmitted between dies and thereby increases the circuit operating speed.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: September 14, 2021
    Assignee: Intel Corporation
    Inventors: Md Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy
  • Patent number: 11114398
    Abstract: An integrated circuit (IC) device includes a lower electrode formed on a substrate, and an upper support structure disposed around the lower electrode and supporting the lower electrode. The upper support structure includes an upper support pattern surrounding the lower electrode and extending in a lateral direction parallel to the substrate, the upper support pattern having a hole through which the lower electrode passes, and an upper spacer support pattern between the upper support pattern and the lower electrode inside the hole and having an outer sidewall in contact with the upper support pattern and an inner sidewall in contact with the lower electrode, wherein a width of the upper spacer support pattern in the lateral direction decreases in a direction toward the substrate. To manufacture an IC device, an upper support pattern is formed on a substrate. An upper spacer support film is formed to cover a sidewall and a top surface of the upper support pattern.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: September 7, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dongwoo Kim, Hyukwoo Kwon, Seongmin Choo, Byoungdeog Choi
  • Patent number: 11114373
    Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a semiconductor device includes a metal-insulator-metal structure which includes a bottom conductor plate layer including a first opening and a second opening, a first dielectric layer over the bottom conductor plate layer, a middle conductor plate layer over the first dielectric layer and including a third opening, a first dummy plate disposed within the third opening, and a fourth opening, a second dielectric layer over the middle conductor plate layer, and a top conductor plate layer over the second dielectric layer and including a fifth opening, a second dummy plate disposed within the fifth opening, a sixth opening, and a third dummy plate disposed within the sixth opening. The first opening, the first dummy plate, and the second dummy plate are vertically aligned.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: September 7, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yuan-Yang Hsiao, Hsiang-Ku Shen, Dian-Hau Chen
  • Patent number: 11107850
    Abstract: Image sensors are provided. The image sensor may include a substrate including a first surface and a second surface opposite the first surface, a photoelectric conversion layer in the substrate, and a lower capacitor connection pattern on the first surface of the substrate. The second surface of the substrate may be configured to receive incident light. The lower capacitor connection pattern may include a capacitor region and a landing region protruding from the capacitor region. The image sensors may also include a capacitor structure including a first conductive pattern, a dielectric pattern, and a second conductive pattern sequentially stacked on the capacitor region, a first wire on the capacitor structure and connected to the second conductive pattern, and a second wire connected to the landing region. The first conductive pattern may be connected to the lower capacitor connection pattern.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: August 31, 2021
    Inventors: Joo Sung Moon, In Gyu Baek, Seung Han Yoo, Hae Min Lim, Min Jung Chung, Jin Yong Choi
  • Patent number: 11107880
    Abstract: Embodiments of the disclosure provide a capacitor structure for an integrated circuit (IC), and methods to form the capacitor structure. The capacitor structure may include: a first ring electrode in an inter-level dielectric (ILD) layer on a substrate; an inner electrode positioned within the first ring electrode; and a capacitor dielectric separating the first ring electrode and the inner electrode, and separating a bottom surface of the inner electrode from the ILD layer.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: August 31, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Dewei Xu, Sunil K. Singh, Siva R. Dangeti, Seung-Yeop Kook
  • Patent number: 11107821
    Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: August 31, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin K. Chan, Sivananda K. Kanakasabapathy, Babar A. Khan, Masaharu Kobayashi, Effendi Leobandung, Theodoras E. Standaert, Xinhui Wang
  • Patent number: 11101222
    Abstract: A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: August 24, 2021
    Assignee: Intel Corporation
    Inventors: Srinivas V. Pietambaram, Sri Ranga Sai Boyapati, Robert A. May, Kristof Darmawikarta, Javier Soto Gonzalez, Kwangmo Lim
  • Patent number: 11088070
    Abstract: A method of forming a multi-level interconnect structure in a semiconductor device is disclosed. In one aspect, the device includes a first interconnection level including a first dielectric layer and a first conductive structure; a second interconnection level including a second dielectric layer and a second conductive structure; and a third interconnection level including a third dielectric layer and a third conductive structure. The method includes forming a trench in the third dielectric layer; providing a first sacrificial material in the trench; and thereafter forming a via extending through the third interconnection level to the second conductive structure; providing a second sacrificial material in the via; forming a multi-level via extending through the third interconnection level to the first conductive structure; removing the first and second sacrificial materials; and depositing a conductive material at least partially filling: the trench; the via; and the multi-level via.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: August 10, 2021
    Assignee: IMEC vzw
    Inventors: Basoene Briggs, Vladimir Machkaoutsan, Zsolt Tokei
  • Patent number: 11087927
    Abstract: A substrate that includes a base layer having a first principal surface defining a plurality of first trenches and intervening first lands, and a cover layer provided over the first principal surface of the base layer and covering the first trenches and first lands substantially conformally, wherein the surface of the cover layer remote from the first principal surface of the base layer comprises a plurality of second trenches and intervening second lands defined at a smaller scale than the first trenches and first lands. The substrate may be used to fabricate a capacitive element in which thin film layers are provided and conformally cover the second trenches and second lands of the cover layer, to create a metal-insulator-metal structure having high capacitance density.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: August 10, 2021
    Assignees: MURATA MANUFACTURING CO., LTD., COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Frédéric Voiron, Julien El Sabahy, Guy Parat
  • Patent number: 11088255
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a first gate-all-around (GAA) transistor over a first region of a substrate and a second GAA transistor over a second region of the substrate. The first GAA transistor includes a plurality of first channel members stacked along a first direction vertical to a top surface of the substrate and a first gate structure over the plurality of first channel members. The second GAA transistor includes a plurality of second channel members stacked along a second direction parallel to the top surface of the substrate and a second gate structure over the plurality of second channel members. The plurality of first channel members and the plurality of second channel members comprise a semiconductor material having a first crystal plane and a second crystal plane different from the first crystal plane. The first direction is normal to the first crystal plane and the second direction is normal to the second crystal plane.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ting Chung, Ching-Wei Tsai, Kuan-Lun Cheng
  • Patent number: 11075260
    Abstract: A device that includes a substrate, a die, and a discrete capacitor. The substrate includes a dielectric layer and a plurality of interconnects formed in the dielectric layer. The discrete capacitor is coupled to the substrate through a first solder interconnect and a second solder interconnect. The first solder interconnect and the second solder interconnect are located within the dielectric layer. The die is coupled to the substrate. In some implementations, the first solder interconnect is located in a first cavity of the dielectric layer, and the second solder interconnect is located in a second cavity of the dielectric layer. In some implementations, the substrate includes a first cavity that is filled with a first via and the first solder interconnect; and a second cavity that is filled with a second via and the second solder interconnect.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: July 27, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Kuiwon Kang, Chin-Kwan Kim, Hong Bok We, Jaehyun Yeon
  • Patent number: 11069569
    Abstract: A semiconductor device includes: a plurality of lower electrodes arranged on a substrate in a first direction, which is parallel to a main surface of the substrate, and a second direction parallel to the main surface of the substrate and perpendicular to the first direction; and a support structure pattern configured to connect the plurality of lower electrodes to each other to support the plurality of lower electrodes, on the substrate and including a plurality of open portions. The plurality of open portions have shapes extending longer in the second direction than in the first direction, and when viewed from inner sides of the plurality of open portions, the plurality of open portions are convex in the first direction and are concave in the second direction.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: July 20, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ji-hoon Kim
  • Patent number: 11044811
    Abstract: A high power radiofrequency (RF) capacitor, integrated circuit board/capacitor and methods for manufacture therefor can include a dielectric substrate, and a first metallic layer and a second metallic layer that can be deposited on opposite sides of the dielectric substrate, and a ground plane that can be co-planar with one of the metallic layers. This can establish a broadside coupling capacitance effect between the first metallic layer and the second metallic layer. The first metallic layer and the second metallic layer can have a circular profile when viewed in plan view; alternatively, the first metallic layer and second metallic layer can have a T-shaped profile when viewed in plan view. The desired profile and the desired profile geometry can depend on the design power and operating frequency for the capacitor can depend on whether the capacitor must operate as a series capacitor or a shunt capacitor.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: June 22, 2021
    Assignee: United States of America as represented by the Secretary of the Navy
    Inventor: Frederick J Verd
  • Patent number: 11043477
    Abstract: A power converter (100) comprising a semiconductor chip (101) with a first (101a) and a parallel second (101b) surface, and through-silicon vias (TSVs, 110). The chip embedding a high-side (HS) field-effect transistor (FET) interconnected with a low side (LS) FET. Surface (101a) includes first metallic pads (111) as inlets of the TSVs, and an attachment site for an integrated circuit (IC) chip (150). Surface (101b) includes second metallic pads (115) as outlets of the TSVs, and third metallic pads as terminals of the converter: Pad (123a) as HS FET inlet, pad (122a) as HS FET gate, pad (131a) as LS FET outlet, pad (132a) as LS FET gate, and gate (140a) as common HS FET and LS FET switch-node. Driver-and-controller IC chip 150) has the IC terminals connected to respective first pads.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: June 22, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Jonathan Almeria Noquil, Osvaldo Jorge Lopez, Haian Lin
  • Patent number: 11037940
    Abstract: An integrated circuit construction comprising memory comprises two memory-cell-array regions having a peripheral-circuitry region laterally there-between in a vertical cross-section. The two memory-cell-array regions individually comprise a plurality of capacitors individually comprising a capacitor storage node electrode, a shared capacitor electrode that is shared by the plurality of capacitors, and a capacitor insulator there-between. A laterally-extending insulator structure is about lateral peripheries of the capacitor storage node electrodes and is vertically spaced from a top and a bottom of individual of the capacitor storage node electrodes in the vertical cross-section. The peripheral-circuitry region in the vertical cross-section comprises a pair of elevationally-extending walls comprising a first insulative composition. A second insulative composition different from the first insulative composition is laterally between the pair of walls.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: June 15, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Mitsunari Sukekawa
  • Patent number: 11037890
    Abstract: A semiconductor assembly with a package on package (POP) structure includes a first semiconductor package having a first lower substrate, a first upper substrate facing the first lower substrate, and a first semiconductor chip mounted on an area of the first lower substrate. The POP structure further includes a second semiconductor package having a second lower substrate stacked on the first semiconductor package and spaced apart from the first semiconductor package, and a second semiconductor chip mounted in an area of the second lower substrate. At least one passive element is disposed in one of the first upper substrate and the second lower substrate and electrically connected to the second semiconductor chip.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: June 15, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki Cheol Bae, Chui Woo Park, Kwang Sub Lee, Sang Gyun Lee, Se Young Jang, Chi Hyun Cho
  • Patent number: 11037948
    Abstract: A semiconductor storage device according to one embodiment is the semiconductor storage device that includes: a cell array region having a plurality of memory cells; and an outer edge portion arranged at an end portion to surround the cell array region. A stacked body in which a plurality of conductive layers are stacked via a first insulating layer and which has a stair portion in which end portions of the plurality of conductive layers form a stair shape is provided inside the cell array region, the stair portion facing the outer edge portion. A center of at least one step of the stair portion has a recess directed to an inner side of the cell array region.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: June 15, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Sonoe Matsushita, Takahito Nishimura, Kazuyuki Yoshimochi, Yoshihiro Yanai, Satoshi Usui
  • Patent number: 11031303
    Abstract: A semiconductor structure can include a high voltage region, a first moat trench isolation structure electrically insulating the high voltage region from low voltage regions of the semiconductor structure, and a second moat trench isolation structure electrically insulating the high voltage region from the low voltage regions of the semiconductor structure. The first moat trench isolation structure can include dielectric sidewall spacers and a conductive fill material portion located between the dielectric sidewall spacers. The second moat trench isolation structure can include only at least one dielectric material, and can include a dielectric moat trench fill structure having a same material composition as the dielectric sidewall spacers and having a lateral thickness that is greater than a lateral thickness of the dielectric sidewall spacers and is less than twice the lateral thickness of the dielectric sidewall spacers.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Hung-Ling Shih, Tsung-Yu Yang, Yun-Chi Wu, Po-Wei Liu
  • Patent number: 11031458
    Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for forming the same are provided. The MIM capacitor structure includes a substrate, and the substrate includes a capacitor region and a non-capacitor region. The MIM capacitor structure includes a first electrode layer formed over the substrate, and a first spacer formed on a sidewall of the first electrode layer. The MIM capacitor structure includes a first dielectric layer formed on the first spacers, and a second electrode layer formed on the first dielectric layer. The second electrode layer extends from the capacitor region to the non-capacitor region, and the second electrode layer extends beyond an outer sidewall of the first spacer.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chih-Fan Huang, Chih-Yang Pai, Yuan-Yang Hsiao, Tsung-Chieh Hsiao, Hui-Chi Chen, Dian-Hau Chen, Yen-Ming Chen
  • Patent number: 11018121
    Abstract: Disclosed is a semiconductor package including a semiconductor chip, a first outer capacitor on the semiconductor chip including a first electrode and a second electrode, a second outer capacitor on the semiconductor chip including a first electrode pattern and a second electrode pattern, and a conductive pattern on the semiconductor chip and electrically connected to the first electrode of the first outer capacitor and the first electrode pattern of the second outer capacitor. The second electrode of the first outer capacitor is insulated from the second electrode pattern of the second outer capacitor.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: May 25, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangnam Jeong, IlJoon Kim, SunWon Kang
  • Patent number: 11018169
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a capacitor. The capacitor is over a substrate and includes a first electrode having a plurality of first electrode layers that are vertically stacked over one another. The plurality of first electrode layers respectively contact an adjacent first electrode layer in a plurality of first connection regions. A second electrode including a plurality of second electrode layers that are vertically stacked over one another. The plurality of second electrode layers respectively contact an adjacent second electrode layer in a plurality of second connection regions. The plurality of second electrode layers are respectively stacked between adjacent ones of the plurality of first electrode layers. A capacitor dielectric structure separates the plurality of first electrode layers and the plurality of second electrode layers.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yimin Huang
  • Patent number: 11004719
    Abstract: A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching holes within the third level; performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level; and performing a bonding of a fourth level above the third level, where the fourth level includes a second single crystal layer, where each of the first memory cells include one first transistor, where each of the second memory cells include one second transistor, where at least one of the first or second transistors has a channel, a source and a drain having a same doping type.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: May 11, 2021
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Patent number: 10989887
    Abstract: Various embodiments may relate to a method of forming a photonic integrated circuit package (PIC). The method may include forming a redistribution layer (RDL) over a carrier. The method may also include forming a through hole or cavity on the redistribution layer. The method may additionally include providing a stop-ring structure, the stop-ring structure including a ring of suitable material, the stop-ring structure defining a hollow space, over the redistribution layer so that the hollow space is over the through hole or cavity. The method may further include arranging a photonic integrated circuit (PIC) die over the redistribution layer so that the photonic integrated circuit (PIC) die is on the stop-ring structure. The method may also include forming a molded package by forming a mold structure to at least partially cover the photonic integrated circuit (PIC) die to form the photonic integrated circuit package.
    Type: Grant
    Filed: September 3, 2018
    Date of Patent: April 27, 2021
    Assignee: Agency for Science, Technology and Research
    Inventors: Teck Guan Lim, Surya Bhattacharya
  • Patent number: 10991793
    Abstract: A method for fabricating a double-sided capacitor is disclosed, which includes: etching trenches having depths not reaching an intermediate insulating layer and trench structures having depths exceeding the intermediate insulating layer on both sides of a silicon-on-insulator (SOI) substrate; and sequentially depositing an insulating dielectric film and a conductive material on surfaces of the trenches and the trenches, then removing insulating material at a bottom of the trenches and the trenches are filled with the conductive material to form conductive channels. The upper conductive channel of the SOI substrate is insulated from an upper layer and is electrically connected to a lower layer; and the lower conductive channel is insulated from the lower layer and is electrically connected to the upper layer.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: April 27, 2021
    Assignee: SHENZHEN WEITONGBO TECHNOLOGY CO., LTD.
    Inventors: Bin Lu, Jian Shen
  • Patent number: 10991708
    Abstract: A semiconductor device of the embodiment includes a stacked body, a first insulating layer, first and second staircase portions 2, and a second insulating layer 46. The stacked body includes a first electrode layer 41 (WLDD) and a second electrode layer 41 (SGD). The first and second staircase portions 2 are provided in a first end portion 101 a second end region 102. The second insulating layer 46 extends in the X-direction. The second insulating layer divides the second electrode layer 41 (SGD) in the X-direction direction. A length L1 in the X-direction of the second insulating layer 46 is longer than a length L2 in the x-direction of the second electrode layer 41 (SGD) and shorter than a length L3 in the X-direction of the first electrode layer 41 (WLDD).
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: April 27, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Wataru Sakamoto, Hiroshi Nakaki, Hanae Ishihara
  • Patent number: 10985163
    Abstract: The present disclosure provides a semiconductor capacitor structure. The semiconductor capacitor structure includes a substrate, a comb-like bottom electrode disposed over the substrate, a top electrode disposed over the comb-like bottom electrode, and a dielectric layer sandwiched between the top electrode and the comb-like bottom electrode. The comb-like bottom electrode includes a plurality of tooth portions parallel to the substrate and a supporting portion coupled to the plurality of tooth portions and perpendicular to the substrate.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: April 20, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chung-Lin Huang
  • Patent number: 10978552
    Abstract: A method of manufacturing a semiconductor device includes forming a preliminary lower electrode layer on a substrate, the preliminary lower electrode layer including a niobium oxide; converting at least a portion of the preliminary lower electrode layer to a first lower electrode layer comprising a niobium nitride by performing a nitridation process on the preliminary lower electrode layer; forming a dielectric layer on the first lower electrode layer; and forming an upper electrode on the dielectric layer.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: April 13, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun-goo Kang, Sang-yeol Kang, Youn-soo Kim, Jin-su Lee, Hyung-suk Jung, Kyu-ho Cho
  • Patent number: 10950178
    Abstract: A vertically stacked pixel circuit is provided that includes a high voltage device for driving a pixel on an upper silicon layer, and low voltage circuitry (such as matrix addressing circuitry, data storage circuitry and uniformity compensation circuitry) on a lower silicon layer. The circuitry on the upper and lower silicon layers are electrically connected via a through-silicon via. This unique arrangement allows the high voltage device for driving a pixel to be physically located on top of the larger number of low voltage devices in the lower silicon layer in order to achieve a substantial reduction in overall pixel emission area. The vertically stacked pixel circuit is particularly suited for organic light-emitting diode microdisplays.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: March 16, 2021
    Assignee: eMagin Corporation
    Inventor: Ihor Wacyk
  • Patent number: 10950630
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: March 16, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Masayoshi Tagami, Jun Iijima, Ryota Katsumata, Kazuyuki Higashi
  • Patent number: 10945335
    Abstract: Apparatuses and methods related to the field of microchip assembly and handling, in particular to devices and methods for assembling and handling microchips manufactured with solid edge-to-edge interconnects, such as Quilt Packaging® interconnect technology. Specialized assembly tools are configured to pick up one or more microchips, place the microchips in a specified location aligned to a substrate, package, or another microchip, and facilitate electrical contact through one of a variety of approaches, including solder reflow. This specialized assembly tooling performs heating functions to reflow solder to establish electrical and mechanical interconnections between multiple microchips. Additionally, the interconnected microchips may be arranged in an arbitrarily large array.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: March 9, 2021
    Assignee: Indiana Integrated Circuits, LLC
    Inventors: Jason M. Kulick, Tian Lu
  • Patent number: 10943869
    Abstract: Multiple component package structures are described in which an interposer chiplet is integrated to provide fine routing between components. In an embodiment, the interposer chiplet and a plurality of conductive vias are encapsulated in an encapsulation layer. A first plurality of terminals of the first and second components may be in electrical connection with the plurality of conductive pillars and a second plurality of terminals of first and second components may be in electrical connection with the interposer chiplet.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: March 9, 2021
    Assignee: Apple Inc.
    Inventors: Jun Zhai, Chonghua Zhong, Kunzhong Hu
  • Patent number: 10934158
    Abstract: An integrated semiconductor device includes: a MEMS structure; an ASIC electronic circuit; and conductive interconnection structures electrically coupling the MEMS structure to the ASIC electronic circuit. The MEMS structure and the ASIC electronic circuit are integrated starting from a same substrate including semiconductor material; wherein the MEMS structure is formed at a first surface of the substrate, and the ASIC electronic circuit is formed at a second surface of the substrate, vertically opposite to the first surface in a direction transverse to a horizontal plane of extension of the first surface and of the second surface.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: March 2, 2021
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Alessandro Tocchio, Lorenzo Corso
  • Patent number: 10937789
    Abstract: A semiconductor structure is provided in which a nanosheet device is formed laterally adjacent, but in proximity to, an embedded dynamic random access memory (eDRAM) cell. The eDRAM cell and the nanosheet device are connected by a doped polycrystalline semiconductor material that is formed during the epitaxial growth of doped single crystalline semiconductor source/drain regions of the nanosheet device. An eDRAM cut mask is used to remove unwanted semiconductor material from regions not including the eDRAM cell and the nanosheet device.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: March 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Muthumanickam Sankarapandian, Donald F. Canaperi, Keith E. Fogel