Including Capacitor Component Patents (Class 257/532)
  • Patent number: 10381374
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: August 13, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Masayoshi Tagami, Jun Iijima, Ryota Katsumata, Kazuyuki Higashi
  • Patent number: 10378103
    Abstract: A molecular sensor includes a substrate defining a substrate plane, and a plurality of pairs of electrode sheets above or below the substrate at an angle to the substrate plane. The molecular sensor further includes a plurality of inner dielectric sheets between each electrode sheet in each pair of electrode sheets of the plurality of pairs, and an outer dielectric sheet between each pair of electrode sheets of the plurality of pairs.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: August 13, 2019
    Assignee: Roswell Biotechnologies, Inc.
    Inventors: Sungho Jin, Barry L. Merriman, Tim Geiser, Chulmin Choi, Paul Mola
  • Patent number: 10373982
    Abstract: A semiconductor device includes a oxide semiconductor layer, a gate electrode arranged above the oxide semiconductor layer, a gate insulation layer between the oxide semiconductor layer and the gate electrode, a first insulation layer arranged above the oxide semiconductor layer and arranged with a first aperture part, wiring including an aluminum layer arranged above the first insulation layer, the wiring being electrically connected to the oxide semiconductor layer via the first aperture part, a barrier layer including aluminum oxide above the first insulation layer, above the wiring and covering a side surface of the wiring, and an organic insulation layer arranged above the barrier layer.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: August 6, 2019
    Assignee: Japan Display Inc.
    Inventors: Toshinari Sasaki, Hajime Watakabe, Akihiro Hanada, Marina Shiokawa
  • Patent number: 10373961
    Abstract: A semiconductor device includes first wiring line patterns on a support layer, second wiring line patterns on the first wiring line patterns, and a multiple insulation pattern. The first wiring line patterns extend in a first direction and are spaced apart from each other in a second direction. The support layer includes first contact hole patterns between the first wiring line patterns that are spaced apart from each other in the first and second directions. The second wiring line patterns extend in the second direction perpendicular and are spaced apart from each other in the first direction. The multiple insulation pattern is on an upper surface of the support layer where the first contact hole patterns are not formed, arranged in a third direction perpendicular to the first direction and the second direction, and between the first wiring line patterns and the second wiring line patterns.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: August 6, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD
    Inventors: Chan-sic Yoon, Ki-seok Lee, Jung-hyun Kim, Je-min Park
  • Patent number: 10373905
    Abstract: Semiconductor devices are provided which have MIM (metal-insulator-metal) capacitor structures that are integrated within air gaps of on-chip interconnect structures, as well as methods for integrating MIM capacitor formation as part of an air gap process flow for fabricating on-chip interconnect structures. For example, a semiconductor device includes a dielectric layer with a first pattern of metal lines and second pattern of metal lines. Air gaps are disposed in spaces between the metal lines. Portions of the spaces between the metal lines of the first pattern of metal lines include a conformal layer of insulating material disposed on sidewalls of the metal lines and metallic material that fills the spaces between the metal lines. The first pattern of metal lines comprises a first capacitor electrode, the metallic fill material comprises a second capacitor electrode, and the conformal layer of insulating material comprises an insulating layer of a MIM capacitor structure.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 10366831
    Abstract: A multilayer capacitor has dielectric layers and multiple internal electrode layers. The laminate includes a stack of multiple dielectric layers made of dielectric material and has a first principal face and a second principal face on the opposite side of the first principal face. In an embodiment, the multiple internal electrode layers have Ni as a primary component, contain at least one metal element selected from Pt, Ru, Rh, Re, Ir, Os, and Pd, and are arranged in parallel with the first principal face and second principal face inside the laminate in such a way that they alternate from the opposing sides with the dielectric layers placed in between, wherein each of the internal electrode layer closest to the first principal face and the internal electrode layer closest to the second principal face has a distance of 30 ?m or less from the corresponding principal face.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: July 30, 2019
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Kotaro Mizuno, Yoichi Kato, Yukihiro Konishi
  • Patent number: 10355073
    Abstract: A semiconductor device includes a lower electrode structure, an upper electrode structure, and a dielectric layer between the lower and upper electrode structures and on side surfaces and an upper surface of the lower electrode structure. The lower electrode structure includes a first lower electrode pattern having a cylindrical shape, a barrier layer on the first lower electrode pattern, and a second lower electrode pattern in a space defined by the barrier layer.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: July 16, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-suk Lee, Ji-won Yu, Ji-woon Park
  • Patent number: 10354920
    Abstract: Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Pai-Chieh Wang, Tung-Heng Hsieh, Yimin Huang, Chung-Hui Chen
  • Patent number: 10355074
    Abstract: A monolayer thin film capacitor includes: a bottom electrode; a top electrode; a dielectric layer disposed between the bottom electrode and the top electrode; a first via formed in the dielectric layer so as to penetrate through the dielectric layer; a second via formed in the top electrode so as to penetrate through the top electrode and having a greater width or a greater diameter than that of the first via; and a connection electrode disposed on inner sides of the first and second vias, electrically connected to the bottom electrode, and electrically insulated from the top electrode.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: July 16, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jong Pil Lee, Jong Bong Lim, Hai Joon Lee, Ji Hyun Park
  • Patent number: 10355097
    Abstract: The present disclosure provides a thin film transistor (TFT), an array substrate, a display panel and a display device. The TFT includes a gate electrode, a gate insulating layer, a source electrode, a drain electrode and an active layer arranged on a base substrate, wherein there is a plurality of overlapping regions separated from each other where a projection of the gate electrode on the base substrate and a projection of the active layer on the base substrate overlap each other.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: July 16, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Lu Yang, Wentao Wang, Xiaowen Si, Haifeng Xu, Jinfeng Wang, Lei Yan, Lei Yao, Feng Li
  • Patent number: 10355121
    Abstract: A semiconductor device, the device including: a first stratum including memory periphery circuits; a second stratum including an array of first memory cells, where the first stratum is overlaid by the second stratum; a third stratum including an array of second memory cells, where the second stratum is overlaid by the third stratum, where the first memory cells include a plurality of first polysilicon structures and the second memory cells include a plurality of second polysilicon structures, and where at least one of the first memory cells is self-aligned to at least one of the second memory cells.
    Type: Grant
    Filed: October 7, 2017
    Date of Patent: July 16, 2019
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Yuniarto Widjaja
  • Patent number: 10340195
    Abstract: A method for co-integrating finFETs of two semiconductor material types, e.g., Si and SiGe, on a bulk substrate is described. Fins for finFETs may be formed in an epitaxial layer of a first semiconductor type, and covered with an insulator. A portion of the fins may be removed to form voids in the insulator, and the voids may be filled by epitaxially growing a semiconductor material of a second type in the voids. The co-integrated finFETs may be formed at a same device level.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: July 2, 2019
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Nicolas Loubet, Prasanna Khare, Qing Liu
  • Patent number: 10340243
    Abstract: A circuit substrate includes: a base material; and a capacitor layer. The capacitor layer includes a first metal layer that is provided on the base material, a dielectric layer that is provided on the first metal layer, and a second metal layer that is provided on the dielectric layer. The first metal layer includes a first electrode region which is provided on the base material and is exposed from the dielectric layer and to which a first terminal of a capacitor element for supplying current to a circuit part through the capacitor layer is connected. The second metal layer includes a second electrode region in which the second metal layer is exposed and to which a second terminal of the capacitor element is connected.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: July 2, 2019
    Assignees: FUJI XEROX CO., LTD., NODA SCREEN CO., LTD.
    Inventors: Daisuke Iguchi, Atsunori Hattori
  • Patent number: 10340322
    Abstract: This application provides a display device and an OLED display panel. The display device comprises a storage capacitor. A part of a source and drain metal layer is a first electrode of a storage capacitor. A cathode layer is a second electrode of the storage capacitor. An electron transmitting functional layer, a passivation layer, and an inorganic pixel defining layer arranged between the first electrode and the second electrode are the dielectric materials of the storage capacitor.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: July 2, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Chunhsiung Fang, Yuanchun Wu
  • Patent number: 10319683
    Abstract: A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: June 11, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Ming Shih Yeh, Wei-Cheng Wu
  • Patent number: 10312241
    Abstract: Some embodiments include an integrated assembly having a capacitor. The capacitor has a storage node configured as an upwardly-opening container shape. The container shape has a first side surface and a second side surface. The first and second side surfaces are along outer edges of the container shape and are in opposing relation to one another. The second side surface has a lower portion vertically overlapped by the first side surface, and has an upper portion which is not vertically overlapped by the first side surface. A middle-level lattice is adjacent to the first side surface and supports the first side surface. A higher-level lattice is adjacent to the second side surface and supports the second side surface. Some embodiments include integrated memory (e.g., DRAM).
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: June 4, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Yuichi Yokoyama
  • Patent number: 10312318
    Abstract: The disclosure is directed to semiconductor structures and, more particularly, to Metal-Insulator-Metal (MIM) capacitor structures and methods of manufacture. The method includes: forming at least one gate structure; removing material from the at least one gate structure to form a trench; depositing capacitor material within the trench and at an edge or outside of the trench; and forming a first contact in contact with a first conductive material of the capacitor material and a second contact in contact with a second conductive material of the capacitor material.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: June 4, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 10306770
    Abstract: A method for manufacturing a thin-film capacitor in a circuit substrate includes: forming, on a dielectric film formed on a surface of a support member, a first electrode layer of the thin-film capacitor; forming, on the dielectric film and the first electrode layer, an insulating base material of the circuit substrate so as to bury the first electrode layer; removing the support member and exposing a surface of the dielectric film on a side opposite to the first electrode layer; patterning the dielectric film so as to leave a dielectric layer overlapping the first electrode layer; forming a first through hole in the dielectric layer so as to expose a part of a surface, on a dielectric layer side, of the first electrode layer; and forming a second electrode layer of the capacitor so as to overlap the dielectric layer including the inside of the first through hole.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: May 28, 2019
    Assignee: NODA SCREEN CO., LTD.
    Inventor: Atsunori Hattori
  • Patent number: 10304838
    Abstract: A semiconductor device and method of manufacturing are provided. The semiconductor device includes a substrate; first and second structures spaced apart from each other on the substrate in a first direction, the first structure including a first lower electrode and the second structure including a second lower electrode; a first supporter pattern disposed on the substrate to support the first and second structures, and including a first region that exposes portions of sidewalls of the first and second structures, and a second region that covers a second portion of the sidewalls; and a second supporter pattern disposed on the first supporter pattern to support the first and second structures, the second supporter pattern including a third region, the third region configured to expose portions of the first sidewall and the second sidewall, and a fourth region that covers a portion of the first and second sidewalls.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: May 28, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ye Ram Kim, Won Chul Lee
  • Patent number: 10297467
    Abstract: Self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. The first layer includes a grating of alternating metal lines and dielectric lines in a first direction. A second layer of the interconnect structure is disposed above the first layer. The second layer includes a grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. Each metal line of the grating of the second layer is disposed on a recessed dielectric line having alternating distinct regions of a first dielectric material and a second dielectric material corresponding to the alternating metal lines and dielectric lines of the first layer of the interconnect structure.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Charles H. Wallace, Paul A. Nyhus
  • Patent number: 10276542
    Abstract: A package structure has first and second dies, a molding compound, a first redistribution layer, at least one first through interlayer via (TIV), second through interlayer vias (TIVs), an electromagnetic interference shielding layer and conductive elements. The first die is molded in the molding compound. The second die is disposed on the molding compound. The first redistribution layer is located between the conductive elements and the molding compound and electrically connected to the first and second dies. The molding compound is located between the second die and the first redistribution layer. The first and second TIVs are molded in the molding compound and electrically connected to the first redistribution layer. The second TIVs are located between the first die and the first TIV. The electromagnetic interference shielding layer is in contact with the first TIV. The conductive elements are connected to the first redistribution layer.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Hsien Huang, An-Jhih Su, Hsien-Wei Chen, Hua-Wei Tseng, Jo-Mei Wang, Tien-Chung Yang, Kuan-Chung Lu
  • Patent number: 10276489
    Abstract: The present disclosure relates to an integrated circuit configured to mitigate damage to MIM decoupling capacitors. In some embodiments, the integrated chip has a lower interconnect layer vertically separated from a substrate by a first inter-level dielectric (ILD) layer. A conductive contact extends from a transistor device within the substrate to an uppermost surface of the first ILD layer. A plurality of MIM (metal-insulator-metal) structures are arranged over the lower interconnect layer. An upper interconnect layer is over the plurality of MIM structures. One or both of the lower interconnect layer and the upper interconnect layer are comprised within a conductive path that electrically couples the plurality of MIM structures in a series connection.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Chi Tu, Chin-Chieh Yang, Wen-Ting Chu
  • Patent number: 10269490
    Abstract: A capacitor may include a first set of conductive fingers interdigitated with a second set of conductive fingers at an interconnect layer in a preferred direction of the interconnect layer. The capacitor may also include the first set of conductive fingers interdigitated with the second set of conductive fingers at a next interconnect layer in the preferred direction of the next interconnect layer. The capacitor may further include a first set of through finger vias electrically coupling the first set of conductive fingers of the interconnect layer to the first set of conductive fingers of the next interconnect layer.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: April 23, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Kevin Jia-Nong Wang, Chao Song
  • Patent number: 10269807
    Abstract: A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor having a first electrode layer, a second electrode layer, and an insulating layer between the first electrode layer and the second electrode layer. At least three dielectric layers are between a bottom surface of the capacitor and the active region.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chern-Yow Hsu, Chen-Jong Wang, Chia-Shiung Tsai, Shih-Chang Liu, Xiaomeng Chen
  • Patent number: 10256249
    Abstract: Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: April 9, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Justin B. Dorhout, David Daycock, Kunal R. Parekh, Martin C. Roberts, Yushi Hu
  • Patent number: 10251272
    Abstract: Embodiments of the invention include a microelectronic device that includes a plurality of organic dielectric layers and a capacitor that is integrated with a first organic dielectric layer of the plurality of organic dielectric layers. The capacitor includes first and second conductive electrodes and an ultra-high-k dielectric layer that is positioned between the first and second conductive electrodes.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Feras Eid, Thomas L. Sounart, Georgios C. Dogiamis, Johanna M. Swan
  • Patent number: 10242741
    Abstract: The present invention discloses a low voltage difference-operated EEPROM and an operating method thereof wherein at least one transistor structure is formed in a semiconductor substrate and each includes a first electric-conduction gate. An ion implantation is performed by masking partial regions to prevent the existence of the conventional lightly doped drain (LDD) structure. An undoped region is formed in the semiconductor substrate under the two sides of the first electric-conductive gate, to increase the intensity of electric field between the gate and the substrate or between the gate and the transistor, whereby to reduce the voltage differences required for writing and erasing. The present invention also discloses an operating method for the low voltage difference-operated EEPROM. The present invention applies to the EEPROM with a single gate transistor structure.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: March 26, 2019
    Assignee: Yield Microelectronics Corp.
    Inventors: Hsin-Chang Lin, Wen-Chien Huang, Chia-Hao Tai
  • Patent number: 10236295
    Abstract: A method of fabricating a semiconductor device includes forming a material layer and a mask pattern on a substrate, mounting the substrate onto an electrostatic chuck, loading the substrate, including the material layer and the mask pattern, mounted on the electrostatic chuck, into an etching chamber, and forming a material pattern by dry etching the material layer using the mask pattern as an etching mask. The dry etching of the material layer includes adjusting a pressure of the etching chamber to adjust a lateral over-etch of the material pattern in a first direction, wherein the first direction is parallel to a surface of the substrate facing the material pattern, and adjusting a temperature of the electrostatic chuck to adjust an etching of the material pattern in a second direction, wherein the second direction crosses the first direction.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: March 19, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chanmin Lee, Youngjae Kim
  • Patent number: 10224309
    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) die. In embodiments, the IC die may include a semiconductor substrate, a plurality of active components disposed on a first side of the semiconductor substrate, and a plurality of passive components disposed on a second side of the semiconductor substrate. In embodiments the second side may be disposed opposite the first side. The passive components may, in some embodiments, include capacitors and/or resistors while the active components may, in some embodiments, include transistors. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: March 5, 2019
    Assignee: Intel Corporation
    Inventor: Kevin J. Lee
  • Patent number: 10217720
    Abstract: Apparatuses and methods are described. This apparatus includes a bridge die having first contacts on a die surface being in a molding layer of a reconstituted wafer. The reconstituted wafer has a wafer surface including a layer surface of the molding layer and the die surface. A redistribution layer on the wafer surface includes electrically conductive and dielectric layers to provide conductive routing and conductors. The conductors extend away from the die surface and are respectively coupled to the first contacts at bottom ends thereof. At least second and third IC dies respectively having second contacts on corresponding die surfaces thereof are interconnected to the bridge die and the redistribution layer. A first portion of the second contacts are interconnected to top ends of the conductors opposite the bottom ends thereof in part for alignment of the at least second and third IC dies to the bridge die.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: February 26, 2019
    Assignee: Invensas Corporation
    Inventors: Liang Wang, Rajesh Katkar
  • Patent number: 10199314
    Abstract: A flange on first open end of a tubular contact member is soldered to a conductive plate of an insulating substrate. An external electrode terminal is fitted into a main body tube portion of the tubular contact member. The tubular contact member includes a protrusion that protrudes inwardly from an inner wall of the main body tube portion. The protrusion is disposed along the entire perimeter of inner wall toward the first open end. The protrusion has a thickness deformation of the protrusion by a load applied thereto when the external electrode terminal is pressed into the main body tube portion. The protrusion is disposed at a height that can block solder that climbs the inner wall of the main body tube portion, to form a gap between the protrusion and a lower end of the external electrode terminal inserted to a predetermined depth of the main body tube portion.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: February 5, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kenshi Kai, Rikihiro Maruyama, Makoto Isozaki
  • Patent number: 10199214
    Abstract: Disclosed is a multilayer insulator, a metal-insulator-metal (MIM) capacitor with the same, and a fabricating method thereof. The capacitor includes: a first electrode; an insulator disposed on the first electrode, the insulator including: a laminate structure in which an aluminum oxide (Al2O3) layer and a hafnium oxide (HfO2) layer are laminated alternately in an iterative manner and a bottom layer and a top layer are formed of the same material; and a second electrode disposed on the insulator.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: February 5, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Kwan-Soo Kim, Soon-Wook Kim
  • Patent number: 10186479
    Abstract: A semiconductor device includes a metal plate capacitor that includes a heat-resistant metal plate and a capacitor unit including a sintered dielectric formed on at least one surface of the heat-resistant metal plate, a semiconductor chip disposed on the metal plate capacitor, a connector configured to electrically connect the semiconductor chip and the metal plate capacitor, and a protector configured to protect the semiconductor chip, the metal plate capacitor, and the connector.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: January 22, 2019
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Hidenori Katsumura, Shinya Tokunaga, Masaya Sumita, Hiroyoshi Yoshida, Yasuhiro Sugaya, Kazuhide Uriu, Osamu Shibata
  • Patent number: 10170397
    Abstract: A semiconductor device includes a via structure penetrating through a substrate, a top metal layer and an electronic component over the via structure, and a bottom metal layer and another electronic component below the via structure. The via structure includes a through hole penetrating from a first surface to an opposite second surface of a substrate, a filling insulating layer within the through hole, a first conductive layer, which is within the through hole and surrounds the filling insulating layer, wherein a portion of the first conductive layer is below the filling insulating layer and at the bottom of the through hole. The via structure further includes a first insulating layer, which is on the sidewalls of the through hole and surrounds the first conductive layer.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: January 1, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Li-Che Chen, Francois Hebert
  • Patent number: 10170363
    Abstract: An interconnection structure of the semiconductor integrated circuit device may be provided. The interconnection structure may include a first conductive pattern, a second conductive pattern, a dielectric layer and a contact part. The first conductive pattern may have a first width and a first length. The second conductive pattern may be formed over the first conductive pattern. The second conductive pattern may have a second width and a second length. The dielectric layer may be interposed between the first conductive pattern and the second conductive pattern. The contact part may be configured to simultaneously make contact with the first conductive pattern and the second conductive pattern.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: January 1, 2019
    Assignee: SK hynix Inc.
    Inventor: Jong Su Kim
  • Patent number: 10163776
    Abstract: Disclosed herein is a capacitive element formed by multilayer wirings, wherein a total capacitance, intralayer capacitance and interlayer capacitance are calculated for a plurality of device structures by changing parameters relating to the multilayer wirings in an integrated circuit, a device structure is identified, from among the plurality of device structures, whose difference in the total capacitance between the device structures is equal to or less than a predetermined level and at least either of whose ratio of the intralayer capacitance to the total capacitance or ratio of the interlayer capacitance to the total capacitance satisfies a predetermined condition, and the parameters of the device structure satisfying the predetermined condition are determined as the parameters of the multilayer wirings.
    Type: Grant
    Filed: January 5, 2010
    Date of Patent: December 25, 2018
    Assignee: Sony Corporation
    Inventors: Kyoko Izuha, Hiroaki Ammo, Yoshiyuki Enomoto
  • Patent number: 10157976
    Abstract: A system-on-chip (SOC) device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or different thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, a radio frequency region, a dynamic random access memory region, and so forth.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chi Tu, Wen-Chuan Chiang, Chen-Jong Wang
  • Patent number: 10153218
    Abstract: A semiconductor structure includes a die including a surface, a lid disposed over the surface of the die, and a thermally conductive material disposed between the die and the lid, wherein the lid includes a protrusion protruded towards the surface of the die and the thermally conductive material surrounds the protrusion. Also, a method of manufacturing a semiconductor structure includes providing a die including a surface, providing a lid, removing a portion of the lid to form a protrusion, disposing a thermally conductive material between the surface of the die and the lid, wherein the protrusion of the lid is surrounded by the thermally conductive material. Further, an apparatus for manufacturing a semiconductor structure and a method of manufacturing a semiconductor structure by the apparatus are disclosed.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: December 11, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tsung-Yu Chen, Wensen Hung, Hung-Chi Li, Cheng-Chieh Hsieh, Tung-Liang Shao, Chih-Hang Tung
  • Patent number: 10151722
    Abstract: A molecular sensor includes a substrate defining a substrate plane, and a plurality of pairs of electrode sheets above or below the substrate at an angle to the substrate plane. The molecular sensor further includes a plurality of inner dielectric sheets between each electrode sheet in each pair of electrode sheets of the plurality of pairs, and an outer dielectric sheet between each pair of electrode sheets of the plurality of pairs.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: December 11, 2018
    Assignee: Roswell Biotechnologies, Inc.
    Inventors: Sungho Jin, Barry L. Merriman, Tim Geiser, Chulmin Choi, Paul Mola
  • Patent number: 10151616
    Abstract: Level sensing designs and techniques that inherently compensate for physical variations in the flowable material. An illustrative container includes an electrode arrangement having two electrodes along a vertical span creating corresponding capacitances indicative of a level of the material within that vertical span. Differing electrode shapes or positions provide the capacitances with different dependences on the level. A level detection method includes: (i) measuring a first capacitance between a drive electrode and a first sensing electrode; (ii) measuring a second capacitance between the drive electrode and a second sensing electrode; and (iii) determining a ratio of variances in the first and second capacitances, the variances being relative to first and second capacitances for a container empty of the material. The ratio is indicative of said level and insensitive to temperature and permittivity of the material.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: December 11, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Takayasu Otagaki, Kazuyoshi Ishikawa
  • Patent number: 10139230
    Abstract: The invention relates to a detection circuit for reading out at least one position signal of a micromechanical capacitive sensor having at least one oscillating element that can be excited so as to move in an oscillating manner. In particular, the invention relates to a sensor that is operated in a closed control loop by using the detection circuit according to the invention. The invention further relates to a method for operating such a sensor. During operation, a first input connection of the detection circuit (100) is connected to an output connection of the capacitive sensor (106) and an output connection of the detection circuit (100) is connected to a loop filter of a control loop (102), wherein the control loop feeds back a feedback voltage for providing a restoring force in dependence on an output voltage of the control loop (102) to a second input connection of the detection circuit (100).
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: November 27, 2018
    Assignee: Albert-Ludwigs-Universitat Freiburg
    Inventors: Michael Maurer, Sebastian Nessler, Yiannos Manoli
  • Patent number: 10125420
    Abstract: A molecular sensor includes a substrate defining a substrate plane, and a plurality of pairs of electrode sheets above or below the substrate at an angle to the substrate plane. The molecular sensor further includes a plurality of inner dielectric sheets between each electrode sheet in each pair of electrode sheets of the plurality of pairs, and an outer dielectric sheet between each pair of electrode sheets of the plurality of pairs.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: November 13, 2018
    Assignee: Roswell Biotechnologies, Inc.
    Inventors: Sungho Jin, Barry L. Merriman, Tim Geiser, Chulmin Choi, Paul Mola
  • Patent number: 10121793
    Abstract: A semiconductor device includes storage electrodes on a substrate and one or more supporters configured to couple one or more portions of the storage electrodes. The semiconductor device may include multiple non-intersecting supporters extending in parallel to a surface of the substrate. At least one supporter may have an upper surface that is substantially coplanar with upper surfaces of the storage electrodes. The storage electrodes may include a capacitor dielectric layer that conformally covers one or more surfaces of the storage electrodes and one or more supporters. A storage electrode may include upper and lower storage electrodes coupled together. The upper and lower storage electrodes may have different horizontal widths.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: November 6, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung-Eun Kim, Yongkwan Kim, Semyeong Jang, Jaehyoung Choi, Yoosang Hwang, Bong-Soo Kim
  • Patent number: 10115784
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes: a semiconductor substrate; a first dielectric layer over the semiconductor substrate; a second dielectric layer over the first dielectric layer; an via extending through the second dielectric layer; a bottom conductive layer conformably formed at a bottom and along side walls of the via; a third dielectric layer conformably formed over the bottom conductive layer; an upper conductive layer conformably formed over the third dielectric layer; and an upper contact formed over and coupled to the upper conductive layer and filling the via; wherein the upper conductive layer provide a diffusion barrier between the upper contact and the third dielectric layer. A metal-insulator-metal (MIM) capacitor and an associated manufacturing method are also disclosed.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: October 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chung-Yen Chou, Shih-Chang Liu
  • Patent number: 10103125
    Abstract: A chip package structure is provided. The chip package structure includes a chip structure. The chip package structure includes a first ground bump below the chip structure. The chip package structure includes a conductive shielding film disposed over the chip structure and extending onto the first ground bump. The conductive shielding film is electrically connected to the first ground bump.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: October 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Hua Yu, Jing-Cheng Lin, Po-Hao Tsai, An-Jhih Su
  • Patent number: 10102905
    Abstract: Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an example, a resistance variable memory cell can include a plurality of resistance variable materials located between a plug material and an electrode material. The resistance variable memory cell also includes a first conductive material that contacts the plug material and each of the plurality of resistance variable materials and a second conductive material that contacts the electrode material and each of the plurality of resistance variable materials.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: October 16, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Ugo Russo, Andrea Redaelli, Fabio Pellizzer
  • Patent number: 10083897
    Abstract: A semiconductor package includes a leadframe having an electrically conductive paddle, electrically conductive perimeter package leads, a first electrically conductive clip electrically connected to a first set of the package leads, and a second electrically conductive clip electrically connected to a second set of the package leads. The semiconductor package includes a single semiconductor die. The die includes a front-side active layer having an integrated power structure of two or more transistors. The die includes a backside portion having a backside contact electrically coupled to at least one of the two or more transistors and to the paddle. One or more first front-side contacts of the die are electrically coupled to at least one of the transistors and to the first clip, and one or more second front-side contacts of the die are electrically coupled to at least one of the transistors and to the second clip.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: September 25, 2018
    Assignee: SILANNA ASIA PTE LTD
    Inventors: Shanghui Larry Tu, Michael A. Stuber, Befruz Tasbas, Stuart B. Molin, Raymond Jiang
  • Patent number: 10079213
    Abstract: Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a method of manufacturing a packaging device includes forming an interconnect wiring over a substrate, and forming conductive balls over portions of the interconnect wiring. A molding material is deposited over the conductive balls and the substrate, and a portion of the molding material is removed from over scribe line regions of the substrate.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: September 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Hsien-Wei Chen, Tsung-Yuan Yu, Ming-Da Cheng, Wen-Hsiung Lu
  • Patent number: 10068907
    Abstract: A dynamic random access memory (DRAM) includes a substrate, two buried word lines and a bit line contact. The substrate includes a first active area, wherein the first active area extends along a first direction. The buried word lines are disposed in the substrate and across the first active area, wherein the buried word lines extend along a second direction. The bit line contact is disposed on the substrate and overlaps the first active area between the two buried word lines, wherein the bit line contact is enclosed by a first side, a second side, a third side and a fourth side, and the first side is parallel to the third side along a third direction while the second side is parallel to the fourth side along a fourth direction, wherein the third direction is parallel to the first direction and the fourth direction is parallel to the second direction.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: September 4, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tsung-Ying Tsai, Chien-Ting Ho, Ming-Te Wei, Li-Wei Feng, Ying-Chiao Wang
  • Patent number: 10056609
    Abstract: Solid state energy storage systems and devices are provided. A solid state energy storage devices can include an active layer disposed between conductive electrodes, the active layer having one or more quantum confinement species (QCS), such as quantum dots, quantum particles, quantum wells, nanoparticles, nanostructures, nanowires and nanofibers. The solid state energy storage device can have a charge rate of at least about 500 V/s and an energy storage density of at least about 150 Whr/kg.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: August 21, 2018
    Assignee: QuantumScape Corporation
    Inventors: Timothy P. Holme, Rainer Fasching, Joseph Han, Weston Arthur Hermann, Friedrich B. Prinz, Phil Reilly, Jagdeep Singh