Including Capacitor Component Patents (Class 257/532)
  • Patent number: 10804411
    Abstract: A semiconductor device includes a capacitive device, a first conductive via, and a second conductive via. The capacitive device includes a first conductive plate, a first insulating plate, a second conductive plate, a second insulating plate, and a third conductive plate. The first conductive via is electrically coupled to the first conductive plate and the third conductive plate, and the first conductive via penetrated through a first film stack with a first thickness. The second conductive via is electrically coupled to the second conductive plate, and the second conductive via penetrated through a second film stack with a second thickness. The second thickness is substantially equal to the first thickness.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Hsing Chang, Chern-Yow Hsu, Shih-Chang Liu
  • Patent number: 10797030
    Abstract: Disclosed is a semiconductor package including a semiconductor chip, a first outer capacitor on the semiconductor chip including a first electrode and a second electrode, a second outer capacitor on the semiconductor chip including a first electrode pattern and a second electrode pattern, and a conductive pattern on the semiconductor chip and electrically connected to the first electrode of the first outer capacitor and the first electrode pattern of the second outer capacitor. The second electrode of the first outer capacitor is insulated from the second electrode pattern of the second outer capacitor.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: October 6, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangnam Jeong, IlJoon Kim, SunWon Kang
  • Patent number: 10789992
    Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the I/O pads.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: September 29, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Luisa Lin, Mohan Dunga, Venkatesh P. Ramachandra, Peter Rabkin, Masaaki Higashitani
  • Patent number: 10784334
    Abstract: The present invention discloses a method of manufacturing a capacitor, which includes the steps of forming a capacitor recess in a sacrificial layer, wherein the sidewall of capacitor recess has a wave profile, forming a bottom electrode layer on the sidewall of capacitor recess, filling up the capacitor recess with a supporting layer, removing the sacrificial layer to forma capacitor pillar made up by the bottom electrode layer and the supporting layer, forming a capacitor dielectric layer on the capacitor pillar, and forming a top electrode layer on the capacitor dielectric layer.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: September 22, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee
  • Patent number: 10784199
    Abstract: Aspects of the present disclosure are directed to systems and methods to reduce inductance on an integrated circuit package of a memory sub-system. A memory sub-system is also hereinafter referred to as a “memory device.” An example of a memory sub-system is a storage system, such as a SSD, and can be embodied as an integrated circuit package, including but not limited to a pin grid array (PGA), and ball grid array (BGA).
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: September 22, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Christopher Kinney
  • Patent number: 10777358
    Abstract: Dielectric patterns may be additionally disposed in margin portions, and thicknesses of the dielectric patterns may be controlled to improve the reliability of a capacitor component.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: September 15, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Young Hoon Song, Byung Yong Wang, Tae Hyeong Kim, Dong Kyu Lee
  • Patent number: 10777690
    Abstract: A capacitor structure includes a semiconductor substrate, a first vertical diffusion plate disposed in the semiconductor substrate, a first shallow trench isolation (STI) structure disposed in the semiconductor substrate and surrounding the first vertical diffusion plate, and a second vertical diffusion plate disposed in the semiconductor substrate and surrounding the first STI structure. The first vertical diffusion plate further includes a first lower portion that is part of the semiconductor substrate. The first lower portion is surrounded and electrically isolated by a first wafer-backside trench isolation structure. The first wafer-backside trench isolation structure is in direct contact with a bottom of the first STI structure.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: September 15, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Liang Chen
  • Patent number: 10763325
    Abstract: A capacitor structure includes an insulative layer, a first electrode over the insulative layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. The first electrode includes a first portion extending along a lateral direction of the insulative layer and a second portion connected to the first portion and extending along a depth direction of the insulative layer. The dielectric layer is substantially conformal with respect to a profile of the first electrode. A semiconductor structure thereof and a method for forming the same are also provided.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: September 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Chih-Kuang Kao
  • Patent number: 10763161
    Abstract: Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Sean King, Hui Jae Yoo, Sreenivas Kosaraju, Timothy Glassman
  • Patent number: 10756031
    Abstract: An IC device carrier includes organic substrate layers and wiring line layers therein. To reduce stain of the organic substrate layers and to provide decoupling capacitance, one or more decoupling capacitor stiffeners (DCS) are applied to the top side metallization (TSM) surface of the IC device carrier. The DCS(s) reduce the amount of curvature of the IC device carrier and reduce the strain seen by the organic substrate layers, thereby mitigating the risk for cracks forming and expanding or other damage within the carrier. The DCS(s) also include two or more capacitor plates and provides capacitance to electrically decouple electrical subsystems of the system of which the DCS is apart.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: August 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, Franklin M. Baez, Brian W. Quinlan, Charles L. Reynolds, Krishna R. Tunga, Thomas Weiss
  • Patent number: 10756091
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate which includes a cell region including first and second regions, and a peri region more adjacent to the second region than adjacent to the first region, first and second lower electrodes disposed in the first and second regions, respectively, first and second lower support patterns disposed on outer walls of the first and second lower electrodes, respectively, an upper support pattern disposed on outer walls of the first and second lower electrodes, and being on and spaced apart from the first and second lower support patterns, a dielectric layer disposed on surfaces of the first and second lower electrodes, the first and second lower support patterns, and the upper support pattern, and an upper electrode disposed on a surface of the dielectric layer, wherein thickness of the first lower support pattern is smaller than thickness of the second lower support pattern.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: August 25, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji Ung Pak, Won Chul Lee
  • Patent number: 10748928
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: August 18, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Masayoshi Tagami, Jun Iijima, Ryota Katsumata, Kazuyuki Higashi
  • Patent number: 10741636
    Abstract: A semiconductor structure and a method of fabricating thereof are provided. The semiconductor structure includes a substrate and a capacitor structure. The substrate has a first blind hole and a trench. The first blind hole communicates with the trench. The first blind hole has a first depth, and the trench has a second depth smaller than the first depth. The capacitor structure includes a first inner conductor, a first inner insulator, and an outer conductor. The first inner conductor is in the first blind hole. The first inner insulator surrounds the first inner conductor. The outer conductor has a first portion surrounding the first inner insulator and an extending portion extending from the first portion. The first portion is in the first blind hole, and the extending portion is in the trench. The first inner conductor is separated from the outer conductor by the first inner insulator.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: August 11, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Tieh-Chiang Wu
  • Patent number: 10727295
    Abstract: A wafer level package which includes an IC chip; a rewiring layer on the IC chip; and a capacitor embedded in the rewiring layer.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: July 28, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Tatsuya Funaki, Noriyuki Inoue
  • Patent number: 10714480
    Abstract: A method for fabricating a semiconductor device includes the following steps. First, a contact structure is formed in the insulating layer. Preferably, the contact structure includes a bottom portion in part of the insulating layer and a top portion on part of the bottom portion and extending to cover part of the insulating layer. Next, a dielectric layer is formed on the bottom portion and the top portion, part of the dielectric layer is removed to form a first opening exposing part of the top portion and part of the bottom portion, and a capacitor is formed in the first opening and contacting the pad portion and the contact portion directly.
    Type: Grant
    Filed: October 28, 2018
    Date of Patent: July 14, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee
  • Patent number: 10714420
    Abstract: Devices and methods are provided for fabricating a metal-insulator-metal capacitor within an interconnect structure (e.g., back-end-of-line interconnect structure) to provide capacitive decoupling between positive and negative power supply voltage lines of a power distribution network. Various via contact configurations including interlevel via contacts and truncated via contacts are utilized to connect the metal-insulator-metal capacitor electrodes to power supply voltage lines of the power distribution network to provide an array of high-density, low resistance via contact connections at various locations across the capacitor electrodes to reduce the resistance of the metal-insulator-metal capacitor and, thus, enhance the transient response time and increase the cutoff frequency of the metal-insulator-metal capacitor.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: July 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Joshua M. Rubin, Joel A. Silberman, Robert Groves
  • Patent number: 10714408
    Abstract: A package includes a substrate having an electronic component flip chip mounted thereto by flip chip bumps. The electronic component includes an active surface and an inactive surface. Electrically conductive columns (TSV) extend through the electronic component between the active surface and the inactive surface. A RDL structure is coupled to the inactive surface, the RDL structure redistributing the pattern of the electrically conductive columns at the inactive surface to a pattern of inactive surface RDL lands. The inactive surface RDL lands are exposed through via apertures of a package body. By using the inactive surface of the electronic component to distribute the inactive surface RDL lands, the allowable size of the electronic component is maximized.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: July 14, 2020
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Louis W. Nicholls, Roger D. St. Amand, Jin Seong Kim, Woon Kab Jung, Sung Jin Yang, Robert F. Darveaux
  • Patent number: 10707212
    Abstract: A method of forming an apparatus comprises forming a first metal nitride material over an upper surface of a conductive material within an opening extending through at least one dielectric material through a non-conformal deposition process. A second metal nitride material is formed over an upper surface of the first metal nitride material and side surfaces of the at least one dielectric material partially defining boundaries of the opening through a conformal deposition process. A conductive structure is formed over surfaces of the second metal nitride material within the opening. Apparatuses and electronic systems are also described.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: July 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kentaro Ishii, Yongjun J. Hu, Amirhasan Nourbakhsh, Durai Vishak Nirmal Ramaswamy, Christopher W. Petz, Luca Fumagalli
  • Patent number: 10706913
    Abstract: A memory stack comprises at least two memory components. The memory components have a first data link interface and are to transmit signals on a data link coupled to the first data link interface at a first voltage level. A buffer component has a second data link interface coupled to the data link. The buffer component is to receive signals on the second data link interface at the first voltage level. A level shifting latch produces a second voltage level in response to receiving the signals at the second data link interface, where the second voltage level is higher than the first voltage level.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: July 7, 2020
    Assignee: RAMBUS INC.
    Inventors: Frederick A. Ware, John Eric Linstadt, Thomas Vogelsang
  • Patent number: 10700162
    Abstract: A method for fabricating a capacitor includes: forming a bottom electrode; forming a dielectric layer on the bottom electrode; forming a metal oxide layer including a metal having a high electronegativity on the dielectric layer; forming a sacrificial layer on the metal oxide layer to reduce the metal oxide layer to a metal layer; and forming a top electrode on the sacrificial layer to convert the reduced metal layer into a high work function interface layer.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: June 30, 2020
    Assignee: SK hynix Inc.
    Inventors: Beom-Yong Kim, Deok-Sin Kil, Hee-Young Jeon
  • Patent number: 10680012
    Abstract: According to one embodiment, there is provided a semiconductor device including a stacked body, a semiconductor columnar member, an insulating film, and a structure. The stacked body is disposed above a semiconductor substrate. In the stacked body, a conductive film and an insulating layer are alternately disposed in a stacking direction. The semiconductor columnar member penetrates the stacked body in the stacking direction. The insulating film surrounds the semiconductor columnar member and penetrates the stacked body in the stacking direction. The structure is disposed in a peripheral circuit region on the semiconductor substrate. The peripheral circuit region is a region including a plurality of circuit blocks. The structure has a plate-shaped portion extending at least between the plurality of circuit blocks.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: June 9, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shihoko Asai, Hisakazu Matsumori, Yasuko Takechi
  • Patent number: 10679688
    Abstract: A memory cell and method for utilizing the memory cell are described. The memory cell includes at least one ferroelectric transistor (FE-transistor) and at least one selection transistor coupled with the FE-transistor. An FE-transistor includes a transistor and a ferroelectric capacitor for storing data. The ferroelectric capacitor includes ferroelectric material(s). In some aspects, the memory cell consists of a FE-transistor and a selection transistor. In some aspects, the transistor of the FE-transistor includes a source, a drain and a gate coupled with the ferroelectric capacitor. In this aspect, the selection transistor includes a selection transistor source, a selection transistor drain and a selection transistor gate. In this aspect, a write port of the memory cell is the selection transistor source or the selection transistor drain. The other of the selection transistor source and drain is coupled to the ferroelectric capacitor.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: June 9, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Titash Rakshit, Borna J. Obradovic, Ryan M. Hatcher, Jorge A. Kittl
  • Patent number: 10672864
    Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: June 2, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tzu-Chin Wu, Wei-Hsin Liu, Yi-Wei Chen, Chia-Lung Chang, Jui-Min Lee, Po-Chun Chen, Li-Wei Feng, Ying-Chiao Wang, Wen-Chieh Lu, Chien-Ting Ho, Tsung-Ying Tsai, Kai-Ping Chen
  • Patent number: 10673326
    Abstract: A semiconductor device including: a semiconductor substrate; at least one circuit block provided on a main surface of the semiconductor substrate and having a predetermined function; a wiring layer including plural metal layers that connect the circuit block; and plural capacitors including a first capacitor connected to the circuit block and that uses the plurality of metal layers, and a second capacitor that uses an active area disposed within the main surface of the semiconductor substrate, wherein at least one of the first capacitor and at least one of the second capacitor are stacked in a stacking direction of layers of the semiconductor.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: June 2, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Masayuki Otsuka
  • Patent number: 10665550
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hui Yu Lee, Chin-Chou Liu, Cheng-Hung Yeh, Fong-Yuan Chang, Po-Hsiang Huang, Yi-Kan Cheng, Ka Fai Chang
  • Patent number: 10658286
    Abstract: A capacitor cell for a semiconductor device, wherein the capacitor cell comprises: a capacitor having a first node and a second node; a first electrode structure, comprising a first contact point and a second contact point, wherein the first contact point and the second contact point are electrically connected to the first node of said capacitor and located at two different edges of the capacitor cell; and a second electrode structure, comprising a third contact point and a fourth contact point, wherein the third contact point and the fourth contact point are electrically connected to the second node of said capacitor and located at said two different edges of the capacitor cell.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: May 19, 2020
    Assignee: Nuvoton Technology Corporation
    Inventors: Fu-Sheng Hsu, Ming-Chun Liang
  • Patent number: 10651149
    Abstract: A method includes bonding a first device die and a second device die to a substrate, and filling a gap between the first device die and the second device die with a gap-filling material. A top portion of the gap-filling material covers the first device die and the second device die. Vias are formed to penetrate through the top portion of the gap-filling material. The vias are electrically coupled to the first device die and the second device die. The method further includes forming redistribution lines over the gap-filling material using damascene processes, and forming electrical connectors over and electrically coupling to the redistribution lines.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: May 12, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Chen-Hua Yu
  • Patent number: 10651138
    Abstract: A microwave IC waveguide device module includes: a substrate having a throughhole; a microwave IC provided on or above the first face of the substrate; a waveguide member provided below the second face of the substrate opposite from the first face, the waveguide member having an electrically conductive waveguide face which opposes the throughhole; an electrically conductive member covering at least a portion of the second face that extends in a manner of following along the waveguide face; and an artificial magnetic conductor on both sides of the waveguide member. The substrate includes an inner-wall electrically conductive portion covering an inner wall of the throughhole and being electrically connected with the electrically conductive member. The signal terminal and the ground terminal of the IC are electrically connected respectively with two portions of the inner-wall electrically conductive portion opposing each other with the throughhole interposed therebetween.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: May 12, 2020
    Assignees: NIDEC CORPORATION, WGR CO., LTD.
    Inventors: Hideki Kirino, Hiroyuki Kamo
  • Patent number: 10644003
    Abstract: A semiconductor memory device includes a substrate having an active region, word lines extending across the active region, a bit line on the active region between the word lines, a bit line node contact between the bit line and the active region, and a storage node contact on an end portion of the active region, wherein one or more of the bit line node contact or the storage node contact include silicon germanium.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: May 5, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min Hee Cho, Satoru Yamada, Junsoo Kim, Honglae Park, Wonsok Lee, Namho Jeon
  • Patent number: 10643910
    Abstract: A sacrificial interposer test structure including a release layer, a dummy layer on the release layer, one or more conductive pads embedded in the dummy layer, wherein each of the one or more conductive pads has an exposed surface, and a tie layer on the dummy layer and on each exposed surface of the one or more conductive pads.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: May 5, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hiroyuki Mori, Keishi Okamoto
  • Patent number: 10629550
    Abstract: A power integrated module, including at least one first bridge formed in a chip, wherein the first bridge includes: a first upper bridge switch, formed by a plurality of first sub switches formed in the chip connected in parallel, and including a first, a second and a control end; a first lower bridge switch, formed by a plurality of second sub switches formed in the chip connected in parallel, and including a first, a second and a control end; a first electrode, connected to the first end of the first upper bridge switch; a second electrode, connected to the second end of the first lower bridge switch; and a third electrode, connected to the second end of the first upper bridge switch and the first end of the first lower bridge switch, wherein the first, the second and the third electrode are bar-type electrodes arranged side by side.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: April 21, 2020
    Assignee: Delta Electronics (Shanghai) CO., LTD
    Inventors: Jianhong Zeng, Yan Chen, Le Liang, Xiaoni Xin
  • Patent number: 10629469
    Abstract: A coreless package substrate with dual side solder resist layers is disclosed. The coreless package substrate has a top side and a bottom side opposite of the top side and includes a single build-up structure formed of at least one insulating layer, at least one via, and at least one conductive layer. The coreless package substrate also includes a bottom plurality of contact pads on the bottom side, and a top plurality of contact pads on the top side. A bottom solder resist layer is on the bottom side, and a top solder resist layer is on the top side. The concept of dual side solder resist is extended to packages with interconnect bridge with C4 interconnection pitch over a wide range.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: April 21, 2020
    Assignee: Intel Corporation
    Inventors: Manohar S. Konchady, Tao Wu, Mihir K. Roy, Wei-Lun K. Jen, Yi Li
  • Patent number: 10629523
    Abstract: Certain aspects of the present disclosure provide an integrated circuit (IC) that includes at least one of a via-based vertical capacitor structure or a via-based vertical resistor structure. The IC includes a substrate oriented in a horizontal plane, electrically conductive layers disposed above the substrate, and electrically insulative layers disposed above the substrate and interposed between the plurality of electrically conductive layers. At least one of the vertical capacitor structure or the vertical resistor structure is disposed in the electrically conductive layers and the electrically insulative layers.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: April 21, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Chao Song, Ye Lu, Haitao Cheng
  • Patent number: 10629674
    Abstract: An integrated trench capacitor and method for making the trench capacitor is disclosed. The method includes forming a trench in a silicon layer, forming a first dielectric on the exposed surface of the trench, performing an anisotropic etch of the first dielectric to expose silicon at the bottom of the trench, implanting a dopant into exposed silicon at the bottom of the trench, forming a first polysilicon layer over the first dielectric, forming a second dielectric over the first polysilicon layer, and forming a second polysilicon layer over the second dielectric to fill the trench.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: April 21, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hideaki Kawahara, Binghua Hu, Sameer Pendharkar
  • Patent number: 10621387
    Abstract: A method includes calculating a maximum value of an on-die decoupling capacitor for an integrated circuit (IC) design based on a switching current defined by a number of simultaneously switching bits for the IC design. The method also includes calculating a total decoupling capacitance value offered by spacer cells in the IC design. The method further includes determining an optimal on-die decoupling capacitance value for the IC design as a function of the maximum value of the on-die decoupling capacitor and the total decoupling capacitance value offered by the spacer cells.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: April 14, 2020
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Nitin Kumar Chhabra, Rohit Halba, Shrikrishna Nana Mehetre
  • Patent number: 10622300
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a lower interconnect layer disposed within a first inter-level dielectric (ILD) layer over a substrate. A plurality of MIM (metal-insulator-metal) structures are disposed within a second inter-level dielectric (ILD) layer over the lower interconnect layer. An upper interconnect layer is coupled to the plurality of MIM structures at first locations that are directly over second locations at which the lower interconnect layer is coupled to the plurality of MIM structures. One or both of the lower interconnect layer and the upper interconnect layer are comprised within a conductive path that electrically couples the plurality of MIM structures in a series connection.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: April 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Chi Tu, Chin-Chieh Yang, Wen-Ting Chu
  • Patent number: 10615250
    Abstract: A tapered metal nitride structure having a gentle sloping (i.e., tapered) sidewall is provided that includes an oxygen rich metal nitride portion located between each metal nitride portion of a stack of metal nitride portions. The structure is formed by incorporating/introducing oxygen into an upper portion of a first metal nitride layer to form an oxygen rich metal nitride surface layer. A second nitride is then formed atop the oxygen rich metal nitride surface layer. The steps of oxygen incorporation/addition and nitride layer formation may be repeated any number of times. An etch mask is then provided and thereafter a sputter etch is performed to provide the tapered metal nitride structure. The tapered metal nitride structure may be used as an electrode in a semiconductor device.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Martin M. Frank, Hiroyuki Miyazoe, Vijay Narayanan
  • Patent number: 10615113
    Abstract: A capacitor includes a first set of conductive fingers having a first conductive pitch at a first interconnect layer and arranged in a first unidirectional routing. The capacitor further includes a second set of conductive fingers having a second conductive pitch at a second interconnect layer and arranged in a second unidirectional routing that is orthogonal to the first unidirectional routing. The first conductive pitch is different from the second conductive pitch. A first set of through finger vias electrically couples the first set of conductive fingers of the first interconnect layer to the second set of conductive fingers of the second interconnect layer. A third set of conductive fingers at a third conductive layer are parallel to, but offset from, the first set of conductive fingers. A second set of through finger vias electrically couples the third set of conductive fingers to the second set of conductive fingers.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: April 7, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Junjing Bao, Bin Yang, Gengming Tao
  • Patent number: 10600861
    Abstract: A method for fabricating a fingerprint sensor includes providing a base substrate including a plurality of pixel regions, forming a sensing dielectric structure on the base substrate in the plurality of pixel regions, and forming a sensing connection structure in the sensing dielectric structure. The sensing dielectric structure exposes the sensing connection structure, and the sensing connection structure is connected to the base substrate. The method also includes forming a plurality of electrode plates on surfaces of the sensing dielectric structure and the sensing connection structure, forming a plurality of protrusions on surfaces of the electrode plates by performing a bulging treatment process on the plurality of electrode plates, and forming an insulation medium structure on the plurality of electrode plates.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: March 24, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fu Gang Chen
  • Patent number: 10593614
    Abstract: In an embodiment, a semiconductor device includes: a lead-frame including one or more electrically conductive areas, one or more dielectric layers over the electrically conductive area or areas, one or more electrically conductive layer over the one or more dielectric layers thus forming one or more capacitors each including the dielectric layer sandwiched between an electrically conductive area and the electrically conductive layer. The semiconductor device also includes a semiconductor die on the lead-frame electrically connected to the one or more electrically conductive layers.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: March 17, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Fulvio Vittorio Fontana, Giovanni Graziosi
  • Patent number: 10586724
    Abstract: A method includes forming an adhesive layer over a carrier, forming a sacrificial layer over the adhesive layer, forming through-vias over the sacrificial layer, and placing a device die over the sacrificial layer. The Method further includes molding and planarizing the device die and the through-vias, de-bonding the carrier by removing the adhesive layer, and removing the sacrificial layer.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: March 10, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hsiang Hu, Chung-Shi Liu, Hung-Jui Kou, Ming-Da Cheng
  • Patent number: 10580745
    Abstract: RF semiconductor chips may be packaged on wafer level on the basis of a two-step process for providing a package material, thereby providing very short electrical connections between antenna structures formed in the package material and the semiconductor chip. In some illustrative embodiments, the antenna structures may be provided above the semiconductor chip, which results in a very space-efficient overall configuration.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: March 3, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Marcel Wieland, Christian Goetze
  • Patent number: 10580777
    Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: March 3, 2020
    Assignee: SK hynix Inc.
    Inventors: Jeong-Yeop Lee, Dong-Su Park, Jong-Bum Park, Sang-Do Lee, Jae-Min Lee, Kee-Jeung Lee, Jun-Soo Jang
  • Patent number: 10580579
    Abstract: A multilayer ceramic capacitor includes a body a first internal electrode and a second internal electrode disposed with a dielectric layer interposed therebetween, a first connecting electrode connected to the first internal electrode through the body, a second connecting electrode connected to the second internal electrode through the body, a first external electrode disposed on one surface of the body and connected to the first connecting electrode, and a second external electrode disposed on one surface of the body, spaced apart from the first external electrode, and connected to the second connecting electrode, wherein the first and second external electrodes each include a first electrode layer disposed on the body and including ceramics, and a second electrode layer disposed on the first electrode layer and having the content of ceramics smaller than that of the first electrode layer.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: March 3, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Seung Woo Song, Taek Jung Lee, Jin Kyung Joo, Hyo Youn Lee, Sung Kwon An
  • Patent number: 10580581
    Abstract: Methods for fabricating a structure that includes a metal-insulator-metal (MIM) capacitor and structures that include a MIM capacitor. The MIM capacitor includes a layer stack with a first electrode, a second electrode, and a third electrode. The layer stack includes a pilot opening extending at least partially through at least one of the first electrode, the second electrode, and the third electrode. A dielectric layer is arranged over the metal-insulator-metal capacitor, and includes a via opening extending vertically to the pilot opening. A via is arranged in the via opening and the pilot opening. The pilot opening has a cross-sectional area that is less than a cross-sectional area of the via opening.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: March 3, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Robert J. Fox, III, Lili Cheng, Roderick A. Augur
  • Patent number: 10559562
    Abstract: A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: February 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jin-Ping Han, Yulong Li, Dennis M. Newns, Paul M. Solomon, Xiao Sun
  • Patent number: 10553612
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: February 4, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Masayoshi Tagami, Jun Iijima, Ryota Katsumata, Kazuyuki Higashi
  • Patent number: 10553500
    Abstract: A plurality of semiconductor devices (5) are formed on a semiconductor wafer (1). A film thickness measurement wiring pattern (3,4) is formed on a dicing line (6,7) defining the plurality of semiconductor devices (5). An SOG film (10) is formed on the semiconductor devices (5) and the film thickness measurement wiring pattern (3,4). A film thickness of the SOG film (10) at a central part of the film thickness measurement wiring pattern (3,4) is measured. The film thickness measurement wiring pattern (3,4) is a rectangular pattern having long sides parallel to the dicing line (3,4).
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: February 4, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yuji Kawasaki
  • Patent number: 10553609
    Abstract: A semiconductor device includes a substrate, a first gate structure including first gate electrodes that are vertically stacked on the substrate, first channels penetrating the first gate structure to contact the substrate, a second gate structure including a channel connection layer on the first gate structure and second gate electrodes on the channel connection layer, second channels penetrating the second gate structure to contact the first channels, respectively, and separation regions penetrating the second gate structure and the first gate structure and extending in a first direction. The second gate electrodes are vertically stacked on the channel connection layer. The channel connection layer is between the separation regions and has at least one sidewall that is spaced apart from sidewalls of the separation regions.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: February 4, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woong Seop Lee, Byung Kwan You, Jae Woo Kwak
  • Patent number: 10545111
    Abstract: Moisture detection and ingression monitoring systems and methods of manufacture are provided. The moisture detection structure includes chip edge sealing structures including at least one electrode forming a capacitor structured to detect moisture ingress within an integrated circuit. The at least one electrode and a second electrode of the capacitor is biased to ground and to a moisture detection circuit or vice versa, respectively.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: January 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Fen Chen, Jeffrey P. Gambino, Carole D. Graas, Wen Liu, Prakash Periasamy