Including Capacitor Component Patents (Class 257/532)
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Patent number: 11978624Abstract: Embodiments of the present application provide a semiconductor structure and its formation method. The method includes: the substrate being provided with a groove, a sidewall of the groove including a first sub-sidewall and a second sub-sidewall that extend upwards from a bottom of the groove sub-sidewall; blowing a first precursor to a surface of the substrate, so that the first precursor is attached to a top surface of the substrate and the second sub-sidewall; blowing a second precursor to the surface of the substrate, so that the second precursor reacts with the first precursor to form a dielectric layer; alternately blowing the first precursor and the second precursor to the surface of the substrate to form a plurality of dielectric layers until a top opening of the groove is blocked, a region enclosed by the first sub-sidewall, the dielectric layer and the bottom of the groove forming a void.Type: GrantFiled: November 19, 2021Date of Patent: May 7, 2024Assignee: Changxin Memory Technologies, Inc.Inventor: Jiang Chu
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Patent number: 11978595Abstract: A capacitor component includes a body having first surface and second surfaces opposing each other and including through-holes penetrating through the first surface and the second surface, a first electrode covering an inner wall of each of the plurality of through-holes, a first common electrode covering the first surface and connected to the first electrode, a dielectric layer surrounded by the first electrode in the through-hole, a second electrode surrounded by the dielectric layer in the through-hole, a second common electrode layer covering the second surface and connected to the second electrode, a first external electrode disposed on at least one of a plurality of side surfaces of the body and connected to the first common electrode layer, and a second external electrode disposed on at least one of the plurality of side surfaces of the body and connected to the second common electrode layer.Type: GrantFiled: April 4, 2022Date of Patent: May 7, 2024Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Sang Jong Lee, Su Bong Jang, Min Cheol Park, Tae Ho Yun, Han Kim
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Patent number: 11980027Abstract: The present technology includes a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a first semiconductor layer, a cell stack and a peripheral stack each disposed on the first semiconductor layer, a first slit structure extending in a first direction and penetrating the cell stack and the peripheral stack, a penetration structure penetrating the peripheral stack and being spaced apart from the first slit structure, and a support structure penetrating the peripheral stack. The support structure includes first sidewall portions spaced apart from each other and a second sidewall portion connecting the first sidewall portions to each other, and the penetration structure is disposed between the first sidewall portions.Type: GrantFiled: August 4, 2022Date of Patent: May 7, 2024Assignee: SK hynix Inc.Inventor: Sang Bum Lee
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Patent number: 11977332Abstract: A substrate treating apparatus and a substrate treating method are provided. The substrate treating apparatus includes a first process chamber to apply an organic solvent to a substrate applied with a developer and introduced, and a second process chamber to treat the substrate applied with the organic solvent and introduced, through a supercritical fluid.Type: GrantFiled: September 11, 2020Date of Patent: May 7, 2024Assignees: SEMES CO., LTD., Research & Business Foundation SUNGKYUNKWAN UNIVERSITYInventors: Hae-Won Choi, Yerim Yeon, Anton Koriakin, Kihoon Choi, Youngran Ko, Jeong Ho Cho, Hyungseok Kang, Hong Gi Min
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Patent number: 11973166Abstract: A displaying base plate and a fabricating method thereof. The displaying base plate includes a substrate, and a first flat layer on one side of the substrate; a first metal layer on one side of the first flat layer that is further away from the substrate; a second flat layer on sides of the first metal layer and the first flat layer that are further away from the substrate; and a second metal layer on one side of the second flat layer that is further away from the substrate; wherein the first metal layer includes a first metal trace, an orthographic projection of the second metal layer on the substrate and an orthographic projection of the first metal trace on the substrate have an overlapping part, and an orthographic projection of the second flat layer on the substrate covers the orthographic projection of the first metal trace on the substrate.Type: GrantFiled: June 7, 2021Date of Patent: April 30, 2024Assignee: BOE Technology Group Co., Ltd.Inventors: Lubin Shi, Bin Qin, Liang Chen, Dongni Liu, Fangzhen Zhang, Ke Wang
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Patent number: 11973149Abstract: A semiconductor device includes: a first conductive plate and a second conductive plate disposed adjacent to the first conductive plate; a first insulating plate disposed over the first conductive plate and the second conductive plate; a third conductive plate disposed over the first insulating plate; a second insulating plate disposed over the third conductive plate; a fourth conductive plate disposed over the second insulating plate; a first conductive via penetrating the fourth conductive plate, the second insulating plate, the first insulating plate, and the first conductive plate, wherein the first conductive via is electrically coupled to the fourth conductive plate and the first conductive plate; and a second conductive via penetrating the second insulating plate, the third conductive plate, the first insulating plate, and the second conductive plate, wherein the second conductive via is electrically coupled to the third conductive plate and the second conductive plate.Type: GrantFiled: February 6, 2023Date of Patent: April 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yu-Hsing Chang, Chern-Yow Hsu, Shih-Chang Liu
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Patent number: 11961882Abstract: A semiconductor device includes a semiconductor substrate including a connection region, a pair of epitaxial patterns provided at the semiconductor substrate, a capacitor disposed between the pair of epitaxial patterns, a middle connection layer on the capacitor, an interconnection layer on the middle connection layer, and a through-via provided under the interconnection layer and penetrating the connection region of the semiconductor substrate. The capacitor includes an upper portion of the semiconductor substrate between the pair of epitaxial patterns, a metal electrode on the upper portion of the semiconductor substrate, and a dielectric pattern disposed between the upper portion of the semiconductor substrate and the metal electrode. The through-via is connected to the capacitor through the interconnection layer and the middle connection layer.Type: GrantFiled: September 13, 2021Date of Patent: April 16, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Shaofeng Ding, Jeong Hoon Ahn, Yun Ki Choi
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Patent number: 11963420Abstract: There is provided a display substrate and a display device. The display substrate includes a first metal layer, a first insulating layer, a metal oxide layer, a second insulating layer and a second metal layer which are stacked; wherein the metal oxide layer comprises a first pattern, a second pattern and a capacitance pattern, the first metal layer comprises a first electrode plate, there is at least a first overlapping region between the first electrode plate and the capacitance pattern to form a first storage capacitor, the second metal layer comprises a second electrode plate, there is at least a second overlapping region between the second electrode plate on the base substrate and the capacitance pattern to form a second storage capacitor, and the first electrode plate and the second electrode plate have same potential.Type: GrantFiled: July 15, 2020Date of Patent: April 16, 2024Assignees: Beijing BOE Technology Development Co., Ltd., BOE Technology Group Co., Ltd.Inventors: Chen Xu, Xueguang Hao, Yong Qiao, Xinyin Wu
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Patent number: 11955291Abstract: A composite capacitor that includes a first capacitor and a second capacitor. Each of plural first columnar conductors and each of plural second columnar conductors have a nano-size outer diameter. The composite capacitor includes a connecting conductor layer and a reinforcement conductor. The reinforcement conductor is located between a first counter electrode layer and a second counter electrode layer of the first capacitor and the second capacitor, respectively, and is connected to each of the first counter electrode layer, the second counter electrode layer, and the connecting conductor layer. The material forming the reinforcement conductor is the same as each of the first counter electrode layer and the second counter electrode layer and is different from the material forming the connecting conductor layer.Type: GrantFiled: April 18, 2022Date of Patent: April 9, 2024Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Masaki Nagata, Yasuhiro Shimizu
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Patent number: 11955509Abstract: A metal-insulator-metal capacitor includes a first electrode disposed in a first region of an upper surface of a substrate, a second electrode covering the first electrode and extending to a second region surrounding an outer periphery of the first region, a third electrode covering the second electrode and extending to a third region surrounding an outer periphery of the second region, a first dielectric layer disposed between the first electrode and the second electrode to cover an upper surface and a side surface of the first electrode and extending to the second region, and a second dielectric layer disposed between the second electrode and the third electrode to cover an upper surface and a side surface of the second electrode and extending to the third region and in contact with the first dielectric layer.Type: GrantFiled: December 22, 2021Date of Patent: April 9, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Jihyung Kim, Jeonghoon Ahn, Jaehee Oh, Shaofeng Ding, Wonji Park, Jegwan Hwang
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Patent number: 11956969Abstract: Provided is a semiconductor storage device that includes a substrate, a first storage element formed on the substrate and including a first insulating film, and a second storage element formed on the substrate and including a second insulating film having a film thickness of equal to or greater than 0.5 times and equal to or less than 2 times a film thickness of the first insulating film, the second storage element differing from the first storage element in power consumption at a time of writing.Type: GrantFiled: November 21, 2019Date of Patent: April 9, 2024Assignee: SONY GROUP CORPORATIONInventor: Toshiyuki Kobayashi
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Patent number: 11955510Abstract: A capacitor structure includes at least one first layer and at least one second layer that are alternately stacked. The at least one first layer includes first electrodes and second electrodes alternately arranged in a first direction, and the at least one second layer includes third electrodes and fourth electrodes alternately arranged in a second direction intersecting the first direction, the third electrodes and the fourth electrodes being electrically connected to the first electrodes and the second electrodes. Each of the first electrodes and the second electrodes includes a base portion and branch portions protruding from the base portion, and the third electrodes and the fourth electrodes are arranged side by side to correspond to the branch portions.Type: GrantFiled: February 14, 2022Date of Patent: April 9, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyeokki Hong, Cheheung Kim, Sungchan Kang, Yongseop Yoon, Choongho Rhee
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Patent number: 11955195Abstract: According to various embodiments, a semiconductor memory device includes a substrate that includes a memory cell region and a test region. The semiconductor memory device further includes an active pattern on the memory cell region, a source/drain pattern on the active pattern, a dummy pattern on the test region, a first gate electrode on the dummy pattern, a first common contact, and a first wiring layer. The first wiring layer includes a first test line electrically connected to the first common contact. The first common contact includes a first contact pattern in contact with the dummy pattern, and a first gate contact connected to the first gate electrode. The first gate contact includes a body and a protrusion part. A lowermost level of a top surface of the active pattern is lower than a lowermost level of a top surface of the dummy pattern.Type: GrantFiled: May 19, 2022Date of Patent: April 9, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seongkyung Kim, Dahye Min, Ukjin Jung
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Patent number: 11956942Abstract: According to one embodiment, a device includes: a circuit on a first surface of a substrate and including a first contact; an aluminum oxide layer above the substrate in a first direction perpendicular to the first surface; a cell including a capacitor provided in the aluminum oxide layer; a first conductive layer provided between the substrate and the aluminum oxide layer in the first direction and connected to the cell; a first insulating layer between the first conductive layer and the substrate in the first direction; a second insulating layer adjacent to the aluminum oxide layer in a second direction parallel to the first surface and provided above the substrate in the first direction; and a second contact in the second insulating layer and above the first contact in the first direction to connect the cell to the first contact.Type: GrantFiled: September 10, 2021Date of Patent: April 9, 2024Assignee: Kioxia CorporationInventors: Mutsumi Okajima, Yasuaki Ootera, Tsutomu Nakanishi
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Patent number: 11942278Abstract: Provided is a thin film capacitor comprising a capacitance portion in which at least one dielectric layer is sandwiched between a pair of electrode layers included in a plurality of electrode layers, wherein the capacitance portion has an opening which extends in a lamination direction in which the plurality of electrode layers and the dielectric layer are laminated and through which one electrode layer of the plurality of electrode layers is exposed, the one electrode layer has an exposed portion exposed at a bottom surface of the opening, the exposed portion is in contact with a wiring layer connecting the one electrode layer and an electrode terminal, and a thickness of the exposed portion of the one electrode layer is smaller than a thickness of other portions of the one electrode layer and is 50% or more of the thickness of the other portions of the one electrode layer.Type: GrantFiled: October 20, 2021Date of Patent: March 26, 2024Assignee: TDK CorporationInventors: Michihiro Kumagae, Kazuhiro Yoshikawa, Kenichi Yoshida, Junki Nakamoto, Norihiko Matsuzaka
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Patent number: 11942277Abstract: A method of manufacturing a semiconductor structure includes: forming a first oxide layer over a landing pad layer; forming a middle patterned dielectric layer over the first oxide layer; sequentially forming a second oxide layer and a top dielectric layer over the middle patterned dielectric layer; forming a trench through the top dielectric layer, the second oxide layer and the first oxide layer; conformally forming a bottom conductive layer in the trench; removing a portion of the top dielectric layer adjacent to the trench to expose a portion of the second oxide layer beneath the portion of the top dielectric layer; and performing an etching process to remove the second oxide layer and the first oxide layer. A semiconductor structure is also provided.Type: GrantFiled: April 13, 2021Date of Patent: March 26, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Mao-Ying Wang, Yu-Ting Lin
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Patent number: 11943914Abstract: A method of manufacturing a memory structure is provided. The method includes forming a first gate structure, a second gate structure, and a plurality of source/drain regions in a substrate, in which the plurality of source/drain regions are disposed on opposite sides of the first gate structure and the second gate structures; performing a dry etching process to form a trench between the first gate structure and the second gate structure; performing a wet etching process to expand the trench, in which the expanded trench has a hexagonal shaped cross section profile; and forming a bit line contact in the expanded trench.Type: GrantFiled: March 20, 2023Date of Patent: March 26, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Yu-Ying Lin
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Patent number: 11942414Abstract: Integrated circuits (ICs), including capacitors and inductors, employing directly coupled metal lines between vertically-adjacent interconnect layers for reduced coupling resistance, and related fabrication methods. By directly coupled, it is meant that there is not an intermediate vertical interconnect access (via) layer with a via(s) interconnecting the metal lines in vertically-adjacent interconnect layers. An overlying and underlying metal line in respective and vertically-adjacent overlying and underlying interconnect layers are directly coupled to each other without the need for an intermediate via layer. For example, directly coupled metal in adjacent interconnect layers of IC can reduce contact resistance between the metal lines and reduce the overall height of the IC.Type: GrantFiled: September 17, 2021Date of Patent: March 26, 2024Assignee: QUALCOMM IncorporatedInventors: John Jianhong Zhu, Junjing Bao, Giridhar Nallapati
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Patent number: 11935760Abstract: A package structure includes a first thermal dissipation structure, a first semiconductor die, a second semiconductor die. The first thermal dissipation structure includes a semiconductor substrate, conductive vias embedded in the semiconductor substrate, first capacitors electrically connected to the conductive vias, and a thermal transmission structure disposed over the semiconductor substrate and the conductive vias. The first semiconductor die is disposed on the first thermal dissipation structure. The second semiconductor die is disposed on the first semiconductor die opposite to the first thermal dissipation structure.Type: GrantFiled: August 30, 2021Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Yian-Liang Kuo, Kuo-Chung Yee
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Patent number: 11929400Abstract: A method of manufacturing a silicon carbide semiconductor device, including forming a first-conductivity-type region in a SiC semiconductor substrate, selectively forming a plurality of second-conductivity-type regions in the first-conductivity-type region, forming an interlayer insulating film covering the first-conductivity-type region and the second-conductivity-type regions, selectively removing the interlayer insulating film to form a plurality of openings exposing the second-conductivity-type regions, forming, in each opening, a layered metal film having a cap film stacked on an aluminum film, thermally diffusing aluminum atoms in the aluminum film to thereby form a plurality of second-conductivity-type high-concentration regions, removing the layered metal film, selectively removing the interlayer insulating film to form a contact hole, forming a first electrode by sequentially stacking a titanium film and a metal film containing aluminum on the first surface of the semiconductor substrate in the contaType: GrantFiled: June 28, 2021Date of Patent: March 12, 2024Assignee: FUJI ELECTRIC CO., LTD.Inventors: Naoyuki Ohse, Takahito Kojima
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Patent number: 11929679Abstract: An apparatus includes a controller a current mode controller that produces an output voltage by supplying output current from at least one power supply phase of a power supply to power a load. The controller produces an error current signal based on a difference between a magnitude of the output current supplied from the power supply to a load and a phase current setpoint. Based on a magnitude of the error current signal, control a pulse width setting of a pulse width modulation signal controlling the at least one power supply phase. The controller varies a leading edge and a falling edge of a pulse width ON-time of the pulse width modulation signal over each of multiple control cycles depending on variations in the magnitude of the pulse width setting.Type: GrantFiled: June 30, 2021Date of Patent: March 12, 2024Assignee: Infineon Technologies Austria AGInventors: Venkat Sreenivas, Bikiran Goswami, Benjamim Tang, Todd Bellefeuille, Kang Peng
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Patent number: 11922997Abstract: A non-volatile memory device includes a first semiconductor layer and a second semiconductor layer arranged in the vertical direction. A first semiconductor layer includes a plurality of memory cells, and a plurality of metal lines extending in a first direction, and including first bit lines, second bit lines, and a common source line tapping wire between the first bit lines and the second bit lines. A second semiconductor layer includes a page buffer circuit connected to the first bit lines and the second bit lines, and the page buffer circuit includes first transistors arranged below the first bit lines and electrically connected to the first bit lines, second transistors arranged below the second bit lines and electrically connected to the second bit lines, and a first guard ring arranged below and overlapped the common source line tapping wire in the vertical direction and extending in the first direction.Type: GrantFiled: January 13, 2022Date of Patent: March 5, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Changbum Kim, Sunghoon Kim
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Patent number: 11923273Abstract: A method of manufacturing a semiconductor device, including: forming a plurality of first metal strips extending in a first direction on a first plane; and forming a plurality of second metal strips extending in the first direction on a second plane over the first plane by executing a photolithography operation with a single mask, wherein a first second metal strip (FIG. 1, 131) is disposed over a first first metal strip; wherein the first first metal strip and the first second metal strip are directed to a first voltage source; wherein a distance between the first second metal strip and a second second metal strip immediate adjacent to the first second metal strip is greater than a distance between the second second metal strip and a third second metal strip immediate adjacent to the second second metal strip.Type: GrantFiled: July 29, 2022Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Shih-Wei Peng, Chia-Tien Wu, Jiann-Tyng Tzeng
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Patent number: 11923150Abstract: Disclosed herein are IC structures with one or more decoupling capacitors based on dummy TSVs provided in a support structure. An example decoupling capacitor includes first and second capacitor electrodes and a capacitor insulator between them. The first capacitor electrode is a liner of a first electrically conductive material on sidewalls and a bottom of an opening in the support structure, the opening in the support structure extending from the first side towards, but not reaching, the second side. The capacitor insulator is a liner of a dielectric material on sidewalls and a bottom of the opening in the support structure lined with the first electrically conductive material. The second capacitor electrode is a second electrically conductive material filling at least a portion of the opening in the support structure lined with the first electrically conductive material and with the dielectric material.Type: GrantFiled: May 27, 2020Date of Patent: March 5, 2024Assignee: Intel CorporationInventor: Changyok Park
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Patent number: 11923827Abstract: Disclosed is a Bulk Acoustic Wave (BAW) assist filter structure with a BAW resonator stacked onto an integrated passive device (IPD). In exemplary aspects disclosed herein, the BAW filter structure includes a transducer with electrodes and a piezoelectric layer between the electrodes. The IPD is electrically coupled to the BAW resonator and provides a high frequency of operation. In such a configuration, the BAW assist filter structure has a low insertion loss and mitigates electrical length parasitic loss due to the close electrically proximity of the BAW resonator stacked onto the IPD. Further, the BAW assist filter structure is able to filter high frequencies and provides improved filter performance and greater flexibility in design of a filter transfer function.Type: GrantFiled: February 23, 2021Date of Patent: March 5, 2024Assignee: Qorvo US, Inc.Inventors: Jeffery D. Galipeau, Kelly M. Lear
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Patent number: 11925119Abstract: A system on an integrated circuit (IC) chip includes an input terminal and a return terminal, a heater, a thermopile, and a switch device. The heater is coupled between the input terminal and the return terminal. The thermopile is spaced apart from the heater by a galvanic isolation region. The switch device includes a control input coupled to an output of the thermopile. The switch device is coupled to at least one output terminal of the IC chip.Type: GrantFiled: December 14, 2021Date of Patent: March 5, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Barry Jon Male, Henry Litzmann Edwards
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Patent number: 11923288Abstract: To provide a wiring substrate, an electronic device, and an electronic module the size of which can be easily reduced and the strength of which can be maintained. A wiring substrate includes an insulation substrate and an electrical wiring structure. The insulation substrate includes a recess section in one surface. A frame portion of the insulation substrate that forms a side surface which connects an opened surface and a bottom surface of the recess section to each other includes a first conductive portion having a plate shape in the frame portion.Type: GrantFiled: October 31, 2022Date of Patent: March 5, 2024Assignee: KYOCERA CorporationInventors: Takuo Kisaki, Takahiro Sasaki
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Patent number: 11917834Abstract: Some embodiments include an integrated assembly having a first bottom electrode adjacent to a second bottom electrode. An intervening region is directly between the first and second bottom electrodes. Capacitor-insulative-material is adjacent to the first and second bottom electrodes. The capacitor-insulative-material is substantially not within the intervening region. Top-electrode-material is adjacent to the capacitor-insulative-material. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: July 20, 2021Date of Patent: February 27, 2024Assignee: Micron Technology, Inc.Inventors: Durai Vishak Nirmal Ramaswamy, Marcello Mariani, Giorgio Servalli
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Patent number: 11917804Abstract: A manufacturing method of a SRAM memory device includes forming two transistors on a substrate, forming an inner dielectric layer covering the two transistors, forming contacts in the inner dielectric layer for coupling to source nodes of the two transistors, forming a metal interconnect structure on the inner dielectric layer, wherein a portion of an n-th metal layer of the metal interconnect structure is utilized as a lower metal layer, wherein n?1. An opening is formed in the metal interconnect structure to expose the lower metal layer, and then a capacitor is formed in the opening. The capacitor includes the lower metal layer, a first electrode layer, a dielectric layer, a second electrode layer, and an upper metal layer from bottom to top. The upper metal layer is a portion of an m-th metal layer of the metal interconnect structure, wherein m?n+1.Type: GrantFiled: September 15, 2022Date of Patent: February 27, 2024Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Shou-Zen Chang, Yi-Hsung Wei, Pei-Hsiu Tseng, Jia-You Lin
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Patent number: 11910593Abstract: A semiconductor device may comprise: a plurality of lower electrodes which are on a substrate; a first electrode support which is between adjacent lower electrodes and comprises a metallic material; a dielectric layer which is on the lower electrodes and the first electrode support to extend along profiles of the first electrode support and each of the lower electrodes; and an upper electrode which is on the dielectric layer.Type: GrantFiled: September 25, 2020Date of Patent: February 20, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Yoon Young Choi, Seung Jin Kim, Byung-Hyun Lee, Sang Jae Park
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Patent number: 11910725Abstract: The present disclosure relates to magnetic devices. In particular, the disclosure relates to magnetic memory and logic devices that employ the voltage control of magnetic anisotropy (VCMA) effect for magnetization switching. The present disclosure provides a method for manufacturing a magnetic structure for such a magnetic device. The method comprising the following steps: providing a bottom electrode layer, forming a SrTiO3 (STO) stack on the bottom electrode layer by atomic layer deposition (ALD) of at least two different STO nanolaminates, forming a magnetic layer on the STO stack, and forming a perpendicular magnetic anisotropy (PMA) promoting layer on the magnetic layer, the PMA promoting layer being configured to promote PMA in the magnetic layer.Type: GrantFiled: December 14, 2020Date of Patent: February 20, 2024Assignees: IMEC VZW, Katholieke Universiteit LeuvenInventors: Bart Vermeulen, Mihaela Ioana Popovici, Koen Martens, Gouri Sankar Kar
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Patent number: 11908888Abstract: A metal-insulator-metal (MIM) capacitor structure includes a substrate extending along a first direction to define a length, a second direction orthogonal to the first direction to define a width, and a third direction orthogonal to the first and second direction to define a height. The substrate includes a first capacitance region and a second capacitance region. The first capacitance region has a first maximum operating voltage (Vmax) and the second capacitance region has a second Vmax that is greater than the first Vmax.Type: GrantFiled: September 23, 2021Date of Patent: February 20, 2024Assignee: International Business Machines CorporationInventors: Baozhen Li, Chih-Chao Yang, Nan Jing, Huimei Zhou
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Patent number: 11908812Abstract: A memory device including a substrate including a substrate contact pad. The memory device includes a first memory die including a first power supply contact pad electrically coupled to the substrate contact pad and a first power supply circuit on the first memory die. The first memory die further includes a first electrostatic discharge (ESD) power clamp contact pad electrically coupled to the substrate contact pad and a first ESD power clamp circuit on the first memory die. The memory device further includes a second memory die including a second power supply contact pad electrically coupled to the substrate contact pad and a second power supply circuit on the second memory die and a second ESD power clamp contact pad electrically coupled to a second ESD power clamp circuit on the second memory die, wherein the second ESD power clamp contact pad is electrically disconnected from the substrate contact.Type: GrantFiled: February 16, 2021Date of Patent: February 20, 2024Assignee: Micron Technology, Inc.Inventors: Yui Shimizu, James E. Davis
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Patent number: 11901315Abstract: An embodiment of the disclosure provides a package device including a redistribution layer, an integrated passive device layer, a first port, and a second port. The integrated passive device layer contacts the redistribution layer. The integrated passive device layer has at least one capacitor. The at least one capacitor includes a first capacitor and a second capacitor. The first port is electrically connected to the first capacitor and the second capacitor. The second port is provided opposite to the first port. The second port is electrically connected to the first capacitor and the second capacitor. The first port and the second port have the same resistance.Type: GrantFiled: October 7, 2021Date of Patent: February 13, 2024Assignee: Innolux CorporationInventors: Yeong-E Chen, Wei-Hsuan Chen, Chun-Yuan Huang
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Patent number: 11901283Abstract: An integrated circuit (IC) structure includes a semiconductor substrate, a bottom electrode routing, a capacitor structure, a top electrode routing. The bottom electrode routing is over the semiconductor substrate. The capacitor structure is over the bottom electrode routing. The capacitor structure includes a bottom metal layer, a middle metal layer above the bottom metal layer, and a top metal layer above the middle metal layer. When viewed in a plan view, the top metal layer has opposite straight edges extending along a first direction and opposite square wave-shaped edges connecting the opposite straight edges, the square wave-shaped edges each comprise alternating first and second segments extending along a second direction perpendicular to the first direction, and third segments each connecting adjacent two of the first and second segments, wherein the third segments extend along the first direction.Type: GrantFiled: July 9, 2021Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wan-Te Chen, Chung-Hui Chen, Wei Chih Chen
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Patent number: 11901403Abstract: A method for fabricating a semiconductor device includes: forming a mold structure including a mold layer and a supporter layer over a semiconductor substrate; forming an opening penetrating the mold structure; forming a protective layer on a bottom surface and a sidewall of the opening; forming a lower electrode over the protective layer; selectively etching the supporter layer to form a supporter that supports the lower electrode; removing the mold layer to define a non-exposed portion and an exposed portion of an outer wall of the protective layer; and selectively trimming the exposed portion of the protective layer to form a protective layer pattern between the supporter and the lower electrode.Type: GrantFiled: August 30, 2022Date of Patent: February 13, 2024Assignee: SK hynix Inc.Inventors: Jun Hyuk Seo, Myoung Sik Chang
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Patent number: 11901004Abstract: A memory array, a memory structure and an operation method of a memory array are provided. The memory array includes memory cells, floating gate transistors, bit lines and word lines. The memory cells each comprise a capacitor and an electrically programmable non-volatile memory (NVM) serially connected to the capacitor, and further comprise a write transistor with a first source/drain terminal coupled to a common node of the capacitor and the electrically programmable NVM. The floating gate transistors respectively have a gate terminal electrically floated and coupled to the capacitors of a column of the memory cells. The bit lines respectively coupled to the electrically programmable NVMs of a row of the memory cells. The word lines respectively coupled to gate terminals of the write transistors in a row of the memory cells.Type: GrantFiled: April 8, 2022Date of Patent: February 13, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kerem Akarvardar, Win-San Khwa, Rawan Naous, Jin Cai, Meng-Fan Chang, Hon-Sum Philip Wong
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Patent number: 11895823Abstract: A semiconductor device and a manufacturing method are provided. The semiconductor device includes an active region, a bit line, a capacitor contact, a conductive ring and a storage capacitor. The active region is formed in a substrate. The bit line and the capacitor contact are disposed over the substrate and electrically connected with the active region. The bit line is laterally separated from the capacitor contact, and a top surface of the bit line is lower than a top surface of the capacitor contact. An upper portion of the capacitor contact is surrounded by the conductive ring. The storage capacitor is disposed over and in electrical contact with the capacitor contact and the conductive ring.Type: GrantFiled: November 15, 2021Date of Patent: February 6, 2024Assignee: Winbond Electronics Corp.Inventor: Noriaki Ikeda
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Patent number: 11894337Abstract: A power semiconductor element and a support member are stacked with an intermediate structure being interposed between the power semiconductor element and the support member. The intermediate structure includes a first metal paste layer and at least one first penetrating member. The first metal paste layer contains a plurality of first metal particles. The at least one first penetrating member penetrates the first metal paste layer. At least one first vibrator attached to the at least one first penetrating member penetrating the first metal paste layer is vibrated. The first metal paste layer is heated so that the plurality of first metal particles are sintered or fused.Type: GrantFiled: June 25, 2021Date of Patent: February 6, 2024Assignee: Mitsubishi Electric CorporationInventor: Keisuke Kawamoto
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Patent number: 11894418Abstract: A semiconductor structure, a preparation method of the same, and a semiconductor device are provided. The semiconductor structure includes a substrate, including an active area. A first electrode layer is arranged on the substrate and electrically connected to the active area. The first electrode layer extends in a direction perpendicular to the substrate. A dielectric layer is arranged on a surface of the first electrode layer. A second electrode layer is arranged on a surface of the dielectric layer. Each of the surface of the first electrode layer and the surface of the dielectric layer are provided with an uneven structure.Type: GrantFiled: August 31, 2021Date of Patent: February 6, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Xianlei Cao
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Patent number: 11894190Abstract: In an embodiment, a component includes a first electrode and a second electrode arranged one above the other in a stacking direction, wherein the first electrode and the second electrode overlap in a first overlap region, wherein the first electrode has, in a first region containing the first overlap region, an extent in a first direction perpendicular to the stacking direction that is greater than an extent of the second electrode in the first direction in the first region, and wherein the first electrode has, in the first region containing the first overlap region, an extent in a second direction perpendicular to the stacking direction and to the first direction that is greater than an extent of the second electrode in the second direction in the first region, and a third electrode arranged in the same plane as the second electrode, wherein the first electrode is a floating electrode, wherein the first electrode and the third electrode overlap in a second overlap region, wherein the first electrode has, inType: GrantFiled: February 14, 2020Date of Patent: February 6, 2024Assignee: TDK Electronics AGInventors: Alfred Hofrichter, S. Soran Nabavi
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Patent number: 11894359Abstract: The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively physically larger base die using an electrical mesh network that is formed in whole or in part in, on, across, or about all or a portion of the base die. Electrical mesh networks beneficially permit the positioning of the cores in close proximity to support circuitry carried by the base die. The minimal separation between the core circuitry and the support circuitry advantageously improves communication bandwidth while reducing power consumption. Each of the cores may include functionally dedicated circuitry such as processor core circuitry, field programmable logic, memory, or graphics processing circuitry. The use of core dies beneficially and advantageously permits the use of a wide variety of cores, each having a common or similar interface to the electrical mesh network.Type: GrantFiled: January 12, 2022Date of Patent: February 6, 2024Assignee: Intel CorporationInventors: Wilfred Gomes, Mark T. Bohr, Rajesh Kumar, Robert L. Sankman, Ravindranath V. Mahajan, Wesley D. McCullough
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Patent number: 11889677Abstract: A method for forming capacitor holes is provided. By forming a first material layer and a second material layer which are thinner and are different in materials on a supporting layer as an over-etching depth adjusting layer, when etching holes are formed in a hard mask layer and the hard mask layer is over-etched, a certain over-etching depth may be formed in the second material layer, and the etching holes terminate in the first material layer, so that the etching depth of the etching holes can be corrected and adjusted. Accordingly, the etching holes formed after the hard mask layer is over-etched can have the same depth or have a small depth difference. Therefore, time points at which the plurality of capacitors holes formed expose the corresponding connecting pads are substantially the same or differ very little, improving the performance of the DRAM.Type: GrantFiled: November 18, 2021Date of Patent: January 30, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Xifei Bao, Jinguo Fang
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Patent number: 11887934Abstract: The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor package. In one embodiment, a glass or silicon substrate is structured by micro-blasting or laser ablation to form structures for formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor package with embedded dies therein.Type: GrantFiled: December 5, 2022Date of Patent: January 30, 2024Assignee: Applied Materials, Inc.Inventors: Han-Wen Chen, Steven Verhaverbeke, Giback Park, Giorgio Cellere, Diego Tonini, Vincent DiCaprio, Kyuil Cho
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Patent number: 11881462Abstract: A semiconductor device includes an impedance having a first port and a second port located over a semiconductor substrate. The impedance includes at least one metal-insulator-metal (MIM) lateral flux capacitor (LFC) pair. Each LFC pair includes a first LFC connected in series with a second LFC. A terminal of the first LFC is connected to the first port, and a terminal of the second LFC is connected to the second port. Optionally the device further includes circuitry formed over the semiconductor substrate, wherein the circuitry is configured to implement a circuit function in cooperation with the impedance.Type: GrantFiled: September 28, 2020Date of Patent: January 23, 2024Assignee: Texas Instruments IncorporatedInventor: Honglin Guo
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Patent number: 11882686Abstract: A method for forming a capacitor includes: providing a substrate with an electric contact portion; forming a supporting layer and a sacrificial layer which are alternately laminated on a surface of the substrate, wherein the topmost layer is a supporting layer; forming a capacitor hole penetrating through the supporting layer and the sacrificial layer and exposing the electric contact portion; forming a bottom electrode layer covering an inner surface of the capacitor hole; forming a protective layer covering a surface of the bottom electrode layer; removing the sacrificial layer, during which the bottom electrode layer being protected by the protective layer; removing the protective layer; and sequentially forming a capacitor dielectric layer and a top electrode layer.Type: GrantFiled: July 13, 2021Date of Patent: January 23, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Wenfeng Wang, Shuangshuang Wu
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Patent number: 11882692Abstract: A method includes forming an inter-layer insulation layer on a substrate, forming a plug material penetrating the inter-layer insulation layer and contacting a portion of the substrate, forming a contact plug by etching the plug material, forming a trench exposing a side wall of the contact plug by etching the substrate and the inter-layer insulation layer to be aligned with a side wall of the contact plug, forming a gate insulation layer on a surface of the trench and the exposed side wall of the contact plug, and forming a gate electrode partially filling the trench on the gate insulation layer.Type: GrantFiled: July 8, 2022Date of Patent: January 23, 2024Assignee: SK hynix Inc.Inventor: Jae Houb Chun
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Patent number: 11881450Abstract: A system and method for fabricating on-die metal-insulator-metal capacitors capable of supporting relatively high voltage applications and increasing capacitance per area are described. In various implementations, an integrated circuit includes multiple metal-insulator-metal (MIM) capacitors. The MIM capacitors are formed between two signal nets such as two different power rails, two different control signals, or two different data signals. The integrated circuit includes multiple intermediate metal layers (or metal plates) formed between two signal nets. In high voltage regions, a MIM capacitor has one or more intermediate metal plates formed as floating plates between electrode metal plates. The floating plates have no connection to any power supply reference voltage level used by the integrated circuit.Type: GrantFiled: October 25, 2021Date of Patent: January 23, 2024Assignee: Advanced Micro Devices, Inc.Inventor: Regina Tien Schmidt
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Patent number: 11877436Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a substrate and a conductive pad disposed on the substrate and having a first surface facing away from the substrate. The first surface of the conductive pad is recessed toward the substrate and defines a recessed portion. The semiconductor device also includes a capacitor structure at least partially-disposed within the recessed portion of the conductive pad and electrically connected with the substrate through the conductive pad.Type: GrantFiled: September 27, 2021Date of Patent: January 16, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Tsu-Chieh Ai
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Patent number: 11869723Abstract: A multilayer capacitor includes: a capacitor body including first and second internal electrodes alternately stacked with a dielectric layer interposed therebetween, and having first to six surfaces, the first internal electrode being exposed through the third, fifth, and sixth surfaces, the second internal electrode being exposed through the fourth, fifth, and sixth surfaces; first and second side portions disposed on the fifth and sixth surfaces of the capacitor body; and first and second external electrodes. The capacitor body includes upper and lower cover portions disposed on an upper surface of an uppermost internal electrode and a lower surfaces of a lowermost internal electrode, respectively, in a stacking direction of the first and second internal electrodes. The first and second side portions and the upper and lower cover portions include zirconium (Zr).Type: GrantFiled: July 19, 2022Date of Patent: January 9, 2024Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Yong Park, Sim Chung Kang, Jong Ho Lee, Hyung Soon Kwon, Woo Chul Shin