Abstract: This application discloses a flexible sensing system and an associated proximity sensing method. The flexible sensing system includes: a first thin film encapsulation layer and a first electrode layer attached to the first thin film encapsulation layer; the first electrode layer includes a bipolar electrode configured for forming an arc-shaped electric field for determining whether a distance between a target object and the sensing system is within the first distance range; the first electrode layer further includes a unipolar electrode configured for forming a vertical electric field for determining whether a distance between the target object and the sensing system is within the second distance range; and the first distance range is less than the second distance range. By using different sensing solutions for the object at different distance positions, the sensing system avoids the issue that a single sensing solution has a relatively low sensing accuracy.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

Abstract: A semiconductor device may include a cell capacitor including first lower electrodes, a first upper support layer pattern, a first dielectric layer, and a first upper electrode. The decoupling capacitor may include second lower electrodes, a second upper support layer pattern, a second dielectric layer, and a second upper electrode. The first and second lower electrodes may be arranged in a honeycomb pattern at each vertex of a hexagon and a center of the hexagon. The first upper support layer pattern may be connected to upper sidewalls of the first lower electrodes. The first upper support layer pattern may correspond to a first plate defining first openings. The second upper support layer pattern may be connected to upper sidewalls of the second electrodes. The second upper support layer pattern may correspond to a second plate defining second openings having a shape different from a shape of the first opening.

Abstract: Semiconductor device may include a landing pad and a lower electrode that is on and is connected to the landing pad and includes an outer portion and an inner portion inside the outer portion. The outer portion includes first and second regions. The semiconductor devices may also include a dielectric film on the first region of the outer portion on the lower electrode and an upper electrode on the dielectric film. The first region of the outer portion of the lower electrode may include a silicon (Si) dopant, the dielectric film does not extend along the second region of the outer portion. A concentration of the silicon dopant in the first region of the outer portion is different from a concentration of the silicon dopant in the second region of the outer portion and is higher than a concentration of the silicon dopant in the inner portion.

Abstract: An integrated circuit structure includes a first capacitor structure, disposed in a first layer on a semiconductor substrate and comprising a plurality of capacitors; a second capacitor structure, adjacent to first capacitor structure in the first layer, wherein the second capacitor structure and the first capacitor structure are arranged as a strip-shaped structure; a first conductive plate, disposed at one end of the strip-shaped structure in the first layer; and a second conductive plate, disposed in a second layer on the semiconductor substrate over the strip-shaped structure and extending toward the other end of the strip-shaped structure from the one end of the strip-shaped structure.

Abstract: A method for manufacturing a memory and a memory is provided. The method for manufacturing a memory includes: providing a substrate; stacking an electrode support structure, a protective layer and a first mask layer in sequence on the substrate; patterning the first mask layer on an array region, and etching the protective layer, the electrode support structure and the substrate by using the patterned first mask layer as a mask, to form capacitor holes penetrating the protective layer and the electrode support structure and extending into the substrate; removing the first mask layer; and forming a first electrode layer on side walls and bottom walls of the capacitor holes, a top surface of the first electrode layer being flush with a top surface of the electrode support structure.

Abstract: A semiconductor device includes a bottom electrode, a top electrode, a sidewall spacer, and a data storage element. The sidewall spacer is disposed aside the top electrode. The data storage element is located between the bottom electrode and the top electrode, and includes a ferroelectric material. The data storage element has a peripheral region which is disposed beneath the sidewall spacer and which has at least 60% of ferroelectric phase. A method for manufacturing the semiconductor device and a method for transforming a non-ferroelectric phase of a ferroelectric material to a ferroelectric phase are also disclosed.

Abstract: A chip capacitor includes a substrate, a plurality of capacitor wires on the substrate, and a mold layer disposed on the substrate to cover the capacitor wires. Each of the capacitor wires includes a core electrode line having a wire shape, an outer electrode line covering at least a portion of the core electrode line, and a dielectric line interposed between the core electrode line and the outer electrode line.

Abstract: A method for fabricating a semiconductor device includes: forming a mold stack layer including a mold layer and a supporter layer over a substrate; forming opening by etching the mold stack layer; selectively forming a supporter reinforcement layer on an exposed surface of the supporter layer which is positioned in the opening; forming a bottom electrode in the opening in which the supporter reinforcement layer is formed; and forming a supporter opening by etching a portion of the supporter layer to form a supporter that supports an outer wall of the bottom electrode.

Abstract: A thin film structure including a dielectric material layer, a method of manufacturing the same, and an electronic device employing the same are disclosed. The disclosed thin film structure includes a first conductive layer; a first dielectric material layer on the first conductive layer, the first dielectric material layer having a crystal phase and including a metal oxide; an InxOy-based seed material layer formed on the first dielectric material layer and having a thickness less than a thickness of the first dielectric material layer; and a second conductive layer formed on the seed material layer.

Abstract: A multilayer ceramic capacitor includes internal electrode layers and dielectric layers laminated alternately, and external electrodes on end surfaces. The internal electrode layers extend in a length direction and a width direction. The dielectric layers include about 100 moles or more and about 101 moles or less of Ca with respect to 100 moles of Zr. One side in the length direction of the internal electrode layers is connected to one of the external electrodes. Another side of the internal electrode layers is not connected to the external electrodes. A length at a middle portion in the width direction of the internal electrode layers is defined as L1, and a length at an end portion in the width direction is defined as L2, the internal electrode layers include a curved end side extending in the width direction so that L2<L1 is satisfied.

Abstract: A first etching method of an oxide semiconductor film according to an embodiment of the present disclosure includes: forming a reduction layer in an oxide semiconductor film with use of a reducing gas; and sputtering the reduction layer with use of a rare gas.

Abstract: A semiconductor structure and a manufacturing method thereof are present. The method includes: forming a first mask layer having an etching window, wherein the first mask layer includes a first mask sublayer formed on the upper surface of bit line structures, and a second mask sublayer located on the upper surface of the first mask sublayer and the upper surface of an inter-layer dielectric layer, the first mask sublayer has the upper surface level with the upper surface of an inter-layer dielectric layer, and has a plurality of strip-shaped patterns extending in a first direction and spaced apart from each other, and the second mask sublayer has a plurality of strip-shaped patterns extending in a second direction and spaced apart from each other; and etching the inter-layer dielectric layer by using the first mask layer as a mask to form a contact hole exposing a surface of a substrate.

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layer; a second metal layer overlaying the first metal layer; and a second level including a second single crystal layer, the second level including second transistors and at least one third metal layer, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the second level includes a plurality of DRAM memory cells, where each of the plurality of DRAM memory cells includes at least one of the second transistors and one capacitor, where the second level is directly bonded to the first level, and where the bonded includes metal to metal bonds.

Abstract: Methods, systems, and devices for thin film transistor deck selection in a memory device are described. A memory device may include memory arrays arranged in a stack of decks formed over a substrate, and deck selection components distributed among the layers to leverage common substrate-based circuitry. For example, each memory array of the stack may include a set of digit lines of a corresponding deck, and deck selection circuitry operable to couple the set of digit lines with a column decoder that is shared among multiple decks. To access memory cells of a selected memory array on one deck, the deck selection circuitry corresponding to the memory array may each be activated, while the deck selection circuitry corresponding to a non-selected memory array on another deck may be deactivated. The deck selection circuitry, such as transistors, may leverage thin-film manufacturing techniques, such as various techniques for forming vertical transistors.

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.

Abstract: A plurality of first semiconductor layers and second semiconductor layers are formed over a front side of a substrate. The first semiconductor layers interleave with the second semiconductor layers in a vertical direction. The first semiconductor layers and second semiconductor layers are etched into a plurality of stacks. The etching is performed such that a bottommost first semiconductor layer is etched to have a tapered profile in a cross-sectional view. The bottommost first semiconductor layer is replaced with a dielectric layer. The dielectric layer inherits the tapered profile of the bottommost first semiconductor layer. Gate structures are formed over the stacks. The gate structures each extend in a first horizontal direction. A first interconnect structure is formed over the gate structures. A second interconnect structure is formed over a back side of the substrate.

Abstract: An electronic substrate may be fabricated by forming a base substrate and forming an inductor extending through the base substrate, wherein the inductor includes a magnetic material layer and a barrier layer, such that the barrier layer prevents the magnetic material layer from leaching into plating solutions during the fabrication of the electronic substrate. In one embodiment, the barrier material may comprise titanium. In another embodiment, the barrier layer may comprise a polymeric material. In still another embodiment, the barrier layer may comprise a nitride material layer. The inductor may further include a plating seed layer on the barrier layer and a conductive fill material abutting the plating seed layer.

Abstract: Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity ?-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity ?-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity ?-W phase. The ?-W converts to a low-resistivity ?-phase of tungsten in the regions not pre-treated with impurities.

Abstract: A method for forming a chip structure is provided. The method includes providing a semiconductor substrate, a first conductive line, and a first dielectric layer. The method includes forming a first conductive layer over the first dielectric layer. The method includes forming a second conductive layer over the first conductive layer. The method includes forming a second dielectric layer over the second conductive layer and the first conductive layer. The method includes forming a first through hole passing through the second dielectric layer, the first conductive layer, and the first dielectric layer. The method includes forming a first conductive structure in and over the first through hole.

Abstract: A semiconductor substrate includes excavations which form trenches sunk. A capacitive element includes: a first dielectric envelope conforming to sides and bottoms of the trenches; a first semiconductor layer conforming to a surface of the first dielectric envelope in the trenches; a second dielectric envelope conforming to a surface of the first semiconductor layer in the trenches; and a second semiconductor layer conforming to a surface of the second dielectric envelope in the trenches.

Abstract: Embedded three-dimensional electrode capacitors, and methods of fabricating three-dimensional electrode capacitors, are described. In an example, an integrated circuit structure includes a first metallization layer above a substrate, the first metallization layer having a first conductive structure in a first dielectric layer, the first conductive structure having a honeycomb pattern. An insulator structure is on the first conductive structure of the first metallization layer. A second metallization layer is above the first metallization layer, the second metallization layer having a second conductive structure in a second dielectric layer, the second conductive structure on the insulator structure, and the second conductive structure having the honeycomb pattern.

Abstract: Metal-insulator-metal (MIM) capacitor, an integrated semiconductor device having a MIM capacitor and methods of making. The MIM capacitor includes a first metal layer, a second metal layer and a dielectric layer located between the second metal layer and the first metal layer. The first metal layer, the second metal layer and the dielectric layer may be formed in a comb structure, wherein the comb structure include a first tine structure and at least a second tine structure.

Abstract: A radio-frequency module (1) includes a module substrate (70) having major surfaces (701 and 702) opposite to each other, external connection terminals (90a and 90b) disposed on the major surface (702), a power amplifier (11) having major surfaces (111 and 112) opposite to each other and being disposed on the major surface (702) such that the major surface (111) is a mounting surface on the module substrate (70), a bonding wire (45) coupled to the major surface (112), and a heat dissipation electrode (91) disposed apart from the power amplifier (11) on the major surface (112) side with respect to the power amplifier (11) and coupled to the bonding wire (45).

Abstract: A first-tier capacitor assembly is formed, which includes a first alternating layer stack embedded within a first substrate and including at least two first metallic electrode layers interlaced with at least one first node dielectric layer, and first metallic bonding pads located on a first front surface. A second-tier capacitor assembly is formed, which includes a second alternating layer stack embedded within a second substrate and including at least two second metallic electrode layers interlaced with at least one second node dielectric layers, and second metallic bonding pads located on a second backside surface. The second metallic bonding pads are bonded to the first metallic bonding pads such that each of the at least two first metallic electrode layers contacts a respective one of the at least two second metallic electrode layers. A capacitor with increased capacitance is provided.

Abstract: A semiconductor structure includes: a pad structure disposed above a substrate; and a capacitor structure which is disposed between the substrate and the pad structure, is arranged to be opposite to the pad structure, and includes at least two capacitor units connected in parallel and spaced apart from each other, each of the capacitor units includes at least one capacitor device.

Abstract: A capacitor structure comprises a substrate having a first side, a second side opposite to the first side and an upper surface corresponding to the first side; a plurality of first trenches formed on the first side of the substrate, disposed along a first direction and a second direction parallel to the upper surface, and penetrating the substrate along a third direction, the first direction, the second direction and the third direction orthogonal to each other; a plurality of second trenches formed on the second side of the substrate and penetrating the substrate along the third direction, the first trenches and the second trenches separated from each other in the first direction; a first capacitor extending along the first side and into the first trenches; and a second capacitor extending along the second side and into the second trenches.

Abstract: A semiconductor device includes a substrate, an interlayer insulating layer covering an upper surface of the substrate, an individual device in the interlayer insulating layer, a lower insulating layer covering a lower surface of the substrate, a through-silicon-via (TSV) structure extending through the substrate, the interlayer insulating layer and the lower insulating layer, a conductive pad connected to an upper end of the TSV structure, a via insulating layer surrounding the TSV structure, a capping insulating layer surrounding the TSV structure outside the via insulating layer. The via insulating layer and the capping insulating layer have an air gap therebetween. A portion of the air gap extends into the lower insulating layer.

Abstract: Aspects of the present inventive concept provide a semiconductor device capable of enhancing performance and reliability through source/drain engineering in a transistor including an oxide semiconductor layer. The semiconductor device includes a substrate, a metal oxide layer disposed on the substrate, a source/drain pattern being in contact with the metal oxide layer and including a portion protruding from a top surface of the metal oxide layer, a plurality of gate structures disposed on the metal oxide layer with the source/drain pattern interposed therebetween and each including gate spacers and an insulating material layer, the insulating material layer being in contact with the metal oxide layer, and not extending along a top surface of the source/drain pattern, and a contact disposed on the source/drain pattern, the contact being connected to the source/drain pattern.

Abstract: A superconducting input and/or output system employs at least one microwave superconducting resonator. The microwave superconducting resonator(s) may be communicatively coupled to a microwave transmission line. Each microwave superconducting resonator may include a first and a second DC SQUID, in series with one another and with an inductance (e.g., inductor), and a capacitance in parallel with the first and second DC SQUIDs and inductance. Respective inductive interfaces are operable to apply flux bias to control the DC SQUIDs. The second DC SQUID may be coupled to a Quantum Flux Parametron (QFP), for example as a final element in a shift register. A superconducting parallel plate capacitor structure and method of fabricating such are also taught.

Abstract: A semiconductor module parallel circuit includes: a plurality of power semiconductor modules; and a multilayer substrate that interconnects the plurality of power semiconductor modules, each of the power semiconductor modules includes: a power semiconductor switching element; a first signal terminal connected to a gate potential of the power semiconductor switching element; and a second signal terminal connected to a source potential of the power semiconductor switching element, the multilayer substrate includes: an external connection terminal; first signal terminal connection patterns connected to the first signal terminals of the power semiconductor modules; and second signal terminal connection patterns connected to the second signal terminals of the power semiconductor modules, and inductances of gate wiring for the plurality of power semiconductor modules, from the external connection terminal to the first signal terminal connection pattern and from the second signal terminal connection pattern to the e

Abstract: A semiconductor device in a first area includes first non-planar semiconductor structures separated with a first distance, and a first isolation region including a first layer and a second layer that collectively embed a lower portion of each of the first non-planar semiconductor structures. At least one of the first layer or second layer of the first isolation region is in a cured state. The semiconductor device in a second area includes second non-planar semiconductor structures separated with a second distance, and a second isolation region including a first layer and a second layer that collectively embed a lower portion of each of the second non-planar semiconductor structures. At least one of the first or second layer of the second isolation region is in a cured state.

Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.

Abstract: A semiconductor device has a substrate and a first semiconductor layer with a high resistivity, such as an epitaxial layer with a resistivity in the range of 3000-5000 ohms/cm2, formed over the substrate. A second semiconductor layer is formed at least partially in the first semiconductor layer. A capacitor is formed at least partially over the first semiconductor layer. The capacitor has a plurality of trenches extending through the first semiconductor layer and into the substrate, and a first insulating layer formed in the trench. The trenches can be parallel, serpentine, or other geometric shape. The capacitor also has a second insulating layer formed over the first insulating layer, and a polysilicon layer formed over the second insulating layer. A conductive layer is formed over the capacitor. The first semiconductor layer with high resistivity provides a vertical path to discharge high voltage events incident on the capacitor.

Abstract: A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region. At least a majority of channel material of the dummy channel-material strings is replaced in the TAV region with insulator material and operative TAVs are formed in the TAV region. Other methods and structures independent of method are disclosed.

Abstract: A display apparatus includes a plurality of pixels each including a substrate on which are disposed: an interlayer insulating layer; a driving thin film transistor in which a driving semiconductor layer and a driving gate electrode are each disposed between the substrate and the first interlayer insulating layer; a first capacitor in which a first electrode, a first dielectric pattern and a second electrode are sequentially stacked, the first electrode being connected to the driving gate electrode; and a plurality of contact plugs extended through a thickness of the interlayer insulating layer, with which the driving thin film transistor and the first capacitor are respectively connected to electrodes outside thereof. Lateral surfaces of the first dielectric pattern are covered by the interlayer insulating layer, and the first dielectric pattern within the first capacitor is disposed spaced apart from each of the contact plugs.

Abstract: In an embodiment, a device includes: a semiconductor die including a semiconductor material; a through via adjacent the semiconductor die, the through via including a metal; an encapsulant around the through via and the semiconductor die, the encapsulant including a polymer resin; and an adhesion layer between the encapsulant and the through via, the adhesion layer including an adhesive compound having an aromatic compound and an amino group, the amino group bonded to the polymer resin of the encapsulant, the aromatic compound bonded to the metal of the through via, the aromatic compound being chemically inert to the semiconductor material of the semiconductor die.

Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.

Abstract: A semiconductor device includes a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, a first mesa isolation on the HEMT region, a HEMT on the first mesa isolation, a second mesa isolation on the capacitor region, and a capacitor on the second mesa isolation. The semiconductor device further includes buffer layer between the substrate, the first mesa isolation, and the second mesa isolation, in which bottom surfaces of the first mesa isolation and the second mesa isolation are coplanar.

Abstract: The present disclosure provides a method of manufacturing a capacitor connecting line of a memory and a memory. The method of manufacturing includes: forming a bit line layer and a first dielectric layer on a substrate sequentially; patterning the bit line layer and the first dielectric layer, and forming bit line structures arranged at intervals along a first direction and dielectric structures on tops of the bit line structures; forming an insulating layer on the substrate with the bit line structures and the dielectric structures formed thereon, to completely cover the bit line structures and the dielectric structures; forming second isolation structures arranged at intervals between adjacent bit line structures; and forming conductive structures between first isolation structures and the second isolation structures, and forming storage node contact structures.

Abstract: A multi-die package structure with an embedded die embedded in a substrate, a flip chip die mounted above the substrate, and an attached die attached onto the flip chip die. The package is compact and low cost.

Abstract: A display device includes a plurality of pixels arranged in a matrix on a substrate along a first direction and a second direction intersecting the first direction. Each of the plurality of pixels includes a transistor, a first transparent electrode located over the transistor and electrically connected to the transistor, a second transparent electrode located over the first transparent electrode and electrically connected to the first transparent electrode via an opening, an insulating layer located over the second transparent electrode, a third transparent electrode located over the insulating layer; and a metal layer in contact with the third transparent electrode. The opening overlaps a gate electrode of the transistor. At least a part of the metal layer is provided in the opening and overlaps the gate electrode. The metal layer extends along the first direction and is commonly provided in the pixels arranged in the first direction.

Abstract: A semiconductor structure includes a first substrate having a wiring structure, a first semiconductor die disposed on the first substrate, and a multi-terminal capacitor structure disposed on the first substrate. The multi-terminal capacitor includes a second substrate, an insulating layer disposed over the second substrate, a first multi-terminal capacitor disposed over the insulating layer and electrically coupled to the first semiconductor die through the wiring structure, and a second multi-terminal capacitor disposed over the insulating layer and electrically coupled to the second semiconductor die through the wiring structure, wherein the first multi-terminal capacitor and the second multi-terminal capacitor are electrically isolated from the second substrate.

Abstract: A ferroelectric transistor includes a semiconductor channel comprising a semiconductor material, a strained and/or defect containing ferroelectric gate dielectric layer located on a surface of the semiconductor channel, a source region located on a first end portion of the semiconductor channel, and a drain region located on a second end portion of the semiconductor channel.

Abstract: A semiconductor device includes an n? type layer on a first surface of the substrate, a p type region on a part of the n? type layer, a gate on the n? type layer and the p type region, a first gate protection layer on the gate and a second gate protection layer on the first gate protection layer, a source on the second gate protection layer and the p type region, and a drain on the second surface of the substrate.

Abstract: A display apparatus includes a display panel, a gate driver, a data driver and an emission driver. The display panel includes a pixel. The gate driver provides a gate signal to the pixel. The data driver provides a data voltage to the pixel. The emission driver provides an emission signal to the pixel. The pixel includes a light emitting element, a driving switching element which applies a driving current to the light emitting element, a storage capacitor connected to a control electrode of the driving switching element and a bias capacitor including a first electrode connected to the storage capacitor and a second electrode which receives a bias gate signal. A waveform of the bias gate signal varies based on an off ratio representing a ratio of an off period of the emission signal in a frame period.

Abstract: A device including a first structure and a second structure is provided.

Abstract: A semiconductor device includes; an active region extending in a first horizontal direction on a substrate, source/drain regions disposed on the active region, a buried trench formed between the source/drain regions, a buried insulating layer surrounding both side walls of the buried trench in the first horizontal direction between the source/drain regions, a wing trench formed in a lower part of the buried trench and having a width greater than a width of the buried trench, and a gate electrode extending in a second horizontal direction on the active region, and disposed within each of the buried trench and the wing trench.

Abstract: A device structure according to the present disclosure includes a passivation layer, a first conductor plate layer disposed on the passivation layer, a second conductor plate layer disposed over the first conductor layer, a third conductor plate layer disposed over the second conductor layer, and a fourth conductor plate layer disposed over the third conductor layer. The second conductor plate layer encloses the first conductor plate layer and the fourth conductor plate layer encloses the third conductor plate layer. The device structure, when used in a back-end-of-line passive device, reduces leakage and breakdown due to corner discharge effect.

Abstract: The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.