Both Terminals Of Capacitor Isolated From Substrate Patents (Class 257/535)
  • Patent number: 10181818
    Abstract: A low-noise amplifier (LNA), a folded low-noise amplifier (folded LNA) and an amplifier circuit module are provided. The LNA includes a plurality of radio frequency (RF) input stages, at least one bias transistor and at least one radio frequency (RF) output stage. The bias transistor is connected to the RF input stages to provide a DC bias source to one of the RF input stages for isolating others of the RF input stages. The RF output stage is connected in parallel with the RF input stages, which share an adjustable input inductor.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: January 15, 2019
    Assignee: AIROHA TECHNOLOGY CORP.
    Inventors: Heng-Chih Lin, Chien-Kuang Lee, Yao-Te Chiu
  • Patent number: 9691912
    Abstract: In one embodiment, a device includes a substrate having a top surface and cavity that defines generally vertical walls, a thin film of material that has been deposited on the walls of the cavity, and a further material that fills the cavity, wherein a top edge of the thin film is exposed and forms a trace that is flush with the top surface of the substrate and has substrate material on one side and the further material on the other side.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: June 27, 2017
    Assignee: University of South Florida
    Inventors: Jing Wang, I-Tsang Wu
  • Patent number: 9456493
    Abstract: A touch-sensor structure includes a substrate having a plurality of grooves formed thereon. A plurality of first axial electrode strips are disposed in the grooves individually. A plurality of second axial electrode strips are disposed on the substrate and intersect with the first axial electrode strips. An insulating layer fills in the grooves and is disposed at the intersections of the first and second axial electrode strips. Furthermore, the manufacturing method of the touch-sensor structure is provided. The insulating layer is disposed in the grooves of the substrate without a protuberant height on the substrate. Therefore, it can overcome a breakage issue in conventional conductive bridges.
    Type: Grant
    Filed: October 27, 2013
    Date of Patent: September 27, 2016
    Assignee: TPK Touch Solutions (Xiamen) Inc.
    Inventors: Qiong Yuan, Jing Yu, Hongyan Lian, Pingping Huang
  • Patent number: 9395835
    Abstract: Capacitively actuated touch sensor units are integrated between subpixel light emitters of a liquid crystal display panel. In one embodiment, a sensor unit is monolithically integrated on a same substrate as are a plurality of associated subpixel units and the sensor unit includes a variable capacitor and a reference capacitor connected to define a voltage splitting circuit having a split voltage generating node. The sensor unit also includes a sensing transistor operatively coupled to the split voltage generating node and a voltage resetting transistor operatively coupled to the split voltage generating node. In one embodiment, one plate of the variable capacitor is defined by a touchwise flexed portion of a common electrode of the display and an opposed plate is defined by a spaced apart facing electrode provided on a TFT array substrate of the liquid crystal display.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: July 19, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sang-Yong No, Sang-Youn Han, Young-Je Cho
  • Patent number: 9159506
    Abstract: A power conversion device for a vehicle includes: a power module that includes a switching device and, upon operation of the switching device, converts DC power into AC power to be supplied to an electric machine for driving a vehicle; a capacitor module that includes a smoothing capacitor element, an input-side power source terminal for receiving DC power, and an output-side power source terminal for supplying DC power to the power module; and a noise removal capacitor for removing noise, wherein: the noise removal capacitor is built in the capacitor module, and the noise removal capacitor is electrically connected to the input-side power source terminal in a position where a distance between a connection position of the noise removal capacitor and the input-side power source terminal is less than a distance between a connection position of the noise removal capacitor and the output-side power source terminal of the capacitor module.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: October 13, 2015
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Takeshi Matsuo, Kinya Nakatsu, Toshiya Satoh, Ken Maeda
  • Patent number: 9035424
    Abstract: A semiconductor device includes a substrate, a metal film on a portion of the substrate, a first dielectric film having a first portion on the metal film and a second portion on the substrate, the second portion being integral with the first portion, a lower electrode on the first portion, a second dielectric film having a first portion on the lower electrode and a second portion on the first dielectric film, the second portion of the second dielectric film being integral with the first portion of said second dielectric film, an upper electrode on a portion of the second dielectric film, and a reinforcing film disposed on the second dielectric film and in contact with a side of the upper electrode.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: May 19, 2015
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Masahiro Totsuka
  • Publication number: 20150115409
    Abstract: A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor having a first electrode layer, a second electrode layer, and an insulating layer between the first electrode layer and the second electrode layer. At least three dielectric layers are between a bottom surface of the capacitor and the active region.
    Type: Application
    Filed: October 25, 2013
    Publication date: April 30, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Chern-Yow Hsu
  • Publication number: 20150102464
    Abstract: Disclosed herein are a capacitor with a hole structure and a manufacturing method thereof. A capacitor with a hole structure includes: a substrate layer having a plurality of through-holes formed therein; a lower electrode layer including a first conductive layer having a low specific resistance and a second conductive layer having a specific resistance higher than that of the first conductive layer, the first conductive layer being formed on an inner wall of the through-hole and the second conducive layer being formed on the first conductive layer; a thin film dielectric layer formed on the lower electrode layer; and an upper electrode layer including a third conductive layer and a fourth conductive layer having a specific resistance lower than that of the third conductive layer, the third conductive layer being formed on the thin film dielectric layer and the fourth conductive layer being formed on the third conductive layer.
    Type: Application
    Filed: October 11, 2013
    Publication date: April 16, 2015
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Young Sik KANG, Yeong Gyu LEE
  • Patent number: 9000562
    Abstract: A method for forming a metal-insulator-metal (MIM) capacitor includes forming a capacitor bottom plate and a metal interconnect feature on a substrate. A dielectric layer having a predetermined thickness is then formed. The dielectric layer has a first portion overlying the capacitor bottom plate and a second portion overlying the metal interconnect feature. The dielectric layer is processed to adjust the thickness of the first portion of the dielectric layer relative the thickness of the second portion of the dielectric layer. Processing can include etching the first portion of the dielectric layer or adding dielectric material to the second portion of the dielectric layer. A capacitor top plate is formed over the first portion of the dielectric layer to complete the MIM structure.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shean-Ren Horng, Kuo-Nan Hou, Feng-Liang Lai
  • Publication number: 20150091135
    Abstract: A semiconductor device includes an insulating layer formed on a substrate, and a capacitor including first and second electrodes formed in the insulating layer, wherein a lower surface of the first electrode is formed to have a greater depth than a lower surface of the second electrode in the insulating layer.
    Type: Application
    Filed: March 5, 2014
    Publication date: April 2, 2015
    Applicant: SK hynix Inc.
    Inventors: Sung Lae OH, Chang Man SON, Sang Hyun SUNG, Dae Hun KWAK
  • Patent number: 8963286
    Abstract: A finger metal oxide metal (MOM) capacitor includes an outer conducting structure defined in a plurality of metal layers and a plurality of via layers of an integrated circuit. First and second side portions include a plurality of first and second finger sections extending in the plurality of metal layers and first and second hole vias connecting the first and second finger sections, respectively. A middle portion connects the first and second side portions. An inner conducting structure is defined in the plurality of metal layers and the plurality of via layers of the integrated circuit. A plurality of “T”-shaped sections are defined in the plurality of metal layers and third hole vias connecting the plurality of “T”-shaped sections. Middle portions of the plurality of “T”-shaped sections extend towards the middle portion and between the first side portion and the second side portion of the outer conducting structure.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: February 24, 2015
    Assignee: Marvell International Ltd.
    Inventors: Hung Sheng Lin, Shingo Hatanaka, Shafiq M. Jamal
  • Publication number: 20150049537
    Abstract: An electronic device includes a semiconductor device that includes: a substrate including a switching element having a buried gate electrode; a buried decoupling capacitor having a line width same as a line width of the buried gate electrode; and a variable resistance element, electrically coupled to the switching element, formed over the substrate.
    Type: Application
    Filed: July 2, 2014
    Publication date: February 19, 2015
    Inventors: Joon-Seop Sim, Seok-Pyo Song, Jae-Yun Yi
  • Patent number: 8946044
    Abstract: A lower electrode includes a metal-containing oxide layer having a thickness of 2 nm or less on the surface layer. A metal-containing oxide layer is formed by oxidizing the surface of the lower electrode. A dielectric film includes a first phase appearing at room temperature in the bulk state and a second phase appearing at a higher temperature than that in the first phase in the bulk state. The second phase has a higher relative permittivity than that of the first phase.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: February 3, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Takayuki Iwaki, Takamasa Itou, Kana Shimizu
  • Patent number: 8933514
    Abstract: The orientation polarization (positive and negative) of the Si—N bonds and the Si—O bonds is canceled, thereby enabling to minimize the polarization in a capacitive insulating film. As a result, a silicon oxynitride film with a small voltage secondary coefficient is formed, and is applied as a capacitive insulating film for use in a MIM capacitor. Specifically, the refractive index “n” of the silicon oxynitride film satisfies 1.47?n?1.53, for light with a wavelength of 633 nm.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: January 13, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Kiyohiko Sato, Ryohei Maeno, Tsuyoshi Fujiwara, Akira Otaguro, Yukino Ishii, Kiyomi Katsuyama, Hidenori Sato, Daichi Matsumoto
  • Patent number: 8883606
    Abstract: In accordance with the teachings described herein, a multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same are provided. The multi-level thin film capacitor (MLC) may include at least one high permittivity dielectric layer between at least two electrode layers, the electrode layers being formed from a conductive thin film material. A buffer layer may be included between the ceramic substrate and the thin film MLC. The buffer layer may have a smooth surface with a surface roughness (Ra) less than or equal to 0.08 micrometers (um).
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: November 11, 2014
    Assignee: BlackBerry Limited
    Inventors: Ivoyl P. Koutsaroff, Mark Vandermeulen, Andrew Vladimir Claude Cervin, Atin J. Patel
  • Patent number: 8884400
    Abstract: A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying the passivation layer, wherein the bottom capacitor includes the metal pad. The capacitor further includes a top capacitor electrode over the portion of the passivation layer; and a capacitor insulator including the portion of the passivation layer.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo, Tung-Liang Shao, Ying-Ju Chen, Tsung-Yuan Yu, Jie Chen
  • Patent number: 8878340
    Abstract: Devices or systems that include a composite thermal capacitor disposed in thermal communication with a hot spot of the device, methods of dissipating thermal energy in a device or system, and the like, are provided herein. In particular, the device includes a composite thermal capacitor including a phase change material and a high thermal conductivity material in thermal communication with the phase change material. The high thermal conductivity material is also in thermal communication with an active regeneration cooling device. The heat from the composite thermal capacitor is dissipated by the active regeneration cooling device.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: November 4, 2014
    Assignee: Georgia Tech Research Corporation
    Inventors: Andrei G. Fedorov, Craig Green, Yogendra Joshi
  • Patent number: 8860099
    Abstract: A solid-state imaging device includes a first-conductivity-type semiconductor well region, a plurality of pixels each of which is formed on the semiconductor well region and is composed of a photoelectric conversion portion and a pixel transistor, an element isolation region provided between the pixels and in the pixels, and an element isolation region being free from an insulation film and being provided between desired pixel transistors.
    Type: Grant
    Filed: September 14, 2010
    Date of Patent: October 14, 2014
    Assignee: Sony Corporation
    Inventors: Keiji Tatani, Fumihiko Koga, Takashi Nagano
  • Patent number: 8853823
    Abstract: The capacitor of a nonvolatile memory device includes first and second electrodes formed in the capacitor region of a semiconductor substrate to respectively have consecutive concave and convex shape of side surfaces formed along each other and a dielectric layer formed between the first and the second electrodes.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: October 7, 2014
    Assignee: SK Hynix Inc.
    Inventor: Je il Ryu
  • Patent number: 8847359
    Abstract: High voltage bipolar transistors built with a BiCMOS process sequence exhibit reduced gain at high current densities due to the Kirk effect. Threshold current density for the onset of the Kirk effect is reduced by the lower doping density required for high voltage operation. The widened base region at high collector current densities due to the Kirk effect extends laterally into a region with a high density of recombination sites, resulting in an increase in base current and drop in the gain. The instant invention provides a bipolar transistor in an IC with an extended unsilicided base extrinsic region in a configuration that does not significantly increase a base-emitter capacitance. Lateral extension of the base extrinsic region may be accomplished using a silicide block layer, or an extended region of the emitter-base dielectric layer. A method of fabricating an IC with the inventive bipolar transistor is also disclosed.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: September 30, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Scott Gerard Balster, Hiroshi Yasuda, Philipp Steinmann, Badih El-Kareh
  • Patent number: 8841748
    Abstract: A dielectric wafer has, on top of its front face, a front electrical connection including an electrical connection portion. A blind hole passes through from a rear face of the wafer to at least partially reveal a rear face of the electrical connection portion. A through capacitor is formed in the blind hole. The capacitor includes a first conductive layer covering the lateral wall and the electrical connection portion (forming an outer electrode), a dielectric intermediate layer covering the first conductive layer (forming a dielectric membrane), and a second conductive layer covering the dielectric intermediate layer (forming an inner electrode). A rear electrical connection is made to the inner electrode.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: September 23, 2014
    Assignee: STMicroelectronics SA
    Inventors: Sylvain Joblot, Alexis Farcy, Jean-Francois Carpentier, Pierre Bar
  • Patent number: 8841749
    Abstract: A main blind hole is formed in a front face of a wafer having a rear face. A through capacitor is formed in the main blind hole including a conductive outer electrode, a dielectric intermediate layer, and a filling conductive material forming an inner electrode. Cylindrical portions of the outer electrode, the dielectric intermediate layer and the inner electrode have front ends situated in a plane of the front face of the wafer. A secondary rear hole is formed in the rear face of the wafer to reveal a bottom of the outer electrode. A rear electrical connection is made to contact the bottom of the outer electrode through the secondary rear hole. A through hole via filled with a conductive material is provided adjacent the through capacitor. An electrical connection is made on the rear face between the rear electrical connection and the through hole via.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: September 23, 2014
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Sylvain Joblot, Alexy Farcy, Jean-Francois Carpentier, Pierre Bar
  • Patent number: 8829648
    Abstract: A semiconductor package includes a semiconductor element, a capacitor, and a package substrate. The capacitor supplies transient current to the semiconductor element. The semiconductor element and the capacitor are mounted on the package substrate. The semiconductor element includes an integrated circuit, a first connecting part, and a second connecting part. The capacitor includes a third connecting part and a fourth connecting part. The package substrate includes a first metallic layer, a second metallic layer, and a dielectric layer. The first metallic layer includes a first conductive region, a second conductive region, a third conductive region, and a fourth conductive region. The first conductive region is connected via a fifth connecting part to the second metallic layer. The third conductive region is connected via a sixth connecting part to the second metallic layer. The second and fourth conductive regions are connected to each other inside the first metallic layer.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: September 9, 2014
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Daisuke Iguchi
  • Patent number: 8823136
    Abstract: A set of metal line structures including a signal transmission metal line and a capacitively-grounded inductively-signal-coupled metal line is embedded in a dielectric material layer. A capacitor is serially connected between the capacitively-grounded inductively-signal-coupled metal line and a local electrical ground, which may be on the input side or on the output side. The set of metal line structures and the capacitor collective provide a frequency dependent inductor. The Q factor of the frequency dependent inductor has multiple peaks that enable the operation of the frequency dependent inductor at multiple frequencies. Multiple capacitively-grounded inductively-signal-coupled metal lines may be provided in the frequency-dependent inductor, each of which is connected to the local electrical ground through a capacitor. By selecting different capacitance values for the capacitors, multiple values of the Q-factor may be obtained in the frequency dependent inductor at different signal frequencies.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Hanyi Ding, Wayne H. Woods
  • Patent number: 8810007
    Abstract: A wiring board provided with a silicon substrate including a through hole that communicates a first surface and a second surface of the silicon substrate. A capacitor is formed on an insulating film, which is applied to the silicon substrate, on the first surface and a wall surface defining the through hole. A capacitor part of the capacitor includes a first electrode, a dielectric layer, and a second electrode that are sequentially deposited on the insulating film on the first surface and the wall surface of the through hole. A penetration electrode is formed in the through hole covered by the first electrode, the dielectric layer, and the second electrode of the capacitor part.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: August 19, 2014
    Assignees: Shinko Electric Industries Co., Ltd., Taiyo Yuden Co., Ltd.
    Inventors: Akihito Takano, Masahiro Sunohara, Hideaki Sakaguchi, Mitsutoshi Higashi, Kenichi Ota, Yuichi Sasajima
  • Patent number: 8810002
    Abstract: A capacitor includes a first electrode. The first electrode includes a bottom conductive plane and a plurality of first vertical conductive structures. The bottom conductive plane is disposed over a substrate. The capacitor includes a second electrode. The second electrode includes a top conductive plane and a plurality of second vertical conductive structures. The capacitor includes an insulating structure between the first electrode and the second electrode. The first vertical conductive structures and the second vertical conductive structures are interlaced with each other thereby providing higher capacitance density.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: August 19, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chewn-Pu Jou, Chen Ho-Hsiang, Fred Kuo, Tse-Hul Lu
  • Patent number: 8791518
    Abstract: A method for manufacturing a semiconductor device is disclosed. In the method for manufacturing the semiconductor device, a capacitor structure is modified to ensure capacitance of the capacitor, and the height of the capacitor is reduced to prevent defects such as a leaning capacitor or a poor bridge from being generated, such that the fabrication process of semiconductor devices is simplified and therefore the semiconductor devices can be stably manufactured.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: July 29, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang Heon Kim
  • Patent number: 8759893
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a surface that is defined by a first axis and a second axis perpendicular to the first axis; and a capacitor disposed on the substrate, the capacitor having an anode component that includes a plurality of first conductive features and a cathode component that includes a plurality of second conductive features. The first conductive features and the second conductive features each include two metal lines extending along the first axis. At least one metal via extending along a third axis that is perpendicular to the surface of the substrate and interconnecting the two metal lines. The first conductive features are interdigitated with the second conductive features along both the second axis and the third axis.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: June 24, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsiu-Ying Cho
  • Patent number: 8754462
    Abstract: A semiconductor device includes a first electrode electrically connected to an upper surface of a semiconductor element, a first internal electrode electrically connected to a lower surface of the semiconductor element and having a plurality of first comb finger portions and a first connection portion connecting the plurality of first comb finger portions together, a second electrode electrically connected to the first internal electrode, a second internal electrode electrically connected to a lower surface of the first electrode and having a plurality of second comb finger portions and a second connection portion connecting the plurality of second comb finger portions together, the plurality of second comb finger portions being interdigitated with but not in contact with the plurality of first comb finger portions, and a lower dielectric filling the space between the plurality of first comb finger portions and the plurality of second comb finger portions.
    Type: Grant
    Filed: January 3, 2013
    Date of Patent: June 17, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Noboru Miyamoto, Yoshikazu Tsunoda
  • Publication number: 20140145307
    Abstract: A seal ring structure of an integrated circuit includes a seal ring and a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes a top electrode, a bottom electrode disposed below the top electrode, and a first insulating layer disposed between the top electrode and the bottom electrode. The MIM capacitor is disposed within the seal ring and the MIM capacitor is insulated from the seal ring.
    Type: Application
    Filed: January 17, 2013
    Publication date: May 29, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Tung-Liang Shao, Ching-Jung Yang, Yu-Chia Lai, Hao-Yi Tsai, Tsung-Yuan Yu
  • Publication number: 20140117501
    Abstract: A differential MOS capacitor structure includes two capacitor sections coupled to different gates and operating using different signals. The respective signals may be 180° out of phase. The capacitor sections of the differential capacitor each include two or more upper capacitor plates disposed over a single common lower capacitor plate which serves as a common node thereby preventing parasitic capacitance. The upper capacitor plates of a first capacitor section are adjacent one another with no electrical components disposed between them. The upper capacitor plates of a second capacitor section are adjacent one another with no electrical components disposed between them. The upper capacitor plates are formed of a plurality of stacked conductive layers in some embodiments.
    Type: Application
    Filed: October 25, 2012
    Publication date: May 1, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsiao-Tsung YEN, Yu-Ling LIN, Chin-Wei KUO, Min-Chie JENG
  • Patent number: 8680649
    Abstract: A multi-layer capacitor of staggered construction is formed of one or more layers having tapered sidewall(s). The edge(s) of the capacitor film(s) can be etched to have a gentle slope, which can improve adhesion of the overlying layers and provide more uniform film thickness. The multi-layer capacitor can be used in various applications such as filtering and decoupling.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: March 25, 2014
    Assignee: STMicroelectronics (Tours) SAS
    Inventor: Guillaume Guégan
  • Patent number: 8679937
    Abstract: A method for fabricating a capacitor includes providing a substrate having a first surface and a second surface, and forming a plurality of openings in the substrate, the openings are separated from each other by a shape of the substrate, each opening having sidewalls and a bottom. The method further includes submitting the substrate including the openings to an oxidation process to form an oxide layer covering the sidewalls and the bottom of the openings, and a portion of a surface of the substrate, wherein a shape of the substrate disposed between a pair of two adjacent openings is completely oxidized to form an insulation layer between the pair of two adjacent openings; and depositing a conductive material layer over the oxide layer in the openings such that the conductive material layer is electrically continuous and such that the pair of adjacent openings form a capacitor.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: March 25, 2014
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Yefang Zhu, Liangliang Guo, Herb Huang
  • Patent number: 8669643
    Abstract: A wiring board includes a silicon substrate with a through hole communicating with first and second substrate surfaces. A capacitor includes a capacitor part mounted on an insulating film covering the substrate first surface and including a first electrode on the insulating film, a first dielectric layer on the first electrode, and a second electrode on the first dielectric layer. A multilayer structure arranged on a wall surface defining the through hole includes the insulating film on the through hole wall surface, a first metal layer on the insulating film formed from the same material as the first electrode, a second dielectric layer on the first metal layer formed from the same material as the first dielectric layer, and a second metal layer on the second dielectric layer formed from the same material as the second electrode. The multilayer structure covers a penetration electrode in the through hole.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: March 11, 2014
    Assignees: Shinko Electric Industries Co., Ltd., Taiyo Yuden Co., Ltd.
    Inventors: Akihito Takano, Masahiro Sunohara, Hideaki Sakaguchi, Mitsutoshi Higashi, Kenichi Ota, Yuichi Sasajima
  • Publication number: 20140008763
    Abstract: Capacitor device structures can be fabricated on a substrate including multiple separate first electrodes and a common distributed second electrode. The second electrode can be common to the multiple first electrodes and can be distributed in a shape of a grid interdigitating the multiple first electrodes. The distributed nature of the second electrode can replace the substrate backside as the bottom electrode and can reduce the device parasitic characteristics. In some embodiments, the capacitor device structures can be used in a high productivity combinatorial process, wherein the distributed nature of the second electrode can make the test structures more tolerant to misalignment.
    Type: Application
    Filed: July 9, 2012
    Publication date: January 9, 2014
    Applicant: Intermolecular, Inc.
    Inventors: Salil Mujumdar, Amol Joshi
  • Patent number: 8624353
    Abstract: A semiconductor device has a first semiconductor die. A first inductor is formed over the first semiconductor die. A second inductor is formed over the first inductor and aligned with the first inductor. An insulating layer is formed over the first semiconductor die and the first and second inductors. A conductive bridge is formed over the insulating layer and electrically connected between the second inductor and the first semiconductor die. In one embodiment, the semiconductor device has a second semiconductor die and a conductive layer is formed between the first and second semiconductor die. In another embodiment, a capacitor is formed over the first semiconductor die. In another embodiment, the insulating layer has a first thickness over a footprint of the first semiconductor die and a second thickness less than the first thickness outside the footprint of the first semiconductor die.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: January 7, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Kai Liu, Kang Chen
  • Patent number: 8618635
    Abstract: In one embodiment, a capacitor includes a first via level having first metal bars and first vias, such that the first metal bars are coupled to a first potential node. The first metal bars are longer than the first vias. Second metal bars and second vias are disposed in a second via level, the second metal bars are coupled to the first potential node. The second metal bars are longer than the second vias. The second via level is above the first via level and the first metal bars are parallel to the second metal bars. Each of the first metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends. Each of the middle portions of the first metal bars and the second ends of the first metal bars do not contact any metal line.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: December 31, 2013
    Assignee: Infineon Technologies AG
    Inventors: Sunoo Kim, Moosung Chae, Bum Ki Moon
  • Patent number: 8609505
    Abstract: A capacitor structure includes a semiconductor substrate; a first capacitor plate positioned on the semiconductor substrate, the first capacitor plate including a polysilicon structure having a surrounding spacer; a silicide layer formed in a first portion of an upper surface of the first capacitor plate; a capacitor dielectric layer formed over a second portion of the upper surface of the first capacitor plate and extending laterally beyond the spacer to contact the semiconductor substrate; a contact in an interlayer dielectric (ILD), the contact contacting the silicide layer and a first metal layer over the ILD; and a second capacitor plate over the capacitor dielectric layer, wherein a metal-insulator-metal (MIM) capacitor is formed by the first capacitor plate, the capacitor dielectric layer and the second capacitor plate and a metal-insulator-semiconductor (MIS) capacitor is formed by the second capacitor plate, the capacitor dielectric layer and the semiconductor substrate.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: December 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Douglas D. Coolbaugh, Ebenezer E. Eshun, Robert M. Rassel, Anthony K. Stamper
  • Patent number: 8604587
    Abstract: An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (106) is integrated at the top metal interconnect level (104) and includes surface protection cladding (109) for the copper metal (104b) of the top metal interconnect.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: December 10, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Edmund Burke, Satyavolu Srinivas Papa Rao, Timothy Alan Rost
  • Patent number: 8587088
    Abstract: A die package having a vertical stack of dies and side-mounted circuitry and methods for making the same are disclosed, for use in an electronic device. The side-mounted circuitry is mounted to a vertical surface of the stack, as opposed to a top surface or adjacent of the stack to reduce the volume of the NVM package.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: November 19, 2013
    Assignee: Apple Inc.
    Inventor: Nicholas Seroff
  • Patent number: 8575721
    Abstract: A semiconductor device, which exhibits an increased design flexibility for a capacitor element, and can be manufactured with simple method, is provided. A semiconductor device 100 includes: a silicon substrate 101; an interlayer film 103 provided on the silicon substrate 101; a multiple-layered interconnect embedded in the interlayer film 103; a flip-chip pad 111, provided so as to be opposite to an upper surface of an uppermost layer interconnect 105 in the multiple-layered interconnect and having a solder ball 113 for an external coupling mounted thereon; and a capacitance film 109 provided between said uppermost layer interconnect 105 and the flip-chip pad 111. Such semiconductor device 100 includes the flip-chip pad 111 composed of an uppermost layer interconnect 105, a capacitive film 109 and a capacitor element 110.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: November 5, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Ryuichi Okamura
  • Patent number: 8546916
    Abstract: Semiconductor devices, capacitors, and methods of manufacture thereof are disclosed. In one embodiment, a method of fabricating a capacitor includes forming a first material over a workpiece, and patterning the first material, forming a first capacitor plate in a first region of the workpiece and forming a first element in a second region of the workpiece. A second material is formed over the workpiece and over the patterned first material. The second material is patterned, forming a capacitor dielectric and a second capacitor plate in the first region of the workpiece over the first capacitor plate and forming a second element in a third region of the workpiece.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: October 1, 2013
    Assignee: Infineon Technologies AG
    Inventors: Martin Ostermayr, Richard Lindsay
  • Patent number: 8502340
    Abstract: A component includes a substrate and a capacitor formed in contact with the substrate. The substrate can consist essentially of a material having a coefficient of thermal expansion of less than 10 ppm/° C. The substrate can have a surface and an opening extending downwardly therefrom. The capacitor can include at least first and second pairs of electrically conductive plates and first and second electrodes. The first and second pairs of plates can be connectable with respective first and second electric potentials. The first and second pairs of plates can extend along an inner surface of the opening, each of the plates being separated from at least one adjacent plate by a dielectric layer. The first and second electrodes can be exposed at the surface of the substrate and can be coupled to the respective first and second pairs of plates.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: August 6, 2013
    Assignee: Tessera, Inc.
    Inventors: Vage Oganesian, Belgacem Haba, Ilyas Mohammed, Piyush Savalia
  • Patent number: 8492822
    Abstract: A method for manufacturing an LC circuit, including forming a first conductive layer pattern serving as a lower electrode of a capacitor on a first interlayer insulating layer, forming a dielectric layer pattern storing electric charges on the first conductive layer pattern, forming a second conductive layer pattern serving as an upper electrode of the capacitor on the dielectric layer pattern, forming a second interlayer insulating layer on the second conductive layer pattern, forming a contact via exposing one of the first or second conductive layer pattern in the second interlayer insulating layer, and filling the contact via with a contact plug, and forming a third conductive layer pattern on the second interlayer insulating layer having the contact plug, wherein the third conductive layer pattern is electrically connected to the contact plug, and is etched in a metal interconnection type layer and functions as an inductor.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: July 23, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Sung Lim, Chul-Ho Chung
  • Patent number: 8461663
    Abstract: In a conventional semiconductor device, part of a dielectric film of a capacitive element is removed when photoresist is peeled off, and this causes problems of variation in capacitance value of the capacitive element and deterioration of breakdown voltage characteristics. In a semiconductor device according to the present invention, a silicon nitride film serving as a dielectric film is formed on the top face of a lower electrode of a capacitive element, and an upper electrode is formed on the top face of the silicon nitride film. The upper electrode is formed of a laminated structure having a silicon film and a polysilicon film protecting the silicon nitride film. This structure prevents part of the silicon nitride film from being removed when, for example, photoresist is peeled off, thereby preventing variation in capacitance value of the capacitive element and deterioration of the breakdown voltage characteristics.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: June 11, 2013
    Assignees: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.
    Inventors: Reiki Fujimori, Mitsuru Soma
  • Patent number: 8441102
    Abstract: It is an object to provide a semiconductor device integrating various elements without using a semiconductor substrate, and a method of manufacturing the same. According to the present invention, a layer to be separated including an inductor, a capacitor, a resistor element, a TFT element, an embedded wiring and the like, is formed over a substrate, separated from the substrate, and transferred onto a circuit board 100. An electrical conduction with a wiring pattern 114 provided in the circuit board 100 is made by a wire 112 or a solder 107, thereby forming a high frequency module or the like.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: May 14, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Takayama, Junya Maruyama, Yumiko Ohno, Yuugo Goto, Hideaki Kuwabara
  • Publication number: 20130093053
    Abstract: A trench-type PIP capacitor having a small step at the end part of the capacitor without increasing manufacturing cost, and a power integrated circuit device that uses such a trench-type PIP capacitor are disclosed. A method of manufacturing the power integrated circuit device also is disclosed. A trench-type PIP capacitor has a construction, in the surface region of a semiconductor substrate, comprising an isolating insulation layer formed on an inner wall of a trench and a first polysilicon that fills the trench through the isolating insulation layer and becomes a lower electrode. Since this construction has a small step formed at the end region of the capacitor, a metal layer for wiring does not need to be made excessively thick, allowing a fine structure of the metal layer. Therefore, the power IC provided with such a trench-type PIP capacitor can have a fine structure.
    Type: Application
    Filed: October 10, 2012
    Publication date: April 18, 2013
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: FUJI ELECTRIC CO., LTD.
  • Patent number: 8410579
    Abstract: In one embodiment, an integrated circuit (IC) is presented. The IC includes first and second sets of power distribution lines formed in the IC. The IC includes first and second capacitors formed in one or more layers of the IC. A first plurality of vias couple a first input of the first and second capacitors to the first set of power distribution lines, and a second plurality of vias couple a second input of the first and second capacitors to the second set of power distribution lines. The first capacitor and the first plurality of vias and the second plurality of vias coupled thereto having an equivalent series resistance greater than an equivalent series resistance of the second capacitor and the first plurality of vias and the second plurality of vias coupled thereto.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: April 2, 2013
    Assignee: Xilinx, Inc.
    Inventors: Atul V. Ghia, Christopher P. Wyland, Ketan Sodha, Paul T. Sasaki, Jian Tan, Paul Y. Wu, Romi Mayder
  • Patent number: 8410562
    Abstract: A capacitive chemical sensor, along with methods of making and using the sensor are provided. The sensors described herein eliminate undesirable capacitance by etching away the substrate underneath the capacitive chemical sensor, eliminating most of the substrate capacitance and making changes in the chemical-sensitive layer capacitance easier to detect.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: April 2, 2013
    Assignee: Carnegie Mellon University
    Inventors: Nathan Lazarus, Gary Fedder, Sarah Bedair, Chiung Lo
  • Patent number: 8405189
    Abstract: An example of a carbon nanotube capacitor may include (i) a carbon nanotube film having carbon nanotubes and voids with dielectric material, (ii) conductive contacts and (iii) a dielectric layer. The carbon nanotube film may switch from a conductive state to a non-conductive state when a voltage is applied by creating an electrical break within the carbon nanotube film and providing a first conductive region and a second conductive region within the carbon nanotube film. The electrical break may separate the first conductive region from the second conductive region. The first and second conductive regions may store charge. An integrated device may include one or more transistors and one or more carbon nanotube capacitors. A method of making a carbon nanotube capacitor is also disclosed.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: March 26, 2013
    Assignee: Lockheed Martin Corporation
    Inventors: Jonathan W. Ward, Quoc X. Ngo