MEMS pressure sensor and microphone devices having through-vias and methods of forming same
A method embodiment includes providing a MEMS wafer. A portion of the MEMS wafer is patterned to provide a first membrane for a microphone device and a second membrane for a pressure sensor device. A carrier wafer is bonded to the MEMS wafer. The carrier wafer is etched to expose the first membrane and a first surface of the second membrane to an ambient environment. A MEMS structure is formed in the MEMS wafer. A cap wafer is bonded to a side of the MEMS wafer opposing the carrier wafer to form a first sealed cavity including the MEMS structure and a second sealed cavity including a second surface of the second membrane for the pressure sensor device. The cap wafer comprises an interconnect structure. A through-via electrically connected to the interconnect structure is formed in the cap wafer.
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This application claims the benefit of U.S. Provisional Application No. 61/783,475, filed on Mar. 14, 2013 entitled “MEMS Pressure Sensor, Motion Sensor, and Microphone Devices Having Through-Vias and Methods of Forming Same,” which application is hereby incorporated herein by reference.
CROSS-REFERENCE TO RELATED APPLICATIONSThis application relates to the following co-pending and commonly assigned patent applications filed on the same date: “MEMS Integrated Pressure Sensor Devices and Methods of Forming Same” Ser. No. 13/894,821; “MEMS Integrated Pressure Sensor and Microphone Devices and Methods of Forming Same” Ser. No. 13/944,382; “MEMS Integrated Pressure Sensor Devices having Isotropic Cavities and Methods of Forming Same” Ser. No. 13/906,105; and “MEMS Device and Methods of Forming Same” Ser. No. 13/893,058.
BACKGROUNDMicro-electromechanical systems (“MEMS”) are becoming increasingly popular, particularly as such devices are miniaturized and are integrated into integrated circuit manufacturing processes. MEMS devices introduce their own unique requirements into the integration process, however. Electrically interconnecting MEMS devices is an area of unique challenges. In particular, integrating MEMS pressure sensor devices, MEMS microphone devices, and other MEMS devices (e.g., motion sensor devices) into the same integrated circuit manufacturing process has posed challenges.
For a more complete understanding of the present embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The making and using of the present embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosed subject matter, and do not limit the scope of the different embodiments.
Dielectric layer 104 may be formed of a low-k dielectric material, such as silicon dioxide (SiO2). Dielectric layer 104 may be deposited over substrate 102 using, for example, spinning, chemical vapor disposition (CVD), plasma enhanced chemical vapor deposition (PECVD), low pressure CVD, or other suitable deposition techniques. Furthermore, dielectric layer 104 may be formed of a different suitable material such as low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, a polymer such as polyimide, combinations thereof, or the like. Dielectric layer 104 may be released (i.e., removed) in subsequent process steps in order to form MEMS structures; therefore, dielectric layer 104 may also be referred to as oxide release layer 104, sacrificial layer 104, or sacrificial oxide layer 104.
Furthermore, voids (not shown) may or may not be embedded in oxide release layer 104 to decrease oxide release time during a subsequent selective oxide etching process (e.g., vapor HF). Voids may be embedded by depositing and patterning a first portion of oxide release layer 104 to form a plurality of small openings using, for example, a combination of photolithography and etching techniques. The upper portions of the small openings may then be seamed together to seal the small openings, and create voids. The small openings may be seamed together using, for example, an oxide deposition process applied to the upper surface of first portion of oxide release layer 104. For example, the deposition of additional oxide material (i.e., the remaining portion of oxide release layer 104) over the first portion of oxide release layer 104 may be employed to seal off the upper portions of the openings. The oxide deposition may be formed using a deposition process such as CVD or the like. More particularly, by controlling the deposition process, the material of oxide release layer 104 may be deposited in a non-conformable manner. That is, the material of oxide release layer 104 may build up on the upper portions of the small openings faster than along the sidewalls and bottom of the small openings. This process leads to the formation of an overhang at the edge of the upper portion of the small openings, and as the deposition process continues, the overhangs will merge, sealing off the small openings with a plurality of seams and forming voids embedded in oxide release layer 104.
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An oxide mask layer 114 (labeled as 114A and 114B) may be formed and patterned over portions of polysilicon layer 112. Oxide mask layer 114 is formed out of a similar material and using similar methods as oxide release layer 104, and oxide mask layer 114 may be patterned using for example, a combination of photolithography and etching. Oxide mask layer 114 acts as protection for critical portions of polysilicon layer 112 in subsequent process steps. For example, in
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Furthermore, thin polysilicon layer 122 may also act as a shield for various components of MEMS wafer 100 (e.g., substrate 102 and polysilicon layer 112) in subsequent process steps. Thin polysilicon layer 122 may also act as a bonding interface layer; therefore, other suitable bonding materials such as silicon, amorphous silicon, silicon doped with impurities, combinations thereof, and the like may be used in lieu of polysilicon.
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Top surface 100A of MEMS wafer 100 is bonded to top surface 200A of carrier wafer 200. MEMS wafer 100 may be bonded to carrier wafer 200 using any suitable technique such as fusion bonding, anodic bonding, eutectic bonding, and the like. In various embodiments, MEMS wafer 100 may be fusion bonded to carrier wafer 200 using second thin polysilicon layer 122 as a bonding interface.
Furthermore, MEMS wafer 100 may be thinned to a desired thickness T3. The thinning process may include grinding and chemical mechanical polishing (CMP) processes, etch back processes, or other acceptable processes performed on surface 100B of MEMS wafer 100 (i.e., substrate 102). As a result of this thinning process, MEMS wafer 100 may have a thickness between about 5 μm to about 60 μm.
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Device 420 may be a motion sensor that allows for the detection of motion through the disposition of a proof mass (i.e., MEMS structure 208) over an electrode (i.e., portions of polysilicon layer 112) in a sealed cavity defined by the eutectic bond of cap wafer 300 to MEMS wafer 100. Alternatively, device 420 may be an accelerometer, a gyroscope, or the like. The pressure of the sealed cavity containing device 420 may be selected in accordance with a desired functionality of device 420. For example, the sealed cavity may have a pressure between about 100-700 mbar for an accelerometer, between about 10−4 mbar to about 10 mbar for a gyroscope, or the like. Thus, using the various formation steps illustrated in
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Thus, MEMS device 800 is completed. MEMS device 800 includes devices 812 and 814, pressure sensor 816, and microphone 818. Notably, pressure sensor 816 and microphone 818 are disposed on opposite sides of the same MEMS structure 610.
Devices 812 and 814 may be motion sensors, gyroscopes, accelerometers, or the like disposed in sealed cavities defined by the bonding process of cap wafer 700 to MEMS wafer 600. A pressure level of the sealed cavities as defined by the bonding may be selected in accordance with a desired functionality of devices 812 and 814. Devices 812 and 814 may or may not perform the same function.
Pressure sensor 816 includes a membrane of polysilicon layer portion 618C, which is exposed to ambient pressure on one side (via opening 810) and sealed pressure on the other (via cavity 706). Because polysilicon layer portion 618C is uninterrupted, cavity 706 is sealed and not exposed to ambient pressure. The pressure of cavity 706 may be defined by the eutectic bonding process of MEMS wafer 600 to cap wafer 700. Microphone 818 includes a membrane of a portion of polysilicon layer 604, which is exposed to an ambient environment through opening 810. Thus
Although the present embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the features and functions discussed above can be implemented in software, hardware, or firmware, or a combination thereof.
Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Claims
1. A method for forming a micro-electromechanical (MEMS) device comprising:
- providing a device substrate comprising: a first membrane for a microphone device; a second membrane for a pressure sensor device; and a bonding layer formed over the first membrane;
- bonding a carrier substrate to the device substrate using a fusion bonding process performed after the bonding layer is formed, wherein bonding the carrier substrate comprises forming an interface between the bonding layer and a silicon material of the carrier substrate;
- etching the carrier substrate to expose the first membrane for the microphone device and to expose a first surface of the second membrane for the pressure sensor device to an ambient environment;
- patterning the device substrate to form a MEMS structure;
- bonding a cap substrate having an interconnect structure to a side of the device substrate opposing the carrier substrate to form a first sealed cavity including the MEMS structure and a second sealed cavity including a second surface of the second membrane for the pressure sensor device; and
- forming a through-via in the cap substrate, wherein the through-via is electrically connected to the interconnect structure of the cap substrate.
2. The method of claim 1, wherein pressure levels of the first and second sealed cavities are defined by a bonding process between the cap substrate and the device substrate.
3. The method of claim 1, further comprising providing the cap substrate, wherein providing the cap substrate comprises:
- providing a semiconductor substrate having the interconnect structure on a first surface of the semiconductor substrate;
- forming a conforming oxide layer over the interconnect structure; and
- forming a first plurality of bonds over the conforming oxide layer.
4. The method of claim 3, further comprising forming contact plugs electrically connecting at least a portion the first plurality of bonds to the interconnect structure.
5. The method of claim 3, further comprising shallow etching a portion of the conforming oxide layer to form one or more bumps, and wherein bonding the cap substrate to the device substrate comprises aligning the one or more bumps to the MEMS structure.
6. The method of claim 3, wherein bonding the cap substrate the device substrate comprises a eutectic bonding process between the first plurality of bonds and a second plurality of bonds disposed on the side of the device substrate opposing the carrier substrate.
7. The method of claim 3, wherein forming the through via in the cap substrate comprises:
- forming an opening in a second surface of the semiconductor substrate opposing the first surface to expose a portion of the interconnect structure;
- forming a dielectric layer over the second surface of the semiconductor substrate, wherein the dielectric layer covers sidewalls of the opening; and
- forming the through-via over the dielectric layer in the opening, wherein the through via is electrically connected to the interconnect structure.
8. The method of claim 1, wherein the device substrate comprises a first sacrificial layer, wherein forming the MEMS structure comprises removing portions of the first sacrificial layer.
9. The method of claim 8, wherein removing portions of the first sacrificial layer comprises a vapor hydrogen-flouride (vapor HF) etching process.
10. The method of claim 1, wherein the cap substrate comprises active circuits.
11. The method of claim 1, and wherein providing the device substrate further comprises:
- forming a first sacrificial layer over a silicon comprising substrate;
- forming a conductive layer over the first sacrificial layer;
- patterning the conductive layer to form the first and second membranes;
- forming an etch stop layer over a conductive layer;
- forming a second sacrificial layer over the etch stop layer; and
- forming the bonding layer over the second sacrificial layer.
12. The method of claim 1, wherein a polysilicon layer of the MEMS structure is patterned to provide the first and second membranes.
13. The method of claim 1, wherein the bonding layer is a polysilicon layer.
14. A method for forming a micro-electromechanical (MEMS) device comprising:
- providing a device substrate, wherein a first conductive layer in the device substrate is patterned to provide a first membrane for a microphone device;
- bonding a carrier substrate to the device substrate;
- etching the carrier substrate to expose the first membrane to an ambient environment;
- forming first and second MEMS structures by patterning the device substrate, wherein the first MEMS structure is disposed over the first membrane;
- forming a second conductive layer over a surface of the MEMS structure opposing the first conductive layer, wherein a portion of the second conductive layer is disposed over the first MEMS structure and is patterned to provide a second membrane;
- bonding a cap substrate comprising an interconnect structure to the second conductive layer to form first and second sealed cavities, wherein the first sealed cavity includes the second MEMS structure and the second sealed cavity includes a surface of the second membrane for a pressure sensor device; and
- forming a through via in the cap substrate, wherein the through via is electrically connected to the interconnect structure of the cap substrate.
15. The method of claim 14, further comprising forming a third MEMS structure by patterning the device substrate, and wherein the bonding the cap substrate to the second conductive layer defines a third sealed cavity including the third MEMS structure.
16. The method of claim 14, wherein forming the through via in the cap substrate comprises:
- etching an opening in the cap substrate exposing the interconnect structure;
- forming a dielectric layer over the cap substrate, wherein the dielectric layer covers sidewalls of the opening, and wherein the dielectric layer does not cover a bottom surface of the opening; and
- forming the through via over the dielectric layer in the opening, wherein the through via is electrically connected to the interconnect structure.
17. The method of claim 16, wherein the first and second conductive layers are polysilicon layers, and wherein the dielectric layer is an oxide layer.
18. A method comprising:
- providing a device substrate comprising: a first membrane for a first device; a micro-electromechanical (MEMS) structure; and a second membrane for a second device;
- patterning a carrier substrate bonded to the device substrate, wherein patterning the carrier substrate exposes the first membrane and a first surface of the second membrane to an ambient environment;
- bonding a cap substrate to the device substrate, wherein bonding the cap substrate disposes a second surface of the second membrane in a sealed cavity;
- forming a through-via in the cap substrate, wherein forming the through-via comprises: forming an opening in the cap substrate; and forming the through-via in the opening, wherein the through via extends along a sidewall of the opening, and wherein a gap is formed in the opening between portions of the through via; and
- forming an oxide release layer over the through-via and extending into the gap, wherein the oxide release layer comprises a void disposed in the gap, wherein the void is fully enclosed by the oxide release layer, wherein after patterning the carrier substrate, removing the oxide release layer.
19. The method of claim 18, further comprising:
- forming first membrane in a first conductive layer; and
- forming the second membrane in a second conductive layer, wherein the first conductive layer and the second conductive layer are disposed on opposing sides of the MEMS structure.
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Type: Grant
Filed: Jul 31, 2013
Date of Patent: Oct 18, 2016
Patent Publication Number: 20140264653
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. (Hsin-Chu)
Inventors: Chun-Wen Cheng (Zhubei), Chia-Hua Chu (Zhubei)
Primary Examiner: Cuong B Nguyen
Application Number: 13/955,957
International Classification: H01L 21/00 (20060101); B81C 1/00 (20060101);